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113f33b07971d1edbb59958c7effa5f1184be06e
MicrochipFor32/MX_FastSet/T103C8T6/MDK-ARM/template/bsp_printart.o

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更新modbus,更新rtthread
2023-12-15 01:08:04 +08:00
ELF(  4(63@<40>pG<70><47>pGO<47>0pG<0F>p<EFBFBD>F@h<><68><EFBFBD><EFBFBD><14><06><05><><EFBFBD><EFBFBD><EFBFBD>F F<><46><EFBFBD><EFBFBD>F(h!Fh(F<>G F<><46><EFBFBD><EFBFBD>0Fp<46>]<5D><14> <20><>J<><4A>!pGI`<60>!A`pG<00>
F<EFBFBD><EFBFBD><EFBFBD><EFBFBD>I<>``<00><00> FF<><46><EFBFBD><EFBFBD>I<>``<00><00><00>12bsp_PrintArt18bsp_PrintArt_STM32?@AB<00><><EFBFBD>h<EFBFBD>#<23><><EFBFBD><EFBFBD><00>bsp_Device\\bsp_PrintArt.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]C:\Users\XerolySkinner\Desktop\MDK-ARM__asm___16_bsp_PrintArt_cpp_0653a24f___Z7__REV16jX> ..\Drivers\CMSIS\Include\cmsis_armcc.h<03><01>bsp_Device\\bsp_PrintArt.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]C:\Users\XerolySkinner\Desktop\MDK-ARM__asm___16_bsp_PrintArt_cpp_0653a24f___Z7__REVSHsX> ..\Drivers\CMSIS\Include\cmsis_armcc.h<03><01>bsp_Device\\bsp_PrintArt.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]C:\Users\XerolySkinner\Desktop\MDK-ARM__asm___16_bsp_PrintArt_cpp_0653a24f___Z5__RRXjX> ..\Drivers\CMSIS\Include\cmsis_armcc.h<03>&0<00><><EFBFBD><EFBFBD>armcc+|  
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RQ}<00>}Q__DATE__ "Apr 24 2023"__TIME__ "02:21:34"__STDC__ 1__cplusplus 199711L_BOOL 1__ARRAY_OPERATORS 1__IMPLICIT_INCLUDE 1__RTTI 1__EDG_RUNTIME_USES_NAMESPACES 1__EDG_IA64_ABI 1__EDG_IA64_ABI_VARIANT_CTORS_AND_DTORS_RETURN_THIS 1__EDG_IA64_ABI_USE_INT_STATIC_INIT_GUARD 1__EDG_TYPE_TRAITS_ENABLED 1__EDG__ 1__EDG_VERSION__ 407__EDG_SIZE_TYPE__ unsigned int__EDG_PTRDIFF_TYPE__ int__sizeof_int 4__sizeof_long 4__sizeof_ptr 4__ARMCC_VERSION 5060960__TARGET_CPU_CORTEX_M3 1__TARGET_FPU_SOFTVFP 1__TARGET_FPU_SOFTVFP 1__UVISION_VERSION 537_RTE_ 1STM32F10X_MD 1_RTE_ 1USE_HAL_DRIVER 1STM32F103xB 1__CC_ARM 1__arm 1__arm__ 1__TARGET_ARCH_7_M 1__TARGET_ARCH_ARM 0__TARGET_ARCH_THUMB 4__TARGET_ARCH_A64 0__TARGET_ARCH_AARCH32 1__TARGET_PROFILE_M 1__TARGET_FEATURE_HALFWORD 1__TARGET_FEATURE_THUMB 1__TARGET_FEATURE_MULTIPLY 1__TARGET_FEATURE_DOUBLEWORD 1__TARGET_FEATURE_DIVIDE 1__TARGET_FEATURE_UNALIGNED 1__TARGET_FEATURE_CLZ 1__TARGET_FEATURE_DMB 1__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0__APCS_INTERWORK 1__thumb 1__thumb__ 1__t32__ 1__OPTIMISE_SPACE 1__OPT_SMALL_ASSERT 1__OPTIMISE_LEVEL 3__SOFTFP__ 1>%.
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#<23>&ITATBCTR0l#<23>&FIFO1l#<23>&ITCTRL#<23><03>j&&RESERVED5<12>
#<23>&CLAIMSET#<23>&CLAIMCLR#<23><03>j&RESERVED7- #<23>&DEVIDl#<23>&DEVTYPEl#<23>iTPI_Type<12> <01>B<>&DHCSR#&DCRSR#&DCRDR#&DEMCR# iCoreDebug_Typez <01> <03>-<00>ITM_RxBuffer<12> S<><01> __NVIC_SetPriorityGrouping3jPriorityGroupureg_valuejuPriorityGroupTmpjR<><01> __NVIC_GetPriorityGroupingjz__resultjS<><01> __NVIC_EnableIRQ3IRQnR<><01> __NVIC_GetEnableIRQj3IRQnz__resultjS<><01> __NVIC_DisableIRQ3IRQnR<><01> __NVIC_GetPendingIRQj3IRQnz__resultjS<><01> __NVIC_SetPendingIRQ3IRQnS<><01> __NVIC_ClearPendingIRQ3IRQnR<><01> __NVIC_GetActivej3IRQnz__resultjS<><01> __NVIC_SetPriority3IRQn3jpriorityR<><01> __NVIC_GetPriorityj3IRQnz__resultjR<><01> NVIC_EncodePriorityj3jPriorityGroup3jPreemptPriority3jSubPriorityz__resultjuPriorityGroupTmpjuPreemptPriorityBitsjuSubPriorityBitsjS<><01> NVIC_DecodePriority3jPriority3jPriorityGroup3<12>pPreemptPriority3<12>pSubPriorityuPriorityGroupTmpjuPreemptPriorityBitsjuSubPriorityBitsj0jS<><01> __NVIC_SetVector3IRQn3jvectoruvectors<12>R<> <01> __NVIC_GetVectorj3IRQnz__resultjuvectors<12>S<> <01> "__NVIC_SystemResetR<> <01>SCB_GetFPUTypejz__resultjR<>!<01>SysTick_Configj3jticksz__resultjR<>!<01>ITM_SendCharj3jchz__resultjR<>"<01>ITM_ReceiveChar-z__result-uch-R<>"<01>ITM_CheckChar-z__result-L<00> ITM_RxBufferrstu __SYSTEM_STM32F10X_H `W ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]C:\Users\XerolySkinner\Desktop\MDK-ARM<00>SystemCoreClockjK<03><12><00>AHBPrescTable<12><03><12><00>APBPrescTableF$<00>SystemCoreClock<00>AHBPrescTable
APBPrescTablewxy&__STM32F103xB_H 2__CM3_REV 0x0200U3__MPU_PRESENT 0U4__NVIC_PRIO_BITS 4U5__Vendor_SysTickConfig 0U<03><03><03><01>FLASH_BASE 0x08000000UL<01>FLASH_BANK1_END 0x0801FFFFUL<01>SRAM_BASE 0x20000000UL<01>PERIPH_BASE 0x40000000UL<01>SRAM_BB_BASE 0x22000000UL<01>PERIPH_BB_BASE 0x42000000UL<01>APB1PERIPH_BASE PERIPH_BASE<01>APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)<01>AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)<01>TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)<01>TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)<01>TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)<01>RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)<01>WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)<01>IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)<01>SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)<01>USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)<01>USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)<01>I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)<01>I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)<01>CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL)<01>BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL)<01>PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)<01>AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL)<01>EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)<01>GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL)<01>GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL)<01>GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL)<01>GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL)<01>GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL)<01>ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL)<01>ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL)<01>TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)<01>SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)<01>USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)<01>DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)<01>DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL)<01>DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL)<01>DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL)<01>DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL)<01>DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL)<01>DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL)<01>DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL)<01>RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)<01>CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)<01>FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL)<01>FLASHSIZE_BASE 0x1FFFF7E0UL<01>UID_BASE 0x1FFFF7E8UL<01>OB_BASE 0x1FFFF800UL<01>DBGMCU_BASE 0xE0042000UL<01>USB_BASE (APB1PERIPH_BASE + 0x00005C00UL)<01>USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL)<01>TIM2 ((TIM_TypeDef *)TIM2_BASE)<01>TIM3 ((TIM_TypeDef *)TIM3_BASE)<01>TIM4 ((TIM_TypeDef *)TIM4_BASE)<01>RTC ((RTC_TypeDef *)RTC_BASE)<01>WWDG ((WWDG_TypeDef *)WWDG_BASE)<01>IWDG ((IWDG_TypeDef *)IWDG_BASE)<01>SPI2 ((SPI_TypeDef *)SPI2_BASE)<01>USART2 ((USART_TypeDef *)USART2_BASE)<01>USART3 ((USART_TypeDef *)USART3_BASE)<01>I2C1 ((I2C_TypeDef *)I2C1_BASE)<01>I2C2 ((I2C_TypeDef *)I2C2_BASE)<01>USB ((USB_TypeDef *)USB_BASE)<01>CAN1 ((CAN_TypeDef *)CAN1_BASE)<01>BKP ((BKP_TypeDef *)BKP_BASE)<01>PWR ((PWR_TypeDef *)PWR_BASE)<01>AFIO ((AFIO_TypeDef *)AFIO_BASE)<01>EXTI ((EXTI_TypeDef *)EXTI_BASE)<01>GPIOA ((GPIO_TypeDef *)GPIOA_BASE)<01>GPIOB ((GPIO_TypeDef *)GPIOB_BASE)<01>GPIOC ((GPIO_TypeDef *)GPIOC_BASE)<01>GPIOD ((GPIO_TypeDef *)GPIOD_BASE)<01>GPIOE ((GPIO_TypeDef *)GPIOE_BASE)<01>ADC1 ((ADC_TypeDef *)ADC1_BASE)<01>ADC2 ((ADC_TypeDef *)ADC2_BASE)<01>ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)<01>TIM1 ((TIM_TypeDef *)TIM1_BASE)<01>SPI1 ((SPI_TypeDef *)SPI1_BASE)<01>USART1 ((USART_TypeDef *)USART1_BASE)<01>DMA1 ((DMA_TypeDef *)DMA1_BASE)<01>DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)<01>DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)<01>DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)<01>DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)<01>DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)<01>DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)<01>DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)<01>RCC ((RCC_TypeDef *)RCC_BASE)<01>CRC ((CRC_TypeDef *)CRC_BASE)<01>FLASH ((FLASH_TypeDef *)FLASH_R_BASE)<01>OB ((OB_TypeDef *)OB_BASE)<01>DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)<01>
RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos)<01>
RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk<01>
RCC_APB2ENR_IOPAEN_Pos (2U)<01>
RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos)<01>
RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk<01>
RCC_APB2ENR_IOPBEN_Pos (3U)<01>
RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos)<01>
RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk<01>
RCC_APB2ENR_IOPCEN_Pos (4U)<01>
RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos)<01>
RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk<01>
RCC_APB2ENR_IOPDEN_Pos (5U)<01>
RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos)<01>
RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk<01>
RCC_APB2ENR_ADC1EN_Pos (9U)<01>
RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)<01>
RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk<01>
RCC_APB2ENR_ADC2EN_Pos (10U)<01>
RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)<01>
RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk<01>
RCC_APB2ENR_TIM1EN_Pos (11U)<01>
RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)<01>
RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk<01>
RCC_APB2ENR_SPI1EN_Pos (12U)<01>
RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)<01>
RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk<01>
RCC_APB2ENR_USART1EN_Pos (14U)<01>
RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)<01>
RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk<01>
RCC_APB2ENR_IOPEEN_Pos (6U)<01>
RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos)<01>
RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk<01>
RCC_APB1ENR_TIM2EN_Pos (0U)<01>
RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)<01>
RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk<01>
RCC_APB1ENR_TIM3EN_Pos (1U)<01>
RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)<01>
RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk<01>
RCC_APB1ENR_WWDGEN_Pos (11U)<01>
RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)<01>
RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk<01>
RCC_APB1ENR_USART2EN_Pos (17U)<01>
RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)<01>
RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk<01>
RCC_APB1ENR_I2C1EN_Pos (21U)<01>
RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)<01>
RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk<01>
RCC_APB1ENR_CAN1EN_Pos (25U)<01>
RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)<01>
RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk<01>
RCC_APB1ENR_BKPEN_Pos (27U)<01>
RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos)<01>
RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk<01>
RCC_APB1ENR_PWREN_Pos (28U)<01>
RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)<01>
RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk<01>
RCC_APB1ENR_TIM4EN_Pos (2U)<01>
RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)<01>
RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk<01>
RCC_APB1ENR_SPI2EN_Pos (14U)<01>
RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)<01>
RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk<01>
RCC_APB1ENR_USART3EN_Pos (18U)<01>
RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)<01>
RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk<01>
RCC_APB1ENR_I2C2EN_Pos (22U)<01>
RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)<01>
RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk<01>
RCC_APB1ENR_USBEN_Pos (23U)<01>
RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos)<01>
RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk<01>
RCC_BDCR_LSEON_Pos (0U)<01>
RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)<01>
RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk<01>
RCC_BDCR_LSERDY_Pos (1U)<01>
RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)<01>
RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk<01>
RCC_BDCR_LSEBYP_Pos (2U)<01>
RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)<01>
RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk<01>
RCC_BDCR_RTCSEL_Pos (8U)<01>
RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)<01>
RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk<01>
RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)<01>
RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)<01>
RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U<01>
RCC_BDCR_RTCSEL_LSE 0x00000100U<01>
RCC_BDCR_RTCSEL_LSI 0x00000200U<01>
RCC_BDCR_RTCSEL_HSE 0x00000300U<01>
RCC_BDCR_RTCEN_Pos (15U)<01>
RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)<01>
RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk<01>
RCC_BDCR_BDRST_Pos (16U)<01>
RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)<01>
RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk<01>
RCC_CSR_LSION_Pos (0U)<01>
RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)<01>
RCC_CSR_LSION RCC_CSR_LSION_Msk<01>
RCC_CSR_LSIRDY_Pos (1U)<01>
RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)<01>
RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk<01>
RCC_CSR_RMVF_Pos (24U)<01> RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)<01> RCC_CSR_RMVF RCC_CSR_RMVF_Msk<01> RCC_CSR_PINRSTF_Pos (26U)<01> RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)<01> RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk<01> RCC_CSR_PORRSTF_Pos (27U)<01> RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)<01> RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk<01> RCC_CSR_SFTRSTF_Pos (28U)<01> RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)<01> RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk<01> RCC_CSR_IWDGRSTF_Pos (29U)<01> RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)<01> RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk<01> RCC_CSR_WWDGRSTF_Pos (30U)<01> RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)<01> RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk<01> RCC_CSR_LPWRRSTF_Pos (31U)<01> RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)<01> RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk<01> GPIO_CRL_MODE_Pos (0U)<01> GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos)<01> GPIO_CRL_MODE GPIO_CRL_MODE_Msk<01> GPIO_CRL_MODE0_Pos (0U)<01> GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos)<01> GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk<01> GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos)<01> GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos)<01> GPIO_CRL_MODE1_Pos (4U)<01> GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos)<01> GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk<01> GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos)<01> GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos)<01> GPIO_CRL_MODE2_Pos (8U)<01> GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos)<01> GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk<01> GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos)<01> GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos)<01> GPIO_CRL_MODE3_Pos (12U)<01> GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos)<01> GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk<01> GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos)<01> GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos)<01> GPIO_CRL_MODE4_Pos (16U)<01> GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos)<01> GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk<01> GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos)<01> GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos)<01> GPIO_CRL_MODE5_Pos (20U)<01> GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos)<01> GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk<01> GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos)<01> GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos)<01> GPIO_CRL_MODE6_Pos (24U)<01> GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos)<01> GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk<01> GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos)<01> GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos)<01> GPIO_CRL_MODE7_Pos (28U)<01> GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos)<01> GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk<01> GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos)<01> GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos)<01> GPIO_CRL_CNF_Pos (2U)<01> GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos)<01> GPIO_CRL_CNF GPIO_CRL_CNF_Msk<01> GPIO_CRL_CNF0_Pos (2U)<01> GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos)<01> GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk<01> GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos)<01> GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos)<01> GPIO_CRL_CNF1_Pos (6U)<01> GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos)<01> GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk<01> GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos)<01> GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos)<01> GPIO_CRL_CNF2_Pos (10U)<01> GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos)<01> GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk<01> GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos)<01> GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos)<01> GPIO_CRL_CNF3_Pos (14U)<01> GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos)<01> GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk<01> GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos)<01> GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos)<01> GPIO_CRL_CNF4_Pos (18U)<01> GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos)<01> GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk<01> GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos)<01> GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos)<01> GPIO_CRL_CNF5_Pos (22U)<01> GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos)<01> GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk<01> GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos)<01> GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos)<01> GPIO_CRL_CNF6_Pos (26U)<01> GPIO
DMA1_Channel1_IRQn DMA1_Channel2_IRQn DMA1_Channel3_IRQn DMA1_Channel4_IRQnDMA1_Channel5_IRQnDMA1_Channel6_IRQnDMA1_Channel7_IRQnADC1_2_IRQnUSB_HP_CAN1_TX_IRQnUSB_LP_CAN1_RX0_IRQnCAN1_RX1_IRQnCAN1_SCE_IRQnEXTI9_5_IRQnTIM1_BRK_IRQnTIM1_UP_IRQnTIM1_TRG_COM_IRQnTIM1_CC_IRQnTIM2_IRQnTIM3_IRQnTIM4_IRQnI2C1_EV_IRQnI2C1_ER_IRQn I2C2_EV_IRQn!I2C2_ER_IRQn"SPI1_IRQn#SPI2_IRQn$USART1_IRQn%USART2_IRQn&USART3_IRQn'EXTI15_10_IRQn(RTC_Alarm_IRQn)USBWakeUp_IRQn*iIRQn_Type<12>~B<>
P&SR#&CR1#&CR2#&SMPR1# &SMPR2#&JOFR1#&JOFR2#&JOFR3#&JOFR4# &HTR#$&LTR#(&SQR1#,&SQR2#0&SQR3#4&JSQR#8&JDR1#<&JDR2#@&JDR3#D&JDR4#H&DR#L<00>jiADC_TypeDef<01>B<>
P&SR#&CR1#&CR2#<03>
j&RESERVEDD# &DR#LiADC_Common_TypeDef <01>B<> 8&RESERVED0j#&DR1#&DR2#&DR3# &DR4#&DR5#&DR6#&DR7#&DR8# &DR9#$&DR10#(&RTCCR#,&CR#0&CSR#4iBKP_TypeDef<12><01>B<> &TIR#&TDTR#&TDLR#&TDHR# iCAN_TxMailBox_TypeDefB<01>B<> &RIR#&RDTR#&RDLR#&RDHR# iCAN_FIFOMailBox_TypeDef<12><01>B<>&FR1#&FR2#iCAN_FilterRegister_TypeDef<12><01>B<><11>&MCR#&MSR#&TSR#&RF0R# &RF1R#&IER#&ESR#&BTR#<03>jW&RESERVED0<12># <03>v&sTxMailBox<12>#<23><03><12>&sFIFOMailBox<12>#<23><03>j &RESERVED1<12>#<23>&FMR#<23>&FM1R#<23>&RESERVED2j#<23>&FS1R#<23>&RESERVED3j#<23>&FFA1R#<23>&RESERVED4j#<23>&FA1R#<23><03>j&RESERVED5u#<23><03> &sFilterRegister<12>#<23>iCAN_TypeDef&<01>B<> &DR#&IDR #&RESERVED0K#&RESERVED1Z#&CR#<00>KiCRC_TypeDef<12><01>B<>&IDCODE#&CR#iDBGMCU_TypeDef- <01>B<>&CCR#&CNDTR#&CPAR#&CMAR# iDMA_Channel_TypeDefa <01>B<>&ISR#&IFCR#iDMA_TypeDef<12> <01>B<>&IMR#&EMR#&RTSR#&FTSR# &SWIER#&PR#iEXTI_TypeDef<12> <01>B<>$&ACR#&KEYR#&OPTKEYR#&SR# &CR#&AR#&RESERVED#&OBR#&WRPR# iFLASH_TypeDefA
<01>B<>&RDP- #&USER- #&Data0- #&Data1- #&WRP0- #&WRP1- #
&WRP2- # &WRP3- #<00>ZiOB_TypeDef<12>
<01>B<>&CRL#&CRH#&IDR#&ODR# &BSRR#&BRR#&LCKR#iGPIO_TypeDefG <01>B<> &EVCR#&MAPR#<03>&EXTICR<12> #&RESERVED0j#&MAPR2#iAFIO_TypeDef<12> <01>B<>$&CR1#&CR2#&OAR1#&OAR2# &DR#&SR1#&SR2#&CCR#&TRISE# iI2C_TypeDef <01>B<>&KR#&PR#&RLR#&SR# iIWDG_TypeDef<12> <01>B<>&CR#&CSR#iPWR_TypeDef<12> <01>B<>(&CR#&CFGR#&CIR#&APB2RSTR# &APB1RSTR#&AHBENR#&APB2ENR#&APB1ENR#&BDCR# &CSR#$iRCC_TypeDef <01>B<>(&CRH#&CRL#&PRLH#&PRLL# &DIVH#&DIVL#&CNTH#&CNTL#&ALRH# &ALRL#$iRTC_TypeDef<12> <01>B<> &CR1#&CR2#&SR#&DR# &CRCPR#&RXCRCR#&TXCRCR#&I2SCFGR#iSPI_TypeDef5<01>B<>T&CR1#&CR2#&SMCR#&DIER# &SR#&EGR#&CCMR1#&CCMR2#&CCER# &CNT#$&PSC#(&ARR#,&RCR#0&CCR1#4&CCR2#8&CCR3#<&CCR4#@&BDTR#D&DCR#H&DMAR#L&OR#PiTIM_TypeDef<12><01>B<> &SR#&DR#&BRR#&CR1# &CR2#&CR3#&GTPR#iUSART_TypeDef<12><01>B<>#T&EP0R- #&RESERVED0- #&EP1R- #&RESERVED1- #&EP2R- #&RESERVED2- #
&EP3R- # &RESERVED3- #&EP4R- #&RESERVED4- #&EP5R- #&RESERVED5- #&EP6R- #&RESERVED6- #&EP7R- #<03>"- &RESERVED7<12>#&CNTR- #@&RESERVED8- #B&ISTR- #D&RESERVED9- #F&FNR- #H&RESERVEDA- #J&DADDR- #L&RESERVEDB- #N&BTABLE- #P&RESERVEDC- #RiUSB_TypeDef"<01>B<># &CR#&CFR#&SR#iWWDG_TypeDef<12><01>{|}~__STM32F1xx_HAL_H X__HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)Y__HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)^__HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)___HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)e__HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)f__HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)<01>__HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)<01>__HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)<01>__HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)<01>__HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)<01>__HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)<01>__HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)<01>__HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)<01>__HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)<01>__HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)<01>__HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)<01>__HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)<01>__HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)<01>IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || ((FREQ) == HAL_TICK_FREQ_1KHZ))|p ../Drivers/STM32F1xx_HAL_Driver/Inc/../Core/Inc/stm32f1xx_hal.hstm32f1xx_hal_conf.hp../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]C:\Users\XerolySkinner\Desktop\MDK-ARM<19>HAL_TICK_FREQ_10HZ dHAL_TICK_FREQ_100HZ
HAL_TICK_FREQ_1KHZ HAL_TICK_FREQ_DEFAULT iHAL_TickFreqTypeDef<12>7<03>j<00>uwTick4<01>uwTickPrioj<01>uwTickFreq7t;uwTickIuwTickPrio]uwTickFreq<00><00><00>'__STM32F1XX_H 5STM32F1 ___STM32F1_CMSIS_VERSION_MAIN (0x04)`__STM32F1_CMSIS_VERSION_SUB1 (0x03)a__STM32F1_CMSIS_VERSION_SUB2 (0x03)b__STM32F1_CMSIS_VERSION_RC (0x00)c__STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24) |(__STM32F1_CMSIS_VERSION_SUB1 << 16) |(__STM32F1_CMSIS_VERSION_SUB2 << 8 ) |(__STM32F1_CMSIS_VERSION_RC))<03><01>IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))<01>SET_BIT(REG,BIT) ((REG) |= (BIT))<01>CLEAR_BIT(REG,BIT) ((REG) &= ~(BIT))<01>READ_BIT(REG,BIT) ((REG) & (BIT))<01>CLEAR_REG(REG) ((REG) = (0x0))<01>WRITE_REG(REG,VAL) ((REG) = (VAL))<01>READ_REG(REG) ((REG))<01>MODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))<01>POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))<01>ATOMIC_SET_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)<01>ATOMIC_CLEAR_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)<01>ATOMIC_MODIFY_REG(REG,CLEARMSK,SETMASK) do { uint32_t val; do { val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)<01>ATOMIC_SETH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)<01>ATOMIC_CLEARH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)<01>ATOMIC_MODIFYH_REG(REG,CLEARMSK,SETMASK) do { uint16_t val; do { val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)<03><00><00> ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx.hstm32f103xb.hstm32f1xx_hal.hT../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]C:\Users\XerolySkinner\Desktop\MDK-ARM<19>RESET SET iFlagStatus<12><01>iITStatus<12><01><19>DISABLE ENABLE iFunctionalState<12><01><19>SUCCESS ERROR iErrorStatus(<01><00><00><00>STM32_HAL_LEGACY $AES_FLAG_RDERR CRYP_FLAG_RDERR%AES_FLAG_WRERR CRYP_FLAG_WRERR&AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF'AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR(AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR0ADC_RESOLUTION12b ADC_RESOLUTION_12B1ADC_RESOLUTION10b ADC_RESOLUTION_10B2ADC_RESOLUTION8b ADC_RESOLUTION_8B3ADC_RESOLUTION6b ADC_RESOLUTION_6B4OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN5OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED6EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV7EOC_SEQ_CONV ADC_EOC_SEQ_CONV8EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV9REGULAR_GROUP ADC_REGULAR_GROUP:INJECTED_GROUP ADC_INJECTED_GROUP;REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP<AWD_EVENT ADC_AWD_EVENT=AWD1_EVENT ADC_AWD1_EVENT>AWD2_EVENT ADC_AWD2_EVENT?AWD3_EVENT ADC_AWD3_EVENT@OVR_EVENT ADC_OVR_EVENTAJQOVF_EVENT ADC_JQOVF_EVENTBALL_CHANNELS ADC_ALL_CHANNELSCREGULAR_CHANNELS ADC_REGULAR_CHANNELSDINJECTED_CHANNELS ADC_INJECTED_CHANNELSESYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSORFSYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINTGADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1HADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2IADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4JADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6KADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8LADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGOMADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2NADC_EXTERNA
USART_CLOCK_DISABLED USART_CLOCK_DISABLE<01>
USART_CLOCK_ENABLED USART_CLOCK_ENABLE<01>
USARTNACK_ENABLED USART_NACK_ENABLE<01>
USARTNACK_DISABLED USART_NACK_DISABLE<01>
CFR_BASE WWDG_CFR_BASE<01>
CAN_FilterFIFO0 CAN_FILTER_FIFO0<01>
CAN_FilterFIFO1 CAN_FILTER_FIFO1<01>
CAN_IT_RQCP0 CAN_IT_TME<01>
CAN_IT_RQCP1 CAN_IT_TME<01>
CAN_IT_RQCP2 CAN_IT_TME<01>
INAK_TIMEOUT CAN_TIMEOUT_VALUE<01>
SLAK_TIMEOUT CAN_TIMEOUT_VALUE<01>
CAN_TXSTATUS_FAILED ((uint8_t)0x00U)<01>
CAN_TXSTATUS_OK ((uint8_t)0x01U)<01>
CAN_TXSTATUS_PENDING ((uint8_t)0x02U)<01>
VLAN_TAG ETH_VLAN_TAG<01>
MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD<01>
MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD<01>
JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD<01>
MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK<01>
MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK<01>
MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK<01>
DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK<01>
ETH_MMCCR 0x00000100U<01>
ETH_MMCRIR 0x00000104U<01>
ETH_MMCTIR 0x00000108U<01>
ETH_MMCRIMR 0x0000010CU<01>
ETH_MMCTIMR 0x00000110U<01>
ETH_MMCTGFSCCR 0x0000014CU<01>
ETH_MMCTGFMSCCR 0x00000150U<01>
ETH_MMCTGFCR 0x00000168U<01>
ETH_MMCRFCECR 0x00000194U<01>
ETH_MMCRFAECR 0x00000198U<01>
ETH_MMCRGUFCR 0x000001C4U<01>
ETH_MAC_TXFIFO_FULL 0x02000000U<01>
ETH_MAC_TXFIFONOT_EMPTY 0x01000000U<01>
ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U<01>
ETH_MAC_TXFIFO_IDLE 0x00000000U<01>
ETH_MAC_TXFIFO_READ 0x00100000U<01>
ETH_MAC_TXFIFO_WAITING 0x00200000U<01>
ETH_MAC_TXFIFO_WRITING 0x00300000U<01>
ETH_MAC_TRANSMISSION_PAUSE 0x00080000U<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U<01>
ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U<01>
ETH_MAC_RXFIFO_EMPTY 0x00000000U<01>
ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U<01>
ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U<01>
ETH_MAC_RXFIFO_FULL 0x00000300U<01>
ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U<01>
ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U<01>
ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U<01>
ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U<01>
ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U<01>
ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U<01>
ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U<01>
HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR<01>
DCMI_IT_OVF DCMI_IT_OVR<01>
DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI<01>
DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI<01>
HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop<01>
HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop<01>
HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop<01> HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback<01> HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef<01> HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef<01> HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish<01> HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish<01> HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish<01> HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish<01> HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1<01> HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224<01> HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256<01> HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5<01> HASH_AlgoMode_HASH HASH_ALGOMODE_HASH<01> HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC<01> HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY<01> HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY<01> HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode<01> HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode<01> HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode<01> HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode<01> HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode<01> HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode<01> HAL_DBG_LowPowerConfig(Periph,cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))<01> HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect<01> HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())<01> HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())<01> HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())<01> HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())<01> FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram<01> FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown<01> FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown<01> HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock<01> HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock<01> HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase<01> HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program<01> HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter<01> HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter<01> HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter<01> HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter<01> HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus,cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))<01> HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT<01> HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT<01> HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT<01> HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT<01> HAL_PWR_PVDConfig HAL_PWR_ConfigPVD<01> HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg<01> HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown<01> HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor<01> HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg<01> HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown<01> HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor<01> HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler<01> HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD<01> HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler<01> HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback<01> HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive<01> HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive<01> HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC<01> HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC<01> HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM<01> PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL<01> PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING<01> PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING<01> PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING<01> PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING<01> PWR_MODE_EVENT_FALLING
__HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)<01>
__HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)<01>
__HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)<01>
__HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)<01> __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))<01> __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))<01> __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))<01> __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))<01> __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))<01> __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))<01> __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))<01> __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))<01> __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))<01> __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))<01> __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))<01> __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))<01> __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))<01> __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))<01> __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))<01> __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))<01> __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))<01> __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)<01> __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))<01> __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))<01> __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))<01> __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))ti ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.hstm32f1xx_hal_def.h../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]C:\Users\XerolySkinner\Desktop\MDK-ARMB<>(&OscillatorTypej#&HSEStatej#&HSEPredivValuej#&LSEStatej# &HSIStatej#&HSICalibrationValuej#&LSIStatej#&PLL<10>#iRCC_OscInitTypeDef<12><01>B<>&PeriphClockSelectionj#&RTCClockSelectionj#&AdcClockSelectionj#&UsbClockSelectionj# iRCC_PeriphCLKInitTypeDef<12><01><00><00><00>__STM32F1xx_HAL_RCC_H _RCC_PLLSOURCE_HSI_DIV2 0x00000000U`RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRCiRCC_OSCILLATORTYPE_NONE 0x00000000UjRCC_OSCILLATORTYPE_HSE 0x00000001UkRCC_OSCILLATORTYPE_HSI 0x00000002UlRCC_OSCILLATORTYPE_LSE 0x00000004UmRCC_OSCILLATORTYPE_LSI 0x00000008UuRCC_HSE_OFF 0x00000000UvRCC_HSE_ON RCC_CR_HSEONwRCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))RCC_LSE_OFF 0x00000000U<01>RCC_LSE_ON RCC_BDCR_LSEON<01>RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))<01>RCC_HSI_OFF 0x00000000U<01>RCC_HSI_ON RCC_CR_HSION<01>RCC_HSICALIBRATION_DEFAULT 0x10U<01>RCC_LSI_OFF 0x00000000U<01>RCC_LSI_ON RCC_CSR_LSION<01>RCC_PLL_NONE 0x00000000U<01>RCC_PLL_OFF 0x00000001U<01>RCC_PLL_ON 0x00000002U<01>RCC_CLOCKTYPE_SYSCLK 0x00000001U<01>RCC_CLOCKTYPE_HCLK 0x00000002U<01>RCC_CLOCKTYPE_PCLK1 0x00000004U<01>RCC_CLOCKTYPE_PCLK2 0x00000008U<01>RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI<01>RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE<01>RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL<01>RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI<01>RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE<01>RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL<01>RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1<01>RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2<01>RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4<01>RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8<01>RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16<01>RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64<01>RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128<01>RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256<01>RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512<01>RCC_HCLK_DIV1 RCC_CFGR_P
RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))<01>
RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))<01>
RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))<01>
CR_REG_INDEX ((uint8_t)1)<01>
BDCR_REG_INDEX ((uint8_t)2)<01>
CSR_REG_INDEX ((uint8_t)3)<01>
RCC_FLAG_MASK ((uint8_t)0x1F)<01>
__HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE<01>
__HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE<01>
__HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET<01>
__HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET<01>
IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || ((__SOURCE__) == RCC_PLLSOURCE_HSE))<01>
IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))<01>
IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || ((__HSE__) == RCC_HSE_BYPASS))<01>
IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS))<01>
IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))<01>
IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)<01>
IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))<01>
IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON))<01>
IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))<01>
IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))<01>
IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))<01>
IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512))<01>
IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || ((__PCLK__) == RCC_HCLK_DIV16))<01>
IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)<01>
IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))<01>
IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))<00><00> ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.hstm32f1xx_hal_def.hstm32f1xx_hal_rcc_ex.h<01>../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]C:\Users\XerolySkinner\Desktop\MDK-ARMB<> &PLLStatej#&PLLSourcej#&PLLMULj#iRCC_PLLInitTypeDef<12>;B<>&ClockTypej#&SYSCLKSourcej#&AHBCLKDividerj#&APB1CLKDividerj# &APB2CLKDividerj#iRCC_ClkInitTypeDefP<00><00><00>STM32F1xx_HAL_GPIO_EX_H 6AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX07AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX18AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX29AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3:AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4;AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5<AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6=AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7>AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8?AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9@AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10AAFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11BAFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12CAFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13DAFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14EAFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15GIS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || ((__PIN__) == AFIO_EVENTOUT_PIN_1) || ((__PIN__) == AFIO_EVENTOUT_PIN_2) || ((__PIN__) == AFIO_EVENTOUT_PIN_3) || ((__PIN__) == AFIO_EVENTOUT_PIN_4) || ((__PIN__) == AFIO_EVENTOUT_PIN_5) || ((__PIN__) == AFIO_EVENTOUT_PIN_6) || ((__PIN__) == AFIO_EVENTOUT_PIN_7) || ((__PIN__) == AFIO_EVENTOUT_PIN_8) || ((__PIN__) == AFIO_EVENTOUT_PIN_9) || ((__PIN__) == AFIO_EVENTOUT_PIN_10) || ((__PIN__) == AFIO_EVENTOUT_PIN_11) || ((__PIN__) == AFIO_EVENTOUT_PIN_12) || ((__PIN__) == AFIO_EVENTOUT_PIN_13) || ((__PIN__) == AFIO_EVENTOUT_PIN_14) || ((__PIN__) == AFIO_EVENTOUT_PIN_15))_AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA`AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PBaAFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PCbAFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PDcAFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PEeIS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || ((__PORT__) == AFIO_EVENTOUT_PORT_B) || ((__PORT__) == AFIO_EVENTOUT_PORT_C) || ((__PORT__) == AFIO_EVENTOUT_PORT_D) || ((__PORT__) == AFIO_EVENTOUT_PORT_E))|__HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP)<01>__HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP)<01>__HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP)<01>__HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP)<01>__HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP)<01>__HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP)<01>__HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP)<01>__HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP)<01>__HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)<01>__HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)<01>__HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)<01>__HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)<01>__HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)<01>__HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)<01>__HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)<01>__HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_
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