MicrochipFor32/MX_FastSet/T103RC/MDK-ARM/template/vartable.o

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<00>
bsp_System\\vartable.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]D:\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM__asm___12_vartable_cpp_253fac6e___Z7__REV16jX>







..\Drivers\CMSIS\Include\cmsis_armcc.h
<03>


<01>
bsp_System\\vartable.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]D:\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM__asm___12_vartable_cpp_253fac6e___Z7__REVSHsX>







..\Drivers\CMSIS\Include\cmsis_armcc.h
<03>


<01>
bsp_System\\vartable.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]D:\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM__asm___12_vartable_cpp_253fac6e___Z5__RRXjX>







..\Drivers\CMSIS\Include\cmsis_armcc.h
<03>
&

0<00><><EFBFBD><EFBFBD>armcc+
|

	
0<00><><EFBFBD><EFBFBD>armcc+
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0<00><><EFBFBD><EFBFBD>armcc+
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0<00><><EFBFBD><EFBFBD>armcc+|

	
A~<7E>
A}0<00><><EFBFBD><EFBFBD>armcc+|

	
A~<7E><02>
<00>bsp_System\vartable.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<00>bsp_System\vartable.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM`<60>
7<00>
N<02>x{X
P{h<02>t
bsp_System\vartable.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARMU<>
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bsp_System\vartable.cpp

\/





bsp_System\vartable.cpp
!+
  


X/





bsp_System\vartable.cpp
!/
&&


}}}}<00><><EFBFBD>}
Q
P
T
__DATE__ "May  9 2023"
__TIME__ "15:47:57"
__STDC__ 1
__cplusplus 199711L
_BOOL 1
__ARRAY_OPERATORS 1
__IMPLICIT_INCLUDE 1
__RTTI 1
__EDG_RUNTIME_USES_NAMESPACES 1
__EDG_IA64_ABI 1
__EDG_IA64_ABI_VARIANT_CTORS_AND_DTORS_RETURN_THIS 1
__EDG_IA64_ABI_USE_INT_STATIC_INIT_GUARD 1
__EDG_TYPE_TRAITS_ENABLED 1
__EDG__ 1
__EDG_VERSION__ 407
__EDG_SIZE_TYPE__ unsigned int
__EDG_PTRDIFF_TYPE__ int
__sizeof_int 4
__sizeof_long 4
__sizeof_ptr 4
__ARMCC_VERSION 5060960
__TARGET_CPU_CORTEX_M3 1
__TARGET_FPU_SOFTVFP 1
__TARGET_FPU_SOFTVFP 1
__UVISION_VERSION 537
_RTE_ 1
STM32F10X_HD 1
_RTE_ 1
USE_HAL_DRIVER 1
STM32F103xE 1
__CC_ARM 1
__arm 1
__arm__ 1
__TARGET_ARCH_7_M 1
__TARGET_ARCH_ARM 0
__TARGET_ARCH_THUMB 4
__TARGET_ARCH_A64 0
__TARGET_ARCH_AARCH32 1
__TARGET_PROFILE_M 1
__TARGET_FEATURE_HALFWORD 1
__TARGET_FEATURE_THUMB 1
__TARGET_FEATURE_MULTIPLY 1
__TARGET_FEATURE_DOUBLEWORD 1
__TARGET_FEATURE_DIVIDE 1
__TARGET_FEATURE_UNALIGNED 1
__TARGET_FEATURE_CLZ 1
__TARGET_FEATURE_DMB 1
__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0
__APCS_INTERWORK 1
__thumb 1
__thumb__ 1
__t32__ 1
__OPTIMISE_SPACE 1
__OPT_SMALL_ASSERT 1
__OPTIMISE_LEVEL 3
__SOFTFP__ 1

<00>u32Endian


%

.


 !"

'__DEBUG__ 
+_STM32_HAL_ 
.BPS_CONFIG_VERSION "1.0.0"
3EQ_CheckBox 0
7EQ_NumBox 0
>EQ_BITERABI 0x000
BEQ_BITERABIS 0x00
Itext(format,__VA_ARGS__...) com.print(format, ## __VA_ARGS__)4)






bsp_System\User.h


<01>bsp_System\User.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM
$%&

__stdint_h 
__ARMCLIB_VERSION 5060044
__INT64 __int64
__INT64_C_SUFFIX__ ll
__PASTE2(x,y) x ## y
__PASTE(x,y) __PASTE2(x, y)
__INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))
__UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))
__LONGLONG long long
#__STDINT_DECLS %__CLIBNS
)__CLIBNS std::<02>__INT64<02>__LONGLONGXM






D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h


D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]
unsigned charunsigned shortunsigned intunsigned long long
signed charshortintlong long<00>
<01>stdiint8_t<12>
8 iint16_t<12>
9 iint32_t<12>
: iint64_t<12>
; iuint8_t<12>
> iuint16_t<12>
? iuint32_t<12>
@ iuint64_t<12>
A iint_least8_t<12>
G iint_least16_t<12>
H iint_least32_t<12>
I iint_least64_t<12>
J iuint_least8_t<12>
M iuint_least16_t<12>
N iuint_least32_t<12>
O iuint_least64_t<12>
P iint_fast8_t<12>
U iint_fast16_t<12>
V iint_fast32_t<12>
W iint_fast64_t<12>
X iuint_fast8_t<12>
[ iuint_fast16_t<12>
\ iuint_fast32_t<12>
] iuint_fast64_t<12>
^ iintptr_t<12>
e iuintptr_t<12>
f iintmax_t<12>
j!iuintmax_t<12>
k!
()*
#
>P8(x) ((u8*)(&(x)))
?Pn8(x,y) (((u8*)(&(x)))[y])
@P16(x) ((u16*)(&(x)))
APn16(x,y) (((u16*)(&(x)))[y])
BP32(x) ((u32*)(&(x)))
CPn32(x,y) (((u32*)(&(x)))[y])
EDelLb(x) (x & (x - 1))
FqDelLb(x) (x=(x & (x - 1)))
HtoBool(x) (x!=0)
IuBit(x,y) (x&(1<<y))
JtBit(x,y) (toBool(uBit(x,y)))
LsBit(x,y) (x|(1<<y))
MrBit(x,y) (x&(~(1<<y)))
NmBit(x,y,z) ((z)?sBit(x,y):rBit(x,y))
PLoopAdd(var,min,step,max) (var<max?var+step:min)
QqLoopAdd(var,min,step,max) (var=var<max?var+step:min)
RLoopDec(var,min,step,max) (var>min?var-step:max)
SqLoopDec(var,min,step,max)

<01>__set_FPSCR3j
fpscr
@AB

__CMSIS_COMPILER_H "<00><00>






../Drivers/CMSIS/Include/D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\cmsis_compiler.h
stdint.hcmsis_armcc.h


<01>../Drivers/CMSIS/Include/cmsis_compiler.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM
DEFG

 __CORE_CM3_H_GENERIC "?
B__CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
C__CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
D__CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | __CM3_CMSIS_VERSION_SUB )
G__CORTEX_M (3U)
L__FPU_USED 0Us
__CORE_CM3_H_DEPENDANT 
<01>
__I volatile
<01>
__O volatile
<01>
__IO volatile
<01>
__IM volatile const
<01>
__OM volatile
<01>
__IOM volatile
<01>
APSR_N_Pos 31U
<01>
APSR_N_Msk (1UL << APSR_N_Pos)
<01>
APSR_Z_Pos 30U
<01>
APSR_Z_Msk (1UL << APSR_Z_Pos)
<01>
APSR_C_Pos 29U
<01>
APSR_C_Msk (1UL << APSR_C_Pos)
<01>
APSR_V_Pos 28U
<01>
APSR_V_Msk (1UL << APSR_V_Pos)
<01>
APSR_Q_Pos 27U
<01>
APSR_Q_Msk (1UL << APSR_Q_Pos)
<01>
IPSR_ISR_Pos 0U
<01>
IPSR_ISR_Msk (0x1FFUL )
<01>xPSR_N_Pos 31U
<01>xPSR_N_Msk (1UL << xPSR_N_Pos)
<01>xPSR_Z_Pos 30U
<01>xPSR_Z_Msk (1UL << xPSR_Z_Pos)
<01>xPSR_C_Pos 29U
<01>xPSR_C_Msk (1UL << xPSR_C_Pos)
<01>xPSR_V_Pos 28U
<01>xPSR_V_Msk (1UL << xPSR_V_Pos)
<01>xPSR_Q_Pos 27U
<01>xPSR_Q_Msk (1UL << xPSR_Q_Pos)
<01>xPSR_ICI_IT_2_Pos 25U
<01>xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)
<01>xPSR_T_Pos 24U
<01>xPSR_T_Msk (1UL << xPSR_T_Pos)
<01>xPSR_ICI_IT_1_Pos 10U
<01>xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)
<01>xPSR_ISR_Pos 0U
<01>xPSR_ISR_Msk (0x1FFUL )
<01>CONTROL_SPSEL_Pos 1U
<01>CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
<01>CONTROL_nPRIV_Pos 0U
<01>CONTROL_nPRIV_Msk (1UL )
<01>NVIC_STIR_INTID_Pos 0U
<01>NVIC_STIR_INTID_Msk (0x1FFUL )
<01>SCB_CPUID_IMPLEMENTER_Pos 24U
<01>SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
<01>SCB_CPUID_VARIANT_Pos 20U
<01>SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
<01>SCB_CPUID_ARCHITECTURE_Pos 16U
<01>SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
<01>SCB_CPUID_PARTNO_Pos 4U
<01>SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
<01>SCB_CPUID_REVISION_Pos 0U
<01>SCB_CPUID_REVISION_Msk (0xFUL )
<01>SCB_ICSR_NMIPENDSET_Pos 31U
<01>SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
<01>SCB_ICSR_PENDSVSET_Pos 28U
<01>SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
<01>SCB_ICSR_PENDSVCLR_Pos 27U
<01>SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
<01>SCB_ICSR_PENDSTSET_Pos 26U
<01>SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
<01>SCB_ICSR_PENDSTCLR_Pos 25U
<01>SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
<01>SCB_ICSR_ISRPREEMPT_Pos 23U
<01>SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
<01>SCB_ICSR_ISRPENDING_Pos 22U
<01>SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
<01>SCB_ICSR_VECTPENDING_Pos 12U
<01>SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
<01>SCB_ICSR_RETTOBASE_Pos 11U
<01>SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
<01>SCB_ICSR_VECTACTIVE_Pos 0U
<01>SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
<01>SCB_VTOR_TBLBASE_Pos 29U
<01>SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)
<01>SCB_VTOR_TBLOFF_Pos 7U
<01>SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
<01>SCB_AIRCR_VECTKEY_Pos 16U
<01>SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
<01>SCB_AIRCR_VECTKEYSTAT_Pos 16U
<01>SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
<01>SCB_AIRCR_ENDIANESS_Pos 15U
<01>SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
<01>SCB_AIRCR_PRIGROUP_Pos 8U
<01>SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
<01>SCB_AIRCR_SYSRESETREQ_Pos 2U
<01>SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
<01>SCB_AIRCR_VECTCLRACTIVE_Pos 1U
<01>SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
<01>SCB_AIRCR_VECTRESET_Pos 0U
<01>SCB_AIRCR_VECTRESET_Msk (1UL )
<01>SCB_SCR_SEVONPEND_Pos 4U
<01>SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
<01>SCB_SCR_SLEEPDEEP_Pos 2U
<01>SCB_SCR_SLEE
CoreDebug_DHCSR_S_REGRDY_Pos 16U
<01>
CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
<01>
CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
<01>
CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
<01>
CoreDebug_DHCSR_C_MASKINTS_Pos 3U
<01>
CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
<01>
CoreDebug_DHCSR_C_STEP_Pos 2U
<01>
CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
<01>
CoreDebug_DHCSR_C_HALT_Pos 1U
<01>
CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
<01>
CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
<01>
CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL )
<01>
CoreDebug_DCRSR_REGWnR_Pos 16U
<01>
CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
<01>
CoreDebug_DCRSR_REGSEL_Pos 0U
<01>
CoreDebug_DCRSR_REGSEL_Msk (0x1FUL )
<01>
CoreDebug_DEMCR_TRCENA_Pos 24U
<01>
CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
<01>
CoreDebug_DEMCR_MON_REQ_Pos 19U
<01>
CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
<01>
CoreDebug_DEMCR_MON_STEP_Pos 18U
<01>
CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
<01>
CoreDebug_DEMCR_MON_PEND_Pos 17U
<01>
CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
<01>
CoreDebug_DEMCR_MON_EN_Pos 16U
<01>
CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
<01>
CoreDebug_DEMCR_VC_HARDERR_Pos 10U
<01>
CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
<01>
CoreDebug_DEMCR_VC_INTERR_Pos 9U
<01>
CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
<01>
CoreDebug_DEMCR_VC_BUSERR_Pos 8U
<01>
CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
<01>
CoreDebug_DEMCR_VC_STATERR_Pos 7U
<01>
CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
<01>
CoreDebug_DEMCR_VC_CHKERR_Pos 6U
<01>
CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
<01>
CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
<01>
CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
<01>
CoreDebug_DEMCR_VC_MMERR_Pos 4U
<01>
CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
<01>
CoreDebug_DEMCR_VC_CORERESET_Pos 0U
<01>
CoreDebug_DEMCR_VC_CORERESET_Msk (1UL )
<01>
_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
<01>
_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
<01>
SCS_BASE (0xE000E000UL)
<01>
ITM_BASE (0xE0000000UL)
<01>
DWT_BASE (0xE0001000UL)
<01>
TPI_BASE (0xE0040000UL)
<01>
CoreDebug_BASE (0xE000EDF0UL)
<01>
SysTick_BASE (SCS_BASE + 0x0010UL)
<01>
NVIC_BASE (SCS_BASE + 0x0100UL)
<01>
SCB_BASE (SCS_BASE + 0x0D00UL)
<01>
SCnSCB ((SCnSCB_Type *) SCS_BASE )
<01>
SCB ((SCB_Type *) SCB_BASE )
<01>
SysTick ((SysTick_Type *) SysTick_BASE )
<01>
NVIC ((NVIC_Type *) NVIC_BASE )
<01>
ITM ((ITM_Type *) ITM_BASE )
<01>
DWT ((DWT_Type *) DWT_BASE )
<01>
TPI ((TPI_Type *) TPI_BASE )
<01>
CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
<01>NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
<01>NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
<01>NVIC_EnableIRQ __NVIC_EnableIRQ
<01>NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
<01>NVIC_DisableIRQ __NVIC_DisableIRQ
<01>NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
<01>NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
<01>NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
<01>NVIC_GetActive __NVIC_GetActive
<01>NVIC_SetPriority __NVIC_SetPriority
<01>NVIC_GetPriority __NVIC_GetPriority
<01>NVIC_SystemReset __NVIC_SystemReset
<01>NVIC_SetVector __NVIC_SetVector
<01>NVIC_GetVector __NVIC_GetVector
<01>NVIC_USER_IRQ_OFFSET 16
<01>EXC_RETURN_HANDLER (0xFFFFFFF1UL)
<01>EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL)
<01>EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL)
<01>ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)<00><00>






../Drivers/CMSIS/Include/D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\core_cm3.h
stdint.hcmsis_version.h
cmsis_compiler.h


\../Drivers/CMSIS/Include/core_cm3.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARMl<>'b<12>'wj
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&ISPRL#<23><03>j

&RESERVED2b#<23><03>&
&ICPR#<23><03>j

&RESERVED3<12>#<23><03>&
&IABR<12>#<23><03>j

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&SHP<12>#&SHCSR&#$&CFSR&#(&HFSR&#,&DFSR&#0&MMFAR&#4&BFAR&#8&AFSR&#<<03>
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 __SYSTEM_STM32F10X_H `W






../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h


4
../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<00>
SystemCoreClockj


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<03><12>
<00>
AHBPrescTable<12>

<03><12>
<00>
APBPrescTable


F8
<00>SystemCoreClock
AHBPrescTable 
APBPrescTable
NOP

&__STM32F103xE_H 
2__CM3_REV 0x0200U
3__MPU_PRESENT 0U
4__NVIC_PRIO_BITS 4U
5__Vendor_SysTickConfig 0U<03>
<03>
<03>

<01>FLASH_BASE 0x08000000UL
<01>FLASH_BANK1_END 0x0807FFFFUL
<01>SRAM_BASE 0x20000000UL
<01>PERIPH_BASE 0x40000000UL
<01>SRAM_BB_BASE 0x22000000UL
<01>PERIPH_BB_BASE 0x42000000UL
<01>FSMC_BASE 0x60000000UL
<01>FSMC_R_BASE 0xA0000000UL
<01>APB1PERIPH_BASE PERIPH_BASE
<01>APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
<01>AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
<01>TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)
<01>TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)
<01>TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)
<01>TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL)
<01>TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL)
<01>TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL)
<01>RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)
<01>WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)
<01>IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)
<01>SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)
<01>SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL)
<01>USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)
<01>USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)
<01>UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL)
<01>UART5_BASE (APB1PERIPH_BASE + 0x00005000UL)
<01>I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)
<01>I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)
<01>CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL)
<01>BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL)
<01>PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)
<01>DAC_BASE (APB1PERIPH_BASE + 0x00007400UL)
<01>AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL)
<01>EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)
<01>GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL)
<01>GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL)
<01>GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL)
<01>GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL)
<01>GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL)
<01>GPIOF_BASE (APB2PERIPH_BASE + 0x00001C00UL)
<01>
RCC_CR_HSION RCC_CR_HSION_Msk
<01>
RCC_CR_HSIRDY_Pos (1U)
<01>
RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
<01>
RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
<01>
RCC_CR_HSITRIM_Pos (3U)
<01>
RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
<01>
RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
<01>
RCC_CR_HSICAL_Pos (8U)
<01>
RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
<01>
RCC_CR_HSICAL RCC_CR_HSICAL_Msk
<01>
RCC_CR_HSEON_Pos (16U)
<01>
RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
<01>
RCC_CR_HSEON RCC_CR_HSEON_Msk
<01>
RCC_CR_HSERDY_Pos (17U)
<01>
RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
<01>
RCC_CR_HSERDY RCC_CR_HSERDY_Msk
<01>
RCC_CR_HSEBYP_Pos (18U)
<01>
RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
<01>
RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
<01>
RCC_CR_CSSON_Pos (19U)
<01>
RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
<01>
RCC_CR_CSSON RCC_CR_CSSON_Msk
<01>
RCC_CR_PLLON_Pos (24U)
<01>
RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
<01>
RCC_CR_PLLON RCC_CR_PLLON_Msk
<01>
RCC_CR_PLLRDY_Pos (25U)
<01>
RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
<01>
RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
<01>
RCC_CFGR_SW_Pos (0U)
<01>
RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
<01>
RCC_CFGR_SW RCC_CFGR_SW_Msk
<01>
RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
<01>
RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
<01>
RCC_CFGR_SW_HSI 0x00000000U
<01>
RCC_CFGR_SW_HSE 0x00000001U
<01>
RCC_CFGR_SW_PLL 0x00000002U
<01>
RCC_CFGR_SWS_Pos (2U)
<01>
RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
<01>
RCC_CFGR_SWS RCC_CFGR_SWS_Msk
<01>
RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
<01>
RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
<01>
RCC_CFGR_SWS_HSI 0x00000000U
<01>
RCC_CFGR_SWS_HSE 0x00000004U
<01>
RCC_CFGR_SWS_PLL 0x00000008U
<01>
RCC_CFGR_HPRE_Pos (4U)
<01>
RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
<01>
RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
<01>
RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
<01>
RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
<01>
RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
<01>
RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
<01>
RCC_CFGR_HPRE_DIV1 0x00000000U
<01>
RCC_CFGR_HPRE_DIV2 0x00000080U
<01>
RCC_CFGR_HPRE_DIV4 0x00000090U
<01>
RCC_CFGR_HPRE_DIV8 0x000000A0U
<01>
RCC_CFGR_HPRE_DIV16 0x000000B0U
<01>
RCC_CFGR_HPRE_DIV64 0x000000C0U
<01>
RCC_CFGR_HPRE_DIV128 0x000000D0U
<01>
RCC_CFGR_HPRE_DIV256 0x000000E0U
<01>
RCC_CFGR_HPRE_DIV512 0x000000F0U
<01>
RCC_CFGR_PPRE1_Pos (8U)
<01>
RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
<01>
RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
<01>
RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
<01>
RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
<01>
RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
<01>
RCC_CFGR_PPRE1_DIV1 0x00000000U
<01>
RCC_CFGR_PPRE1_DIV2 0x00000400U
<01>
RCC_CFGR_PPRE1_DIV4 0x00000500U
<01>
RCC_CFGR_PPRE1_DIV8 0x00000600U
<01>
RCC_CFGR_PPRE1_DIV16 0x00000700U
<01>
RCC_CFGR_PPRE2_Pos (11U)
<01>
RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
<01>
RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
<01>
RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
<01>
RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
<01>
RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
<01>
RCC_CFGR_PPRE2_DIV1 0x00000000U
<01>
RCC_CFGR_PPRE2_DIV2 0x00002000U
<01>
RCC_CFGR_PPRE2_DIV4 0x00002800U
<01>
RCC_CFGR_PPRE2_DIV8 0x00003000U
<01>
RCC_CFGR_PPRE2_DIV16 0x00003800U
<01>
RCC_CFGR_ADCPRE_Pos (14U)
<01>
RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos)
<01>
RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk
<01>
RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos)
<01>
RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos)
<01>
RCC_CFGR_ADCPRE_DIV2 0x00000000U
<01>
RCC_CFGR_ADCPRE_DIV4 0x00004000U
<01>
RCC_CFGR_ADCPRE_DIV6 0x00008000U
<01>
RCC_CFGR_ADCPRE_DIV8 0x0000C000U
<01>
RCC_CFGR_PLLSRC_Pos (16U)
<01>
RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos)
<01>
RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk
<01>
RCC_CFGR_PLLXTPRE_Pos (17U)
<01>
RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos)
<01>
RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk
<01>
RCC_CFGR_PLLMULL_Pos (18U)
<01>
RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos)
<01>
RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk
<01>
RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos)
<01>
RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos)
<01>
RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos)
<01>
RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos)
<01>RCC_CFGR_PLLXTPRE_HSE 0x00000000U
<01>RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U
<01>RCC_CFGR_PLLMULL2 0x00000000U
<01>RCC_CFGR_PLLMULL3_Pos (18U)
<01>RCC_CFGR_PLLMULL3_Msk (0x1UL << RCC_CFGR_PLLMULL3_Pos)
<01>RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk
<01>RCC_CFGR_PLLMULL4_Pos (19U)
<01>RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos)
<01>RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk
<01>RCC_CFGR_PLLMULL5_Pos (18U)
<01>RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos)
<01>RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk
<01>RCC_CFGR_PLLMULL6_Pos (20U)
<01>RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos)
<01>RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk
<01>RCC_CFGR_PLLMULL7_Pos (18U)
<01>RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos)
<01>RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk
<01>RCC_CFGR_PLLMULL8_Pos (19U)
<01>RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos)
<01>RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk
<01>RCC_CFGR_PLLMULL9_Pos (18U)
<01>RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos)
<01>RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk
<01>RCC_CFGR_PLLMULL10_Pos (21U)
<01>RCC_CFGR_PLLMULL10_Msk (0x1UL << RCC_CFGR_PLLMULL10_Pos)
<01>RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk
<01>RCC_CFGR_PLLMULL11_Pos (18U)
<01>RCC_CFGR_PLLMULL11_Msk (0x9UL << RCC_CFGR_PLLMULL11_Pos)
<01>RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk
<01>RCC_CFGR_PLLMULL12_Pos (19U)
<01>RCC_CFGR_PLLMULL12_Msk (0x5UL << RCC_CFGR_PLLMULL12_Pos)
<01>RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk
<01>RCC_CFGR_PLLMULL13_Pos (18U)
<01>RCC_CFGR_PLLMULL13_Msk (0xBUL << RCC_CFGR_PLLMULL13_Pos)
<01>RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk
<01>RCC_CFGR_PLLMULL14_Pos (20U)
<01>RCC_CFGR_PLLMULL14_Msk (0x3UL << RCC_CFGR_PLLMULL14_Pos)
<01>RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk
<01>RCC_CFGR_PLLMULL15_Pos (18U)
<01>RCC_CFGR_PLLMULL15_Msk (0xDUL << RCC_CFGR_PLLMULL15_Pos)
<01>RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk
<01>RCC_CFGR_PLLMULL16_Pos (19U)
<01>RCC_CFGR_PLLMULL16_Msk (0x7UL << RCC_CFGR_PLLMULL16_Pos)
<01>RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk
<01>RCC_CFGR_USBPRE_Pos (22U)
<01>RCC_CFGR_USBPRE_Msk (0x1UL << RCC_CFGR_USBPRE_Pos)
<01>RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk
<01>RCC_CFGR_MCO_Pos (24U)
<01>RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos)
<01>RCC_CFGR_MCO RCC_CFGR_MCO_Msk
<01>RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos)
<01>RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos)
<01>RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos)
<01>RCC_CFGR_MCO_NOCLOCK 0x00000000U
<01>RCC_CFGR_MCO_SYSCLK 0x04000000U
<01>RCC_CFGR_MCO_HSI 0x05000000U
<01>RCC_CFGR_MCO_HSE 0x06000000U
<01>RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U
<01>RCC_CFGR_MCOSEL RCC_CFGR_MCO
<01>RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
<01>RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
<01>RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
<01>RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
<01>RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
<01>RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
<01>RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
<01>RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
<01>RCC_CIR_LSIRDYF_Pos (0U)
<01>RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
<01>RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
<01>RCC_CIR_LSERDYF_Pos (1U)
<01>RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
<01>RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
<01>RCC_CIR_HSIRDYF_Pos (2U)
<01>RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
<01>RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
<01>RCC_CIR_HSERDYF_Pos (3U)
<01>RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
<01>RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
<01>RCC_CIR_PLLRDYF_Pos (4U)
<01>RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
<01>RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
<01>RCC_CIR_CSSF_Pos (7U)
<01>RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
<01>RCC_CIR_CSSF RCC_CIR_CSSF_Msk
<01>RCC_CIR_LSIRDYIE_Pos (8U)
<01>RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
<01>RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
<01>RCC_CIR_LSERDYIE_Pos (9U)
<01>RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
<01>RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
<01>RCC_CIR_HSIRDYIE_Pos (10U)
<01>RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
<01>RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
<01>RCC_CIR_HSERDYIE_Pos (11U)
<01>RCC_CIR_HSERDYIE_

NonMaskableInt_IRQnrHardFault_IRQnsMemoryManagement_IRQntBusFault_IRQnuUsageFault_IRQnvSVCall_IRQn{DebugMonitor_IRQn|PendSV_IRQn~SysTick_IRQnWWDG_IRQnPVD_IRQn
TAMPER_IRQnRTC_IRQnFLASH_IRQnRCC_IRQnEXTI0_IRQnEXTI1_IRQnEXTI2_IRQnEXTI3_IRQn	EXTI4_IRQn
DMA1_Channel1_IRQnDMA1_Channel2_IRQnDMA1_Channel3_IRQn
DMA1_Channel4_IRQnDMA1_Channel5_IRQnDMA1_Channel6_IRQnDMA1_Channel7_IRQnADC1_2_IRQnUSB_HP_CAN1_TX_IRQnUSB_LP_CAN1_RX0_IRQnCAN1_RX1_IRQnCAN1_SCE_IRQnEXTI9_5_IRQnTIM1_BRK_IRQnTIM1_UP_IRQnTIM1_TRG_COM_IRQnTIM1_CC_IRQnTIM2_IRQnTIM3_IRQnTIM4_IRQnI2C1_EV_IRQnI2C1_ER_IRQn I2C2_EV_IRQn!I2C2_ER_IRQn"SPI1_IRQn#SPI2_IRQn$USART1_IRQn%USART2_IRQn&USART3_IRQn'EXTI15_10_IRQn(RTC_Alarm_IRQn)USBWakeUp_IRQn*TIM8_BRK_IRQn+TIM8_UP_IRQn,TIM8_TRG_COM_IRQn-TIM8_CC_IRQn.ADC3_IRQn/FSMC_IRQn0SDIO_IRQn1TIM5_IRQn2SPI3_IRQn3UART4_IRQn4UART5_IRQn5TIM6_IRQn6TIM7_IRQn7DMA2_Channel1_IRQn8DMA2_Channel2_IRQn9DMA2_Channel3_IRQn:DMA2_Channel4_5_IRQn;iIRQn_Type<12>
<01>
B<>P&SR"#&CR1"#&CR2"#&SMPR1"#&SMPR2"#&JOFR1"#&JOFR2"#&JOFR3"#&JOFR4"# &HTR"#$&LTR"#(&SQR1"#,&SQR2"#0&SQR3"#4&JSQR"#8&JDR1"#<&JDR2"#@&JDR3"#D&JDR4"#H&DR"#L<00>
j
iADC_TypeDef/
<01>
B<>
P&SR"#&CR1"#&CR2"#<03>j

&RESERVEDa#&DR"#LiADC_Common_TypeDef=
<01>
B<><11>
&RESERVED0j
#&DR1"#&DR2"#&DR3"#&DR4"#&DR5"#&DR6"#&DR7"#&DR8"# &DR9"#$&DR10"#(&RTCCR"#,&CR"#0&CSR"#4<03>j


&RESERVED13K#8&DR11"#@&DR12"#D&DR13"#H&DR14"#L&DR15"#P&DR16"#T&DR17"#X&DR18"#\&DR19"#`&DR20"#d&DR21"#h&DR22"#l&DR23"#p&DR24"#t&DR25"#x&DR26"#|&DR27"#<23>
&DR28"#<23>
&DR29"#<23>
&DR30"#<23>
&DR31"#<23>
&DR32"#<23>
&DR33"#<23>
&DR34"#<23>
&DR35"#<23>
&DR36"#<23>
&DR37"#<23>
&DR38"#<23>
&DR39"#<23>
&DR40"#<23>
&DR41"#<23>
&DR42"#<23>
iBKP_TypeDef<12>
<01>
B<>&TIR"#&TDTR"#&TDLR"#&TDHR"#iCAN_TxMailBox_TypeDef
	
<01>B<>&RIR"#&RDTR"#&RDLR"#&RDHR"#iCAN_FIFOMailBox_TypeDef_	
<01>B<>&FR1"#&FR2"#iCAN_FilterRegister_TypeDef<12>	
<01>B<><16>&MCR"#&MSR"#&TSR"#&RF0R"#&RF1R"#&IER"#&ESR"#&BTR"#<03>j

W&RESERVED0P
# <03>A	
&sTxMailBoxl
#<23><03><12>	

&sFIFOMailBox<12>
#<23><03>j

&RESERVED1<12>
#<23>&FMR"#<23>&FM1R"#<23>&RESERVED2j
#<23>&FS1R"#<23>&RESERVED3j
#<23>&FFA1R"#<23>&RESERVED4j
#<23>&FA1R"#<23><03>j

&RESERVED5@#<23><03><12>	

&sFilterRegister]#<23>iCAN_TypeDef<12>	
<01>B<>&DR"#&IDR<12>#&RESERVED0K
#&RESERVED1Z
#&CR"#<00>
K
iCRC_TypeDef<12>
<01>B<>4&CR"#&SWTRIGR"#&DHR12R1"#&DHR12L1"#&DHR8R1"#&DHR12R2"#&DHR12L2"#&DHR8R2"#&DHR12RD"# &DHR12LD"#$&DHR8RD"#(&DOR1"#,&DOR2"#0iDAC_TypeDef<12>
<01>B<>&IDCODE"#&CR"#iDBGMCU_TypeDef<12>
<01>B<>&CCR"#&CNDTR"#&CPAR"#&CMAR"#iDMA_Channel_TypeDef<12>
<01>B<>&ISR"#&IFCR"#iDMA_TypeDefK

<01>B<>&IMR"#&EMR"#&RTSR"#&FTSR"#&SWIER"#&PR"#iEXTI_TypeDef{

<01>B<>$&ACR"#&KEYR"#&OPTKEYR"#&SR"#&CR"#&AR"#&RESERVED"#&OBR"#&WRPR"# iFLASH_TypeDef<12>

<01>B<>&RDP<12>#&USER<12>#&Data0<12>#&Data1<12>#&WRP0<12>#&WRP1<12>#
&WRP2<12>#&WRP3<12>#<00>
Z
iOB_TypeDef`
<01>B<> <03>"
&BTCR<12>#iFSMC_Bank1_TypeDef<12>
<01>B<><03>"
&BWTR#iFSMC_Bank1E_TypeDef
<01>B<> 8&PCR2"#&SR2"#&PMEM2"#&PATT2"#&RESERVED0j
#&ECCR2"#&RESERVED1j
#&RESERVED2j
#&PCR3"# &SR3"#$&PMEM3"#(&PATT3"#,&RESERVED3j
#0&ECCR3"#4iFSMC_Bank2_3_TypeDefK
<01>B<> &PCR4"#&SR4"#&PMEM4"#&PATT4"#&PIO4"#iFSMC_Bank4_TypeDef5
<01>B<>!&CRL"#&CRH"#&IDR"#&ODR"#&BSRR"#&BRR"#&LCKR"#iGPIO_TypeDef<12>
<01>B<>" &EVCR"#&MAPR"#<03>""
&EXTICR#&RESERVED0j
#&MAPR2"#iAFIO_TypeDef<12>
<01>B<>#$&CR1"#&CR2"#&OAR1"#&OAR2"#&DR"#&SR1"#&SR2"#&CCR"#&TRISE"# iI2C_TypeDefd
<01>B<>$&KR"#&PR"#&RLR"#&SR"#iIWDG_TypeDef<12>
<01>B<>$&CR"#&CSR"#iPWR_TypeDef&
<01>B<>%(&CR"#&CFGR"#&CIR"#&APB2RSTR"#&APB1RSTR"#&AHBENR"#&APB2ENR"#&APB1ENR"#&BDCR"# &CSR"#$iRCC_TypeDefT
<01>B<>&(&CRH"#&CRL"#&PRLH"#&PRLL"#&DIVH"#&DIVL"#&CNTH"#&CNTL"#&ALRH"# &ALRL"#$iRTC_TypeDef<12>
<01>B<>)<29>
&POWER"#&CLKCR"#&ARG"#&CMD"#&RESPCMD"#&RESP1"#&RESP2"#&RESP3"#&RESP4"# &DTIMER"#$&DLEN"#(&DCTRL"#,&DCOUNT"#0&STA"#4&ICR"#8&MASK"#<<03>(j


&RESERVED0O#@&FIFOCNT"#H<03>)j

&RESERVED1z#L&FIFO"#<23>
iSDIO_TypeDef<12>
<01>B<>*$&CR1"#&CR2"#&SR"#&DR"#&CRCPR"#&RXCRCR"#&TXCRCR"#&I2SCFGR"#&I2SPR"# iSPI_TypeDef<12>
<01>B<>,T&CR1"#&CR2"#&SMCR"#&DIER"#&SR"#&EGR"#&CCMR1"#&CCMR2"#&CCER"# &CNT"#$&PSC"#(&ARR"#,&RCR"#0&CCR1"#4&CCR2"#8&CCR3"#<&CCR4"#@&BDTR"#D&DCR"#H&DMAR"#L&OR"#PiTIM_TypeDefA
<01>B<>-&SR"#&DR"#&BRR"#&CR1"#&CR2"#&CR3"#&GTPR"#iUSART_TypeDefL
<01>B<>0T&EP0R<12>#&RESERVED0<12>#&EP1R<12>#&RESERVED1<12>#&EP2R<12>#&RESERVED2<12>#
&EP3R<12>#&RESERVED3<12>#&EP4R<12>#&RESERVED4<12>#&EP5R<12>#&RESERVED5<12>#&EP6R<12>#&RESERVED6<12>#&EP7R<12>#<03>/<12>
&RESERVED7<12>#&CNTR<12>#@&RESERVED8<12>#B&ISTR<12>#D&RESERVED9<12>#F&FNR<12>#H&RESERVEDA<12>#J&DADDR<12>#L&RESERVEDB<12>#N&BTABLE<12>#P&RESERVEDC<12>#RiUSB_TypeDef<12>
<01>B<>0&CR"#&CFR"#&SR"#iWWDG_TypeDefP
<01>
RSTU

__STM32F1xx_HAL_H 
X__HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
Y__HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
^__HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
___HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
e__HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
f__HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
m__HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
n__HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
u__HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
v__HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
}__HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
~__HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
<01>
__HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
<01>
__HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
<01>
__HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
<01>
__HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
<01>
__HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
<01>
__HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
<01>
__HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
<01>
__HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
<01>
__HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
<01>
__HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
<01>
__HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
<01>
__HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
<01>
__HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
<01>
__HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
<01>IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || ((FREQ) == HAL_TICK_FREQ_1KHZ))|p






../Drivers/STM32F1xx_HAL_Driver/Inc/../Core/Inc/stm32f1xx_hal.h
stm32f1xx_hal_conf.h

<01>
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<19>
HAL_TICK_FREQ_10HZdHAL_TICK_FREQ_100HZ
HAL_TICK_FREQ_1KHZ
HAL_TICK_FREQ_DEFAULT
iHAL_TickFreqTypeDef<12>
7<03>
j
<00>
uwTickJ


<01>
uwTickPrioj


<01>
uwTickFreq/


7<00>
Q
uwTick_
uwTickPrios
uwTickFreq
WXY

'__STM32F1XX_H 
5STM32F1 
___STM32F1_CMSIS_VERSION_MAIN (0x04)
`__STM32F1_CMSIS_VERSION_SUB1 (0x03)
a__STM32F1_CMSIS_VERSION_SUB2 (0x03)
b__STM32F1_CMSIS_VERSION_RC (0x00)
c__STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24) |(__STM32F1_CMSIS_VERSION_SUB1 << 16) |(__STM32F1_CMSIS_VERSION_SUB2 << 8 ) |(__STM32F1_CMSIS_VERSION_RC))<03>

<01>
IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
<01>
SET_BIT(REG,BIT) ((REG) |= (BIT))
<01>
CLEAR_BIT(REG,BIT) ((REG) &= ~(BIT))
<01>
READ_BIT(REG,BIT) ((REG) & (BIT))
<01>
CLEAR_REG(REG) ((REG) = (0x0))
<01>
WRITE_REG(REG,VAL) ((REG) = (VAL))
<01>
READ_REG(REG) ((REG))
<01>
MODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
<01>
POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
<01>
ATOMIC_SET_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_CLEAR_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_MODIFY_REG(REG,CLEARMSK,SETMASK) do { uint32_t val; do { val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_SETH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_CLEARH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_MODIFYH_REG(REG,CLEARMSK,SETMASK) do { uint16_t val; do { val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)<03>
<00><00>






../Drivers/CMSIS/Device/ST/STM32F1xx/Include/../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx.h
stm32f103xe.h
stm32f1xx_hal.h

l
../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<19>

RESETSET
iFlagStatus<12>
<01>
iITStatus<12>
<01>
<19>
DISABLEENABLE
iFunctionalState

<01>
<19>
SUCCESSERROR
iErrorStatus>

<01>

[\]

STM32_HAL_LEGACY 
$AES_FLAG_RDERR CRYP_FLAG_RDERR
%AES_FLAG_WRERR CRYP_FLAG_WRERR
&AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
'AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
(AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
0ADC_RESOLUTION12b ADC_RESOLUTION_12B
1ADC_RESOLUTION10b ADC_RESOLUTION_10B
2ADC_RESOLUTION8b ADC_RESOLUTION_8B
3ADC_RESOLUTION6b ADC_RESOLUTION_6B
4OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
5OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
6EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
7EOC_SEQ_CONV ADC_EOC_SEQ_CONV
8EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
9REGULAR_GROUP ADC_REGULAR_GROUP
:INJECTED_GROUP ADC_INJECTED_GROUP
;REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
<AWD_EVENT ADC_AWD_EVENT
=AWD1_EVENT ADC_AWD1_EVENT
>AWD2_EVENT ADC_AWD2_EVENT
?AWD3_EVENT ADC_AWD3_EVENT
@OVR_EVENT ADC_OVR_EVENT
AJQOVF_EVENT ADC_JQOVF_EVENT
BALL_CHANNELS ADC_ALL_CHANNELS
CREGULAR_CHANNELS ADC_REGULAR_CHANNELS
DINJECTED_CHANNELS ADC_INJECTED_CHANNELS
ESYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
FSYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
GADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
HADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
IADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
JADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
KADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
LADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
MADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV
USART_CLOCK_DISABLED USART_CLOCK_DISABLE
<01>
USART_CLOCK_ENABLED USART_CLOCK_ENABLE
<01>
USARTNACK_ENABLED USART_NACK_ENABLE
<01>
USARTNACK_DISABLED USART_NACK_DISABLE
<01>
CFR_BASE WWDG_CFR_BASE
<01>
CAN_FilterFIFO0 CAN_FILTER_FIFO0
<01>
CAN_FilterFIFO1 CAN_FILTER_FIFO1
<01>
CAN_IT_RQCP0 CAN_IT_TME
<01>
CAN_IT_RQCP1 CAN_IT_TME
<01>
CAN_IT_RQCP2 CAN_IT_TME
<01>
INAK_TIMEOUT CAN_TIMEOUT_VALUE
<01>
SLAK_TIMEOUT CAN_TIMEOUT_VALUE
<01>
CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
<01>
CAN_TXSTATUS_OK ((uint8_t)0x01U)
<01>
CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
<01>
VLAN_TAG ETH_VLAN_TAG
<01>
MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
<01>
MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
<01>
JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
<01>
MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
<01>
MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
<01>
MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
<01>
DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
<01>
ETH_MMCCR 0x00000100U
<01>
ETH_MMCRIR 0x00000104U
<01>
ETH_MMCTIR 0x00000108U
<01>
ETH_MMCRIMR 0x0000010CU
<01>
ETH_MMCTIMR 0x00000110U
<01>
ETH_MMCTGFSCCR 0x0000014CU
<01>
ETH_MMCTGFMSCCR 0x00000150U
<01>
ETH_MMCTGFCR 0x00000168U
<01>
ETH_MMCRFCECR 0x00000194U
<01>
ETH_MMCRFAECR 0x00000198U
<01>
ETH_MMCRGUFCR 0x000001C4U
<01>
ETH_MAC_TXFIFO_FULL 0x02000000U
<01>
ETH_MAC_TXFIFONOT_EMPTY 0x01000000U
<01>
ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U
<01>
ETH_MAC_TXFIFO_IDLE 0x00000000U
<01>
ETH_MAC_TXFIFO_READ 0x00100000U
<01>
ETH_MAC_TXFIFO_WAITING 0x00200000U
<01>
ETH_MAC_TXFIFO_WRITING 0x00300000U
<01>
ETH_MAC_TRANSMISSION_PAUSE 0x00080000U
<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U
<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U
<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U
<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U
<01>
ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U
<01>
ETH_MAC_RXFIFO_EMPTY 0x00000000U
<01>
ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U
<01>
ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U
<01>
ETH_MAC_RXFIFO_FULL 0x00000300U
<01>
ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U
<01>
ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U
<01>
ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U
<01>
ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U
<01>
ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U
<01>
ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U
<01>
ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U
<01>
HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
<01>
DCMI_IT_OVF DCMI_IT_OVR
<01>
DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
<01>
DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
<01>
HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
<01>
HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
<01>
HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
<01>HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
<01>HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
<01>HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
<01>HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
<01>HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
<01>HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
<01>HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
<01>HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
<01>HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
<01>HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
<01>HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
<01>HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
<01>HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
<01>HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
<01>HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
<01>HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
<01>HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
<01>HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
<01>HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
<01>HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
<01>HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
<01>HAL_DBG_LowPowerConfig(Periph,cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
<01>HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
<01>HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
<01>HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
<01>HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
<01>HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
<01>FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
<01>FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
<01>FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
<01>HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
<01>HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
<01>HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
<01>HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
<01>HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
<01>HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
<01>HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
<01>HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
<01>HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus,cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
<01>HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
<01>HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
<01>HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
<01>HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
<01>HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
<01>HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
<01>HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
<01>HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
<01>HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
<01>HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
<01>HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
<01>HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
<01>HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
<01>HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
<01>HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
<01>HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
<01>HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
<01>HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
<01>HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
<01>HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
<01>PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
<01>PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
<01>PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
<01>PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
<01>PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
<01>PWR_MODE_EVENT_FALLING
__HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
<01>
__HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
<01>
__HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
<01>
__HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
<01>
__HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
<01>
__HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
<01>
__HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
<01>
__HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
<01>
__HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
<01>
__HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
<01>
__HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
<01>
__HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
<01>__HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
<01>__HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
<01>__HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
<01>__HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
<01>__HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
<01>__HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
<01>__HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
<01>__HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
<01>__HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
<01>__HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
<01>__HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
<01>__HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
<01>__HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
<01>__HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
<01>__HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
<01>__HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
<01>__HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
<01>__HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
<01>__HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
<01>__HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
<01>__HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
<01>__HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
<01>__HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
<01>__HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
<01>__HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
<01>__HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
<01>__HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
<01>__HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
<01>__HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
<01>__HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
<01>__HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
<01>__HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
<01>__HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
<01>__HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
<01>__HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
<01>__HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST))
<01>__HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
<01>__HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
<01>__HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
<01>__HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
<01>
__HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
<01>
__HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
<01>
__HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
<01>
__HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))ti






../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
stm32f1xx_hal_def.h


d../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARMB<>(&OscillatorTypej
#&HSEStatej
#&HSEPredivValuej
#&LSEStatej
#&HSIStatej
#&HSICalibrationValuej
#&LSIStatej
#&PLL
#iRCC_OscInitTypeDef<12>
<01>B<>&PeriphClockSelec
RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
<01>
RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
<01>
RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
<01>
CR_REG_INDEX ((uint8_t)1)
<01>
BDCR_REG_INDEX ((uint8_t)2)
<01>
CSR_REG_INDEX ((uint8_t)3)
<01>
RCC_FLAG_MASK ((uint8_t)0x1F)
<01>
__HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
<01>
__HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
<01>
__HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
<01>
__HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
<01>
IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || ((__SOURCE__) == RCC_PLLSOURCE_HSE))
<01>
IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
<01>
IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || ((__HSE__) == RCC_HSE_BYPASS))
<01>
IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS))
<01>
IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
<01>
IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
<01>
IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
<01>
IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON))
<01>
IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
<01>
IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
<01>
IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
<01>
IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512))
<01>
IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || ((__PCLK__) == RCC_HCLK_DIV16))
<01>
IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
<01>
IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
<01>
IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))<00><00>






../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h
stm32f1xx_hal_def.h
stm32f1xx_hal_rcc_ex.h


<01>
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARMB<>&PLLStatej
#&PLLSourcej
#&PLLMULj
#iRCC_PLLInitTypeDef<12>
;B<>&ClockTypej
#&SYSCLKSourcej
#&AHBCLKDividerj
#&APB1CLKDividerj
#&APB2CLKDividerj
#iRCC_ClkInitTypeDef&

P
opq

STM32F1xx_HAL_GPIO_EX_H 
6AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0
7AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1
8AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2
9AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3
:AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4
;AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5
<AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6
=AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7
>AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8
?AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9
@AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10
AAFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11
BAFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12
CAFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13
DAFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14
EAFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15
GIS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || ((__PIN__) == AFIO_EVENTOUT_PIN_1) || ((__PIN__) == AFIO_EVENTOUT_PIN_2) || ((__PIN__) == AFIO_EVENTOUT_PIN_3) || ((__PIN__) == AFIO_EVENTOUT_PIN_4) || ((__PIN__) == AFIO_EVENTOUT_PIN_5) || ((__PIN__) == AFIO_EVENTOUT_PIN_6) || ((__PIN__) == AFIO_EVENTOUT_PIN_7) || ((__PIN__) == AFIO_EVENTOUT_PIN_8) || ((__PIN__) == AFIO_EVENTOUT_PIN_9) || ((__PIN__) == AFIO_EVENTOUT_PIN_10) || ((__PIN__) == AFIO_EVENTOUT_PIN_11) || ((__PIN__) == AFIO_EVENTOUT_PIN_12) || ((__PIN__) == AFIO_EVENTOUT_PIN_13) || ((__PIN__) == AFIO_EVENTOUT_PIN_14) || ((__PIN__) == AFIO_EVENTOUT_PIN_15))
_AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA
`AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB
aAFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC
bAFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD
cAFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE
eIS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || ((__PORT__) == AFIO_EVENTOUT_PORT_B) || ((__PORT__) == AFIO_EVENTOUT_PORT_C) || ((__PORT__) == AFIO_EVENTOUT_PORT_D) || ((__PORT__) == AFIO_EVENTOUT_PORT_E))
|__HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP)
<01>
__HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP)
<01>
__HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP)
<01>
__HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP)
<01>
__HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP)
<01>
__HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP)
<01>
__HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP)
<01>
__HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP)
<01>
__HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(A
&XferAbortCallback#4&ErrorCode<12>#8&DmaBaseAddress<12>#<&ChannelIndexj
#@0/

<00><00><00>

__STM32F1xx_HAL_CORTEX_H 
ZNVIC_PRIORITYGROUP_0 0x00000007U
\NVIC_PRIORITYGROUP_1 0x00000006U
^NVIC_PRIORITYGROUP_2 0x00000005U
`NVIC_PRIORITYGROUP_3 0x00000004U
bNVIC_PRIORITYGROUP_4 0x00000003U
kSYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
lSYSTICK_CLKSOURCE_HCLK 0x00000004U
<01>IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || ((GROUP) == NVIC_PRIORITYGROUP_4))
<01>IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
<01>IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
<01>IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
<01>IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))ti






../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h
stm32f1xx_hal_def.h


<01>../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM
<00><00><00>

__STM32F1xx_HAL_FLASH_EX_H 
+FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U
,OBR_REG_INDEX 1U
-SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))
7IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
9IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
;IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
=IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))
?IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
AIS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
CIS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
EIS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
[IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU)))
mIS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
tIS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
<01>
IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU))))
<01>
FLASH_PAGE_SIZE 0x800U
<01>FLASH_TYPEERASE_PAGES 0x00U
<01>FLASH_TYPEERASE_MASSERASE 0x02U
<01>FLASH_BANK_1 1U
<01>OPTIONBYTE_WRP 0x01U
<01>OPTIONBYTE_RDP 0x02U
<01>OPTIONBYTE_USER 0x04U
<01>OPTIONBYTE_DATA 0x08U
<01>OB_WRPSTATE_DISABLE 0x00U
<01>OB_WRPSTATE_ENABLE 0x01U
<01>OB_WRP_PAGES0TO1 0x00000001U
<01>OB_WRP_PAGES2TO3 0x00000002U
<01>OB_WRP_PAGES4TO5 0x00000004U
<01>OB_WRP_PAGES6TO7 0x00000008U
<01>OB_WRP_PAGES8TO9 0x00000010U
<01>OB_WRP_PAGES10TO11 0x00000020U
<01>OB_WRP_PAGES12TO13 0x00000040U
<01>OB_WRP_PAGES14TO15 0x00000080U
<01>OB_WRP_PAGES16TO17 0x00000100U
<01>OB_WRP_PAGES18TO19 0x00000200U
<01>OB_WRP_PAGES20TO21 0x00000400U
<01>OB_WRP_PAGES22TO23 0x00000800U
<01>OB_WRP_PAGES24TO25 0x00001000U
<01>OB_WRP_PAGES26TO27 0x00002000U
<01>OB_WRP_PAGES28TO29 0x00004000U
<01>OB_WRP_PAGES30TO31 0x00008000U
<01>OB_WRP_PAGES32TO33 0x00010000U
<01>OB_WRP_PAGES34TO35 0x00020000U
<01>OB_WRP_PAGES36TO37 0x00040000U
<01>OB_WRP_PAGES38TO39 0x00080000U
<01>OB_WRP_PAGES40TO41 0x00100000U
<01>OB_WRP_PAGES42TO43 0x00200000U
<01>OB_WRP_PAGES44TO45 0x00400000U
<01>OB_WRP_PAGES46TO47 0x00800000U
<01>OB_WRP_PAGES48TO49 0x01000000U
<01>OB_WRP_PAGES50TO51 0x02000000U
<01>OB_WRP_PAGES52TO53 0x04000000U
<01>OB_WRP
#&LockE
#&ErrorCode#<00>
t
<01>
j
<00>
z
iFLASH_ProcessTypeDef<12>

f
<00><00><00>

__STM32F1xx_HAL_PWR_H 
EPWR_EXTI_LINE_PVD ((uint32_t)0x00010000)
UPWR_PVDLEVEL_0 PWR_CR_PLS_2V2
VPWR_PVDLEVEL_1 PWR_CR_PLS_2V3
WPWR_PVDLEVEL_2 PWR_CR_PLS_2V4
XPWR_PVDLEVEL_3 PWR_CR_PLS_2V5
YPWR_PVDLEVEL_4 PWR_CR_PLS_2V6
ZPWR_PVDLEVEL_5 PWR_CR_PLS_2V7
[PWR_PVDLEVEL_6 PWR_CR_PLS_2V8
\PWR_PVDLEVEL_7 PWR_CR_PLS_2V9
ePWR_PVD_MODE_NORMAL 0x00000000U
fPWR_PVD_MODE_IT_RISING 0x00010001U
gPWR_PVD_MODE_IT_FALLING 0x00010002U
hPWR_PVD_MODE_IT_RISING_FALLING 0x00010003U
iPWR_PVD_MODE_EVENT_RISING 0x00020001U
jPWR_PVD_MODE_EVENT_FALLING 0x00020002U
kPWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U
vPWR_WAKEUP_PIN1 PWR_CSR_EWUP
PWR_MAINREGULATOR_ON 0x00000000U
<01>
PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
<01>
PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
<01>
PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
<01>
PWR_STOPENTRY_WFI ((uint8_t)0x01)
<01>
PWR_STOPENTRY_WFE ((uint8_t)0x02)
<01>
PWR_FLAG_WU PWR_CSR_WUF
<01>
PWR_FLAG_SB PWR_CSR_SBF
<01>
PWR_FLAG_PVDO PWR_CSR_PVDO
<01>
__HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
<01>
__HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
<01>
__HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
<01>
__HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
<01>
__HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
<01>
__HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
<01>
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
<01>
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
<01>
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
<01>
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
<01>__HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
<01>__HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
<01>__HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
<01>__HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
<01>__HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
<01>IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
<01>IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL))
<01>IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
<01>IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
<01>IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
<01>IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))pf






../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
stm32f1xx_hal_def.h



../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARMB<>
&PVDLevelj
#&Modej
#iPWR_PVDTypeDef<12>
7
<00><00><00>

STM32F1xx_HAL_TIM_EX_H ti






../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h
stm32f1xx_hal_def.h


T
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARMB<>&IC1Polarityj
#&IC1Prescalerj
#&IC1Filte
__HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
<01>
__HAL_TIM_SET_AUTORELOAD(__HANDLE__,__AUTORELOAD__) do{ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); (__HANDLE__)->Init.Period = (__AUTORELOAD__); } while(0)
<01>
__HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
<01>
__HAL_TIM_SET_CLOCKDIVISION(__HANDLE__,__CKD__) do{ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); (__HANDLE__)->Instance->CR1 |= (__CKD__); (__HANDLE__)->Init.ClockDivision = (__CKD__); } while(0)
<01>
__HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
<01>
__HAL_TIM_SET_ICPRESCALER(__HANDLE__,__CHANNEL__,__ICPSC__) do{ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); } while(0)
<01>
__HAL_TIM_GET_ICPRESCALER(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) : ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) : (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
<01>
__HAL_TIM_SET_COMPARE(__HANDLE__,__CHANNEL__,__COMPARE__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) : ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
<01>
__HAL_TIM_GET_COMPARE(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) : ((__HANDLE__)->Instance->CCR4))
<01>__HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
<01>__HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
<01>__HAL_TIM_ENABLE_OCxFAST(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
<01>__HAL_TIM_DISABLE_OCxFAST(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
<01>__HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
<01>__HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
<01>__HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__,__CHANNEL__,__POLARITY__) do{ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); }while(0)
<01>TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
<01>TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
<01>IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
<01>IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || ((__BASE__) == TIM_DMABASE_CR2) || ((__BASE__) == TIM_DMABASE_SMCR) || ((__BASE__) == TIM_DMABASE_DIER) || ((__BASE__) == TIM_DMABASE_SR) || ((__BASE__) == TIM_DMABASE_EGR) || ((__BASE__) == TIM_DMABASE_CCMR1) || ((__BASE__) == TIM_DMABASE_CCMR2) || ((__BASE__) == TIM_DMABASE_CCER) || ((__BASE__) == TIM_DMABASE_CNT) || ((__BASE__) == TIM_DMABASE_PSC) || ((__BASE__) == TIM_DMABASE_ARR) || ((__BASE__) == TIM_DMABASE_RCR) || ((__BASE__) == TIM_DMABASE_CCR1) || ((__BASE__) == TIM_DMABASE_CCR2) || ((__BASE__) == TIM_DMABASE_CCR3) || ((__BASE__) == TIM_DMABASE_CCR4) || ((__BASE__) == TIM_DMABASE_BDTR))
<01>IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
<01>IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || ((__MODE__) == TIM_COUNTERMODE_DOWN) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
<01>IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
<01>IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
<01>IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || ((__STATE__) == TIM_OCFAST_ENABLE))
<01>IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || ((__POLARITY__) == TIM_OCPOLARITY_LOW))
<01>IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARMB<>&Prescalerj
#&CounterModej
#&Periodj
#&ClockDivisionj
#&RepetitionCounterj
#&AutoReloadPreloadj
#iTIM_Base_InitTypeDef<12>
KB<>&OCModej
#&Pulsej
#&OCPolarityj
#&OCNPolarityj
#&OCFastModej
#&OCIdleStatej
#&OCNIdleStatej
#iTIM_OC_InitTypeDefx

kB<>$&OCModej
#&Pulsej
#&OCPolarityj
#&OCNPolarityj
#&OCIdleStatej
#&OCNIdleStatej
#&ICPolarityj
#&ICSelectionj
#&ICFilterj
# iTIM_OnePulse_InitTypeDef
<01>
B<>&ICPolarityj
#&ICSelectionj
#&ICPrescalerj
#&ICFilterj
#iTIM_IC_InitTypeDef<12>
<01>
B<>$&EncoderModej
#&IC1Polarityj
#&IC1Selectionj
#&IC1Prescalerj
#&IC1Filterj
#&IC2Polarityj
#&IC2Selectionj
#&IC2Prescalerj
#&IC2Filterj
# iTIM_Encoder_InitTypeDefb
<01>
B<>	&ClockSourcej
#&ClockPolarityj
#&ClockPrescalerj
#&ClockFilterj
#iTIM_ClockConfigTypeDefD
<01>
B<>
&ClearInputStatej
#&ClearInputSourcej
#&ClearInputPolarityj
#&ClearInputPrescalerj
#&ClearInputFilterj
#iTIM_ClearInputConfigTypeDef<12>
<01>
B<>&MasterOutputTriggerj
#&MasterSlaveModej
#iTIM_MasterConfigTypeDefp
<01>
B<>&SlaveModej
#&InputTriggerj
#&TriggerPolarityj
#&TriggerPrescalerj
#&TriggerFilterj
#iTIM_SlaveConfigTypeDef<12>
<01>B<> &OffStateRunModej
#&OffStateIDLEModej
#&LockLevelj
#&DeadTimej
#&BreakStatej
#&BreakPolarityj
#&BreakFilterj
#&AutomaticOutputj
#iTIM_BreakDeadTimeConfigTypeDefb
<01><19>
HAL_TIM_STATE_RESETHAL_TIM_STATE_READY
HAL_TIM_STATE_BUSYHAL_TIM_STATE_TIMEOUTHAL_TIM_STATE_ERRORiHAL_TIM_StateTypeDef?
<01><19>
HAL_TIM_CHANNEL_STATE_RESETHAL_TIM_CHANNEL_STATE_READY
HAL_TIM_CHANNEL_STATE_BUSYiHAL_TIM_ChannelStateTypeDef<12>
<01><19>
HAL_DMA_BURST_STATE_RESETHAL_DMA_BURST_STATE_READY
HAL_DMA_BURST_STATE_BUSYiHAL_TIM_DMABurstStateTypeDefZ
<01><19>
HAL_TIM_ACTIVE_CHANNEL_1
HAL_TIM_ACTIVE_CHANNEL_2HAL_TIM_ACTIVE_CHANNEL_3HAL_TIM_ACTIVE_CHANNEL_4HAL_TIM_ACTIVE_CHANNEL_CLEAREDiHAL_TIM_ActiveChannel<12>
<01>B<>H&Instance?
#&Init\
#&Channelq	#<03>E

&hdma<12>	# &LockE
#<&StateK
#=<03>P

&ChannelState<12>	#><03>P

&ChannelNState
#B&DMABurstStateU
#F080f
<00>
<12><07>
6<08>
<12>iTIM_HandleTypeDef<12>	
<01>
<00><00><00>

__STM32F1xx_HAL_UART_H 
<01>
HAL_UART_ERROR_NONE 0x00000000U
<01>
HAL_UART_ERROR_PE 0x00000001U
<01>
HAL_UART_ERROR_NE 0x00000002U
<01>
HAL_UART_ERROR_FE 0x00000004U
<01>
HAL_UART_ERROR_ORE 0x00000008U
<01>
HAL_UART_ERROR_DMA 0x00000010U
<01>UART_WORDLENGTH_8B 0x00000000U
<01>UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
<01>UART_STOPBITS_1 0x00000000U
<01>UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
<01>UART_PARITY_NONE 0x00000000U
<01>UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
<01>UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
<01>UART_HWCONTROL_NONE 0x00000000U
<01>UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
<01>UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
<01>UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
<01>UART_MODE_RX ((uint32_t)USART_CR1_RE)
<01>UART_MODE_TX ((uint32_t)USART_CR1_TE)
<01>UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
<01>UART_STATE_DISABLE 0x00000000U
<01>UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
<01>UART_OVERSAMPLING_16 0x00000000U
<01>UART_LINBREAKDETECTLENGTH_10B 0x00000000U
<01>UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
<01>UART_WAKEUPMETHOD_IDLELINE 0x00000000U
<01>UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
<01>UART_FLAG_CTS ((uint32_t)USART_SR_CTS)
<01>UART_FLAG_LBD ((uint32_t)USART_SR_LBD)
<01>UART_FLAG_TXE ((uint32_t)USART_SR_TXE)
<01>UART_FLAG_TC ((uint32_t)USART_SR_TC)
<01>UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
<01>UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
<01>UART_FLAG_ORE ((uint32_t)USART_SR_ORE)
<01>UART_FLAG_NE ((uint32_t)USART_SR_NE)
<01>UART_FLAG_FE ((uint32_t)USART_SR_FE)
<01>UART_FLAG_PE ((uint32_t)USART_SR_PE)
<01>UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
<01>UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
<01>UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
<01>UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
<01>UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
<01>UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
<01>UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
<01>UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
<01>HAL_UART_RECEPTION_STANDARD (0x00000000U)
<01>HAL_UART_RECEPTION_TOIDLE (0x00000001U)
<01>__HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ (__HANDLE__)->gState = HAL_UART_STATE_RESET; (__HANDLE__)->RxState = HAL_UART_STATE_RESET; } while(0U)
<01>__HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
<01>__HAL_UART_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
<01>__HAL_UART_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
<01>__HAL_UART_CLEAR_PEFLAG(__HANDLE__) do{ __IO uint32_t tmpreg = 0x00U; tmpreg = (__HANDLE__)->Instance->SR; tmpreg = (__HANDLE__)->Instance->DR; UNUSED(tmpreg); } while(0U)
<01>__HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
<01>__HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
<01>__HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
<01>__HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
<01>__HAL_UART_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
<01>__HAL_UART_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
<01>__HAL_UART_GET_IT_SOURCE(__HANDLE__,__IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((

<01>assert_param(expr) ((void)0U)@
4







../Core/Inc/../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_conf.h
stm32f1xx_hal_rcc.hstm32f1xx_hal_gpio.hstm32f1xx_hal_exti.hstm32f1xx_hal_dma.hstm32f1xx_hal_cortex.hstm32f1xx_hal_flash.hstm32f1xx_hal_pwr.hstm32f1xx_hal_tim.hstm32f1xx_hal_uart.h

<01>../Core/Inc/stm32f1xx_hal_conf.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM
<00><00><00>

__MAIN_H 
<WK_UP_Pin GPIO_PIN_0
=WK_UP_GPIO_Port GPIOA
>K3_Pin GPIO_PIN_8
?K3_GPIO_Port GPIOC
@K4_Pin GPIO_PIN_9
AK4_GPIO_Port GPIOC
BLED_Pin GPIO_PIN_8
CLED_GPIO_Port GPIOAlb






../Core/Inc/../Drivers/STM32F1xx_HAL_Driver/Inc/main.h
stm32f1xx_hal.h

<01>../Core/Inc/main.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM
<00><00><00>

__GPIO_H__ @4






../Core/Inc/gpio.h
main.h


<01>../Core/Inc/gpio.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM
<00><00><00>

__stdarg_h 

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__STDARG_DECLS __CLIBNS
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e__va_copy(dest,src) ((void)((dest) = (src)))
kva_copy(dest,src) ((void)((dest) = (src)))
uva_end(ap) __va_end(ap)XM






D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\stdarg.h


<01>D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\stdarg.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]<00>
void0<12><00>
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D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
stdio.h


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D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\string.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]<00>
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HNULL 0
mEXIT_FAILURE 1
oEXIT_SUCCESS 0
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MB_CUR_MAX ( __aeabi_MB_CUR_MAX() )
<01>__LANGUAGE_LINKAGE_CHANGES_FUNCTION_TYPE 
<01>__fpsr_IXE 0x100000
<01>__fpsr_UFE 0x80000
<01>__fpsr_OFE 0x40000
<01>__fpsr_DZE 0x20000
<01>__fpsr_IOE 0x10000
<01>__fpsr_IXC 0x10
<01>__fpsr_UFC 0x8
<01>__fpsr_OFC 0x4
<01>__fpsr_DZC 0x2
<01>__fpsr_IOC 0x1<02>__LONGLONGdX






D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h
stdio.h


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Input Comments:p5684-3Component: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide vartable.oComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]ArmCC --cpp --split_sections --debug -c -otemplate\vartable.o --depend=template\vartable.d --cpu=Cortex-M3 --apcs=interwork -O3 --diag_suppress=9931 -I../Core/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I.\bsp_Device -I.\bsp_System -I.\RTE\_template -ID:\SOFTWARE\Keil_v5\ARM\PACK\ARM\CMSIS\5.9.0\CMSIS\Core\Include -ID:\SOFTWARE\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\1.0.5\Device\Include -D__UVISION_VERSION=537 -D_RTE_ -DSTM32F10X_HD -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F103xE --omf_browse=template\vartable.crf bsp_System\vartable.cppp-
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U+UlU/<00><02><00><02>I;P;c;o;V.ARM.attributes.strtab.shstrtab.rel.debug_pubnames.rel.debug_frame.rel.debug_line.rel.debug_info.rel.ARM.exidx.reli._Z9u32Endianj.symtab.comment.arm_vfe_header__ARM_grp..debug_abbrev.group.2_8M0000_tpM4SoO0Naf_000000__ARM_grp.vartable.cpp.2_kG2000_6fATlh0Xk21_l00000__ARM_grp.bsp_PrintArt.h.2_waA100_EZbTO1ncOGd_m10000__ARM_grp.usart.h.2_Fo7300_I1H5Xg$78ne_920000__ARM_grp.stdlib.h.2_Yq1000_ga5O7Uo6Yj1_300000__ARM_grp.string.h.2_BX1000_R9yEUUIdVod_700000__ARM_grp.stdarg.h.2_A$0000_GVPHKELl1X9_300000__ARM_grp.gpio.h.2_MR0000_6OyrTpnGa9d_300000__ARM_grp.main.h.2_wY0000_P4teGi5I2C7_300000__ARM_grp.stm32f1xx_hal_conf.h.2_Ed2000_wywgJupEleb_300000__ARM_grp.stm32f1xx_hal_uart.h.2_QrB100_Jo2y$Mr8gkd_010000__ARM_grp.stm32f1xx_hal_tim.h.2_8gM100_$O2lXnUDC71_K10000__ARM_grp.stm32f1xx_hal_tim_ex.h.2_Ud1000_ZxfRmLFBpea_a00000__ARM_grp.stm32f1xx_hal_pwr.h.2_oK2000_nZ5BPqImzY6_800000__ARM_grp.stm32f1xx_hal_flash.h.2_Ya2000_EoWtPlQ7cu1_c00000__ARM_grp.stm32f1xx_hal_flash_ex.h.2_0m3000_hxMYhuc4zZa_i00000__ARM_grp.stm32f1xx_hal_cortex.h.2_gg1000_OQYi8ICscy1_300000__ARM_grp.stm32f1xx_hal_dma.h.2_Qsy100_0p3O3gaEd20_J00000__ARM_grp.stm32f1xx_hal_dma_ex.h.2_wW2000_A04QKq4Too9_300000__ARM_grp.stm32f1xx_hal_exti.h.2_Qq2000_xpwTjTXHK$4_b00000__ARM_grp.stm32f1xx_hal_gpio.h.2_ot2000_X4ifryQPBif_a00000__ARM_grp.stm32f1xx_hal_gpio_ex.h.2_Ub4000_ngtrEZclQJa_300000__ARM_grp.stm32f1xx_hal_rcc.h.2_gfc000_nkL52EMIXe1_e00000__ARM_grp.stm32f1xx_hal_rcc_ex.h.2_MGe000_a9bLzacZPc3_v00000__ARM_grp.stm32f1xx_hal_def.h.2_wk1000_FvWZiGu4F_0_300000__ARM_grp.stddef.h.2_UY0000_VXMehDdzAme_300000__ARM_grp.stm32_hal_legacy.h.2_c2P000_u4oHfGuP3Y2_300000__ARM_grp.stm32f1xx.h.2_8S1000_gj$zac7Q_W2_300000__ARM_grp.stm32f1xx_hal.h.2_724000_Rzk1e1mUox5_h00000__ARM_grp.stm32f103xe.h.2_stZ200_nc9jYXFpQob_r00000__ARM_grp.system_stm32f1xx.h.2_mo2000_xejZonfYXzd_h00000__ARM_grp.core_cm3.h.2_zuh300_8oMZstvSPE3_p40000__ARM_grp.cmsis_compiler.h.2_gV0000_zMcfeH5WZb6_300000__ARM_grp.cmsis_armcc.h.2_Iu2000_mtYSqJOB_v2_O00000__ARM_grp.cmsis_version.h.2_8X0000_DgZn8yK4Asb_300000__ARM_grp.CallBack.h.2_AR0000_8n_yPUhJfA2_300000__ARM_grp.vartable.h.2_QW0000_YXJQX08vMCa_300000__ARM_grp.stdio.h.2_Ml1000_U_UtJvXZoKb_700000__ARM_grp.varint.h.2_Iw1000_Domp9CeEM96_e00000__ARM_grp.stdint.h.2_Ia1000_2R4Eswy5qxe_300000__ARM_grp.User.h.2_MW0000_LudWk9AoKIb_300000.debug_abbrev__ARM_asm.debug_abbrev.1.debug_macinfo.debug_loci._Z9u16Endiant.rrx_text.revsh_text.rev16_textLib$$Request$$cpplibLib$$Request$$armlib__ARM_grp..debug_pubnames$vartable.cpp$.2_kG2000_6fATlh0Xk21_l00000__ARM_grp..debug_pubnames$usart.h$.2_Fo7300_I1H5Xg$78ne_920000__ARM_grp..debug_pubnames$system_stm32f1xx.h$.2_mo2000_xejZonfYXzd_h00000__ARM_grp..debug_pubnames$string.h$.2_BX1000_R9yEUUIdVod_700000__ARM_grp..debug_pubnames$stm32f1xx_hal.h$.2_724000_Rzk1e1mUox5_h00000__ARM_grp..debug_pubnames$core_cm3.h$.2_zuh300_8oMZstvSPE3_p40000__ARM_grp..debug_macinfo$vartable.h$.2_QW0000_YXJQX08vMCa_300000__ARM_grp..debug_macinfo$vartable.cpp$.2_kG2000_6fATlh0Xk21_l00000__ARM_grp..debug_macinfo$varint.h$.2_Iw1000_Domp9CeEM96_e00000__ARM_grp..debug_macinfo$usart.h$.2_Fo7300_I1H5Xg$78ne_920000__ARM_grp..debug_macinfo$system_stm32f1xx.h$.2_mo2000_xejZonfYXzd_h00000__ARM_grp..debug_macinfo$string.h$.2_BX1000_R9yEUUIdVod_700000__ARM_grp..debug_macinfo$stm32f1xx_hal_uart.h$.2_QrB100_Jo2y$Mr8gkd_010000__ARM_grp..debug_macinfo$stm32f1xx_hal_tim_ex.h$.2_Ud1000_ZxfRmLFBpea_a00000__ARM_grp..debug_macinfo$stm32f1xx_hal_tim.h$.2_8gM100_$O2lXnUDC71_K10000__ARM_grp..debug_macinfo$stm32f1xx_hal_rcc_ex.h$.2_MGe000_a9bLzacZPc3_v00000__ARM_grp..debug_macinfo$stm32f1xx_hal_rcc.h$.2_gfc000_nkL52
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