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<01>__NVIC_DisableIRQ3IRQnR<>
<01>__NVIC_GetPendingIRQj
3IRQnz__resultj

S<>
<01>__NVIC_SetPendingIRQ3IRQnS<>
<01>__NVIC_ClearPendingIRQ3IRQnR<>
<01>__NVIC_GetActivej
3IRQnz__resultj

S<>
<01>__NVIC_SetPriority3IRQn3j
priorityR<>
<01>__NVIC_GetPriorityj
3IRQnz__resultj

R<>
<01>
NVIC_EncodePriorityj
3j
PriorityGroup3j
PreemptPriority3j
SubPriorityz__resultj

uPriorityGroupTmpj
uPreemptPriorityBitsj
uSubPriorityBitsj
S<>
<01>
NVIC_DecodePriority3j
Priority3j
PriorityGroup3<12>pPreemptPriority3<12>pSubPriorityuPriorityGroupTmpj
uPreemptPriorityBitsj
uSubPriorityBitsj
0j
S<>
<01>
__NVIC_SetVector3IRQn3j
vectoruvectors<12>R<> 
<01>
__NVIC_GetVectorj
3IRQnz__resultj

uvectors<12>S<> 
<01>
"__NVIC_SystemResetR<> 
<01>SCB_GetFPUTypej
z__resultj

R<>!
<01>SysTick_Configj
3j
ticksz__resultj

R<>!
<01>ITM_SendCharj
3j
chz__resultj

R<>"
<01>ITM_ReceiveChar-
z__result-

uch-
R<>"
<01>ITM_CheckChar-
z__result-

L<00>ITM_RxBuffer
rstu

 __SYSTEM_STM32F10X_H `W






../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h


 
../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]C:\Users\XerolySkinner\Desktop\MDK-ARM<00>
SystemCoreClockj


K
<03>
<12>
<00>
AHBPrescTable<12>

<03><12>
<00>
APBPrescTable



F$
<00>SystemCoreClock<00>AHBPrescTable

APBPrescTable
wxy

&__STM32F103xE_H 
2__CM3_REV 0x0200U
3__MPU_PRESENT 0U
4__NVIC_PRIO_BITS 4U
5__Vendor_SysTickConfig 0U<03>
<03>
<03>

<01>FLASH_BASE 0x08000000UL
<01>FLASH_BANK1_END 0x0807FFFFUL
<01>SRAM_BASE 0x20000000UL
<01>PERIPH_BASE 0x40000000UL
<01>SRAM_BB_BASE 0x22000000UL
<01>PERIPH_BB_BASE 0x42000000UL
<01>FSMC_BASE 0x60000000UL
<01>FSMC_R_BASE 0xA0000000UL
<01>APB1PERIPH_BASE PERIPH_BASE
<01>APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
<01>AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
<01>TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)
<01>TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)
<01>TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)
<01>TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL)
<01>TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL)
<01>TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL)
<01>RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)
<01>WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)
<01>IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)
<01>SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)
<01>SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL)
<01>USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)
<01>USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)
<01>UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL)
<01>UART5_BASE (APB1PERIPH_BASE + 0x00005000UL)
<01>I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)
<01>I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)
<01>CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL)
<01>BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL)
<01>PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)
<01>DAC_BASE (APB1PERIPH_BASE + 0x00007400UL)
<01>AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL)
<01>EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)
<01>GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL)
<01>GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL)
<01>GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL)
<01>GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL)
<01>GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL)
<01>GPIOF_BASE (APB2PERIPH_BASE + 0x00001C00UL)
<01>GPIOG_BASE (APB2PERIPH_BASE + 0x00002000UL)
<01>ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL)
<01>ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL)
<01>TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)
<01>SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)
<01>TIM8_BASE (APB2PERIPH_BASE + 0x00003400UL)
<01>USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)
<01>ADC3_BASE (APB2PERIPH_BASE + 0x00003C00UL)
<01>SDIO_BASE (PERIPH_BASE + 0x00018000UL)
<01>DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
<01>DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL)
<01>DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL)
<01>DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL)
<01>DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL)
<01>DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL)
<01>DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL)
<01>DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL)
<01>DMA2_BASE (AHBPERIPH_BASE + 0x00000400UL)
<01>DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408UL)
<01>DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CUL)
<01>DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430UL)
<01>DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444UL)
<01>DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458UL)
<01>RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
<01>CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
<01>FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL)
<01>FLASHSIZE_BASE 0x1FFFF7E0UL
<01>UID_BASE 0x1FFFF7E8UL
<01>OB_BASE 0x1FFFF800UL
<01>FSMC_BANK1 (FSMC_BASE)
<01>FSMC_BANK1_1 (FSMC_BANK1)
<01>FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000UL)
<01>FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000UL)
<01>FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000UL)
<01>FSMC_BANK2 (FSMC_BASE + 0x10000000UL)
<01>FSMC_BANK3 (FSMC_BASE + 0x20000000UL)
<01>FSMC_BANK4 (FSMC_BASE + 0x30000000UL)
<01>FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x00000000UL)
<01>FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x00000104UL)
<01>FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x00000060UL)
<01>FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x000000A0UL)
<01>DBGMCU_BASE 0xE0042000UL
<01>USB_BASE (APB1PERIPH_BASE + 0x00005C00UL)
<01>USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL)
<01>TIM2 ((TIM_TypeDef *)TIM2_BASE)
<01>TIM3 ((TIM_TypeDef *)TIM3_BASE)
<01>TIM4 ((TIM_TypeDef *)TIM4_BASE)
<01>TIM5 ((TIM_TypeDef *)TIM5_BASE)
<01>TIM6 ((TIM_TypeDef *)TIM6_BASE)
<01>TIM7 ((TIM_TypeDef *)TIM7_BASE)
<01>RTC ((RTC_TypeDef *)R
RCC_CR_HSION RCC_CR_HSION_Msk
<01>
RCC_CR_HSIRDY_Pos (1U)
<01>
RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
<01>
RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
<01>
RCC_CR_HSITRIM_Pos (3U)
<01>
RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
<01>
RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
<01>
RCC_CR_HSICAL_Pos (8U)
<01>
RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
<01>
RCC_CR_HSICAL RCC_CR_HSICAL_Msk
<01>
RCC_CR_HSEON_Pos (16U)
<01>
RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
<01>
RCC_CR_HSEON RCC_CR_HSEON_Msk
<01>
RCC_CR_HSERDY_Pos (17U)
<01>
RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
<01>
RCC_CR_HSERDY RCC_CR_HSERDY_Msk
<01>
RCC_CR_HSEBYP_Pos (18U)
<01>
RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
<01>
RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
<01>
RCC_CR_CSSON_Pos (19U)
<01>
RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
<01>
RCC_CR_CSSON RCC_CR_CSSON_Msk
<01>
RCC_CR_PLLON_Pos (24U)
<01>
RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
<01>
RCC_CR_PLLON RCC_CR_PLLON_Msk
<01>
RCC_CR_PLLRDY_Pos (25U)
<01>
RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
<01>
RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
<01>
RCC_CFGR_SW_Pos (0U)
<01>
RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
<01>
RCC_CFGR_SW RCC_CFGR_SW_Msk
<01>
RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
<01>
RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
<01>
RCC_CFGR_SW_HSI 0x00000000U
<01>
RCC_CFGR_SW_HSE 0x00000001U
<01>
RCC_CFGR_SW_PLL 0x00000002U
<01>
RCC_CFGR_SWS_Pos (2U)
<01>
RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
<01>
RCC_CFGR_SWS RCC_CFGR_SWS_Msk
<01>
RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
<01>
RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
<01>
RCC_CFGR_SWS_HSI 0x00000000U
<01>
RCC_CFGR_SWS_HSE 0x00000004U
<01>
RCC_CFGR_SWS_PLL 0x00000008U
<01>
RCC_CFGR_HPRE_Pos (4U)
<01>
RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
<01>
RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
<01>
RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
<01>
RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
<01>
RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
<01>
RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
<01>
RCC_CFGR_HPRE_DIV1 0x00000000U
<01>
RCC_CFGR_HPRE_DIV2 0x00000080U
<01>
RCC_CFGR_HPRE_DIV4 0x00000090U
<01>
RCC_CFGR_HPRE_DIV8 0x000000A0U
<01>
RCC_CFGR_HPRE_DIV16 0x000000B0U
<01>
RCC_CFGR_HPRE_DIV64 0x000000C0U
<01>
RCC_CFGR_HPRE_DIV128 0x000000D0U
<01>
RCC_CFGR_HPRE_DIV256 0x000000E0U
<01>
RCC_CFGR_HPRE_DIV512 0x000000F0U
<01>
RCC_CFGR_PPRE1_Pos (8U)
<01>
RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
<01>
RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
<01>
RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
<01>
RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
<01>
RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
<01>
RCC_CFGR_PPRE1_DIV1 0x00000000U
<01>
RCC_CFGR_PPRE1_DIV2 0x00000400U
<01>
RCC_CFGR_PPRE1_DIV4 0x00000500U
<01>
RCC_CFGR_PPRE1_DIV8 0x00000600U
<01>
RCC_CFGR_PPRE1_DIV16 0x00000700U
<01>
RCC_CFGR_PPRE2_Pos (11U)
<01>
RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
<01>
RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
<01>
RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
<01>
RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
<01>
RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
<01>
RCC_CFGR_PPRE2_DIV1 0x00000000U
<01>
RCC_CFGR_PPRE2_DIV2 0x00002000U
<01>
RCC_CFGR_PPRE2_DIV4 0x00002800U
<01>
RCC_CFGR_PPRE2_DIV8 0x00003000U
<01>
RCC_CFGR_PPRE2_DIV16 0x00003800U
<01>
RCC_CFGR_ADCPRE_Pos (14U)
<01>
RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos)
<01>
RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk
<01>
RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos)
<01>
RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos)
<01>
RCC_CFGR_ADCPRE_DIV2 0x00000000U
<01>
RCC_CFGR_ADCPRE_DIV4 0x00004000U
<01>
RCC_CFGR_ADCPRE_DIV6 0x00008000U
<01>
RCC_CFGR_ADCPRE_DIV8 0x0000C000U
<01>
RCC_CFGR_PLLSRC_Pos (16U)
<01>
RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos)
<01>
RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk
<01>
RCC_CFGR_PLLXTPRE_Pos (17U)
<01>
RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos)
<01>
RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk
<01>
RCC_CFGR_PLLMULL_Pos (18U)
<01>
RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos)
<01>
RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk
<01>
RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos)
<01>
RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos)
<01>
RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos)
<01>
RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos)
<01>RCC_CFGR_PLLXTPRE_HSE 0x00000000U
<01>RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U
<01>RCC_CFGR_PLLMULL2 0x00000000U
<01>RCC_CFGR_PLLMULL3_Pos (18U)
<01>RCC_CFGR_PLLMULL3_Msk (0x1UL << RCC_CFGR_PLLMULL3_Pos)
<01>RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk
<01>RCC_CFGR_PLLMULL4_Pos (19U)
<01>RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos)
<01>RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk
<01>RCC_CFGR_PLLMULL5_Pos (18U)
<01>RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos)
<01>RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk
<01>RCC_CFGR_PLLMULL6_Pos (20U)
<01>RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos)
<01>RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk
<01>RCC_CFGR_PLLMULL7_Pos (18U)
<01>RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos)
<01>RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk
<01>RCC_CFGR_PLLMULL8_Pos (19U)
<01>RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos)
<01>RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk
<01>RCC_CFGR_PLLMULL9_Pos (18U)
<01>RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos)
<01>RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk
<01>RCC_CFGR_PLLMULL10_Pos (21U)
<01>RCC_CFGR_PLLMULL10_Msk (0x1UL << RCC_CFGR_PLLMULL10_Pos)
<01>RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk
<01>RCC_CFGR_PLLMULL11_Pos (18U)
<01>RCC_CFGR_PLLMULL11_Msk (0x9UL << RCC_CFGR_PLLMULL11_Pos)
<01>RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk
<01>RCC_CFGR_PLLMULL12_Pos (19U)
<01>RCC_CFGR_PLLMULL12_Msk (0x5UL << RCC_CFGR_PLLMULL12_Pos)
<01>RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk
<01>RCC_CFGR_PLLMULL13_Pos (18U)
<01>RCC_CFGR_PLLMULL13_Msk (0xBUL << RCC_CFGR_PLLMULL13_Pos)
<01>RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk
<01>RCC_CFGR_PLLMULL14_Pos (20U)
<01>RCC_CFGR_PLLMULL14_Msk (0x3UL << RCC_CFGR_PLLMULL14_Pos)
<01>RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk
<01>RCC_CFGR_PLLMULL15_Pos (18U)
<01>RCC_CFGR_PLLMULL15_Msk (0xDUL << RCC_CFGR_PLLMULL15_Pos)
<01>RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk
<01>RCC_CFGR_PLLMULL16_Pos (19U)
<01>RCC_CFGR_PLLMULL16_Msk (0x7UL << RCC_CFGR_PLLMULL16_Pos)
<01>RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk
<01>RCC_CFGR_USBPRE_Pos (22U)
<01>RCC_CFGR_USBPRE_Msk (0x1UL << RCC_CFGR_USBPRE_Pos)
<01>RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk
<01>RCC_CFGR_MCO_Pos (24U)
<01>RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos)
<01>RCC_CFGR_MCO RCC_CFGR_MCO_Msk
<01>RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos)
<01>RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos)
<01>RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos)
<01>RCC_CFGR_MCO_NOCLOCK 0x00000000U
<01>RCC_CFGR_MCO_SYSCLK 0x04000000U
<01>RCC_CFGR_MCO_HSI 0x05000000U
<01>RCC_CFGR_MCO_HSE 0x06000000U
<01>RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U
<01>RCC_CFGR_MCOSEL RCC_CFGR_MCO
<01>RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
<01>RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
<01>RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
<01>RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
<01>RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
<01>RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
<01>RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
<01>RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
<01>RCC_CIR_LSIRDYF_Pos (0U)
<01>RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
<01>RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
<01>RCC_CIR_LSERDYF_Pos (1U)
<01>RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
<01>RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
<01>RCC_CIR_HSIRDYF_Pos (2U)
<01>RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
<01>RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
<01>RCC_CIR_HSERDYF_Pos (3U)
<01>RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
<01>RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
<01>RCC_CIR_PLLRDYF_Pos (4U)
<01>RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
<01>RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
<01>RCC_CIR_CSSF_Pos (7U)
<01>RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
<01>RCC_CIR_CSSF RCC_CIR_CSSF_Msk
<01>RCC_CIR_LSIRDYIE_Pos (8U)
<01>RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
<01>RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
<01>RCC_CIR_LSERDYIE_Pos (9U)
<01>RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
<01>RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
<01>RCC_CIR_HSIRDYIE_Pos (10U)
<01>RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
<01>RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
<01>RCC_CIR_HSERDYIE_Pos (11U)
<01>RCC_CIR_HSERDYIE_

NonMaskableInt_IRQnrHardFault_IRQnsMemoryManagement_IRQntBusFault_IRQnuUsageFault_IRQnvSVCall_IRQn{DebugMonitor_IRQn|PendSV_IRQn~SysTick_IRQnWWDG_IRQnPVD_IRQn
TAMPER_IRQnRTC_IRQnFLASH_IRQnRCC_IRQnEXTI0_IRQnEXTI1_IRQnEXTI2_IRQnEXTI3_IRQn	EXTI4_IRQn
DMA1_Channel1_IRQnDMA1_Channel2_IRQnDMA1_Channel3_IRQn
DMA1_Channel4_IRQnDMA1_Channel5_IRQnDMA1_Channel6_IRQnDMA1_Channel7_IRQnADC1_2_IRQnUSB_HP_CAN1_TX_IRQnUSB_LP_CAN1_RX0_IRQnCAN1_RX1_IRQnCAN1_SCE_IRQnEXTI9_5_IRQnTIM1_BRK_IRQnTIM1_UP_IRQnTIM1_TRG_COM_IRQnTIM1_CC_IRQnTIM2_IRQnTIM3_IRQnTIM4_IRQnI2C1_EV_IRQnI2C1_ER_IRQn I2C2_EV_IRQn!I2C2_ER_IRQn"SPI1_IRQn#SPI2_IRQn$USART1_IRQn%USART2_IRQn&USART3_IRQn'EXTI15_10_IRQn(RTC_Alarm_IRQn)USBWakeUp_IRQn*TIM8_BRK_IRQn+TIM8_UP_IRQn,TIM8_TRG_COM_IRQn-TIM8_CC_IRQn.ADC3_IRQn/FSMC_IRQn0SDIO_IRQn1TIM5_IRQn2SPI3_IRQn3UART4_IRQn4UART5_IRQn5TIM6_IRQn6TIM7_IRQn7DMA2_Channel1_IRQn8DMA2_Channel2_IRQn9DMA2_Channel3_IRQn:DMA2_Channel4_5_IRQn;iIRQn_Type<12>
<01>
B<>P&SR#&CR1#&CR2#&SMPR1#&SMPR2#&JOFR1#&JOFR2#&JOFR3#&JOFR4# &HTR#$&LTR#(&SQR1#,&SQR2#0&SQR3#4&JSQR#8&JDR1#<&JDR2#@&JDR3#D&JDR4#H&DR#L<00>
j
iADC_TypeDef
<01>
B<>P&SR#&CR1#&CR2#<03>j

&RESERVEDK#&DR#LiADC_Common_TypeDef'
<01>
B<><11>
&RESERVED0j
#&DR1#&DR2#&DR3#&DR4#&DR5#&DR6#&DR7#&DR8# &DR9#$&DR10#(&RTCCR#,&CR#0&CSR#4<03>j


&RESERVED135#8&DR11#@&DR12#D&DR13#H&DR14#L&DR15#P&DR16#T&DR17#X&DR18#\&DR19#`&DR20#d&DR21#h&DR22#l&DR23#p&DR24#t&DR25#x&DR26#|&DR27#<23>
&DR28#<23>
&DR29#<23>
&DR30#<23>
&DR31#<23>
&DR32#<23>
&DR33#<23>
&DR34#<23>
&DR35#<23>
&DR36#<23>
&DR37#<23>
&DR38#<23>
&DR39#<23>
&DR40#<23>
&DR41#<23>
&DR42#<23>
iBKP_TypeDef<12>
<01>
B<>&TIR#&TDTR#&TDLR#&TDHR#iCAN_TxMailBox_TypeDef<12>
<01>B<>&RIR#&RDTR#&RDLR#&RDHR#iCAN_FIFOMailBox_TypeDefI	
<01>B<>&FR1#&FR2#iCAN_FilterRegister_TypeDef<12>	
<01>B<><16>&MCR#&MSR#&TSR#&RF0R#&RF1R#&IER#&ESR#&BTR#<03>j

W&RESERVED0:
# <03>+	
&sTxMailBoxV
#<23><03>}	

&sFIFOMailBoxr
#<23><03>j

&RESERVED1<12>
#<23>&FMR#<23>&FM1R#<23>&RESERVED2j
#<23>&FS1R#<23>&RESERVED3j
#<23>&FFA1R#<23>&RESERVED4j
#<23>&FA1R#<23><03>j

&RESERVED5*#<23><03><12>	

&sFilterRegisterG#<23>iCAN_TypeDef<12>	
<01>B<>&DR#&IDR<12>#&RESERVED0K
#&RESERVED1Z
#&CR#<00>
K
iCRC_TypeDef}
<01>B<>4&CR#&SWTRIGR#&DHR12R1#&DHR12L1#&DHR8R1#&DHR12R2#&DHR12L2#&DHR8R2#&DHR12RD# &DHR12LD#$&DHR8RD#(&DOR1#,&DOR2#0iDAC_TypeDef<12>
<01>B<>&IDCODE#&CR#iDBGMCU_TypeDef<12>
<01>B<>&CCR#&CNDTR#&CPAR#&CMAR#iDMA_Channel_TypeDef<12>
<01>B<>&ISR#&IFCR#iDMA_TypeDef5

<01>B<>&IMR#&EMR#&RTSR#&FTSR#&SWIER#&PR#iEXTI_TypeDefe

<01>B<>$&ACR#&KEYR#&OPTKEYR#&SR#&CR#&AR#&RESERVED#&OBR#&WRPR# iFLASH_TypeDef<12>

<01>B<>&RDP<12>#&USER<12>#&Data0<12>#&Data1<12>#&WRP0<12>#&WRP1<12>#
&WRP2<12>#&WRP3<12>#<00>
Z
iOB_TypeDefJ
<01>B<> <03>
&BTCR<12>#iFSMC_Bank1_TypeDef<12>
<01>B<><03>
&BWTR#iFSMC_Bank1E_TypeDef<12>
<01>B<> 8&PCR2#&SR2#&PMEM2#&PATT2#&RESERVED0j
#&ECCR2#&RESERVED1j
#&RESERVED2j
#&PCR3# &SR3#$&PMEM3#(&PATT3#,&RESERVED3j
#0&ECCR3#4iFSMC_Bank2_3_TypeDef5
<01>B<> &PCR4#&SR4#&PMEM4#&PATT4#&PIO4#iFSMC_Bank4_TypeDef
<01>B<>!&CRL#&CRH#&IDR#&ODR#&BSRR#&BRR#&LCKR#iGPIO_TypeDef|
<01>B<>" &EVCR#&MAPR#<03>"
&EXTICR
#&RESERVED0j
#&MAPR2#iAFIO_TypeDef<12>
<01>B<>#$&CR1#&CR2#&OAR1#&OAR2#&DR#&SR1#&SR2#&CCR#&TRISE# iI2C_TypeDefN
<01>B<>#&KR#&PR#&RLR#&SR#iIWDG_TypeDef<12>
<01>B<>$&CR#&CSR#iPWR_TypeDef
<01>B<>%(&CR#&CFGR#&CIR#&APB2RSTR#&APB1RSTR#&AHBENR#&APB2ENR#&APB1ENR#&BDCR# &CSR#$iRCC_TypeDef>
<01>B<>&(&CRH#&CRL#&PRLH#&PRLL#&DIVH#&DIVL#&CNTH#&CNTL#&ALRH# &ALRL#$iRTC_TypeDef<12>
<01>B<>)<29>
&POWER#&CLKCR#&ARG#&CMD#&RESPCMD#&RESP1#&RESP2#&RESP3#&RESP4# &DTIMER#$&DLEN#(&DCTRL#,&DCOUNT#0&STA#4&ICR#8&MASK#<<03>(j


&RESERVED09#@&FIFOCNT#H<03>(j

&RESERVED1d#L&FIFO#<23>
iSDIO_TypeDefj
<01>B<>*$&CR1#&CR2#&SR#&DR#&CRCPR#&RXCRCR#&TXCRCR#&I2SCFGR#&I2SPR# iSPI_TypeDef<12>
<01>B<>,T&CR1#&CR2#&SMCR#&DIER#&SR#&EGR#&CCMR1#&CCMR2#&CCER# &CNT#$&PSC#(&ARR#,&RCR#0&CCR1#4&CCR2#8&CCR3#<&CCR4#@&BDTR#D&DCR#H&DMAR#L&OR#PiTIM_TypeDef+
<01>B<>-&SR#&DR#&BRR#&CR1#&CR2#&CR3#&GTPR#iUSART_TypeDef6
<01>B<>0T&EP0R<12>#&RESERVED0<12>#&EP1R<12>#&RESERVED1<12>#&EP2R<12>#&RESERVED2<12>#
&EP3R<12>#&RESERVED3<12>#&EP4R<12>#&RESERVED4<12>#&EP5R<12>#&RESERVED5<12>#&EP6R<12>#&RESERVED6<12>#&EP7R<12>#<03>/<12>
&RESERVED7x#&CNTR<12>#@&RESERVED8<12>#B&ISTR<12>#D&RESERVED9<12>#F&FNR<12>#H&RESERVEDA<12>#J&DADDR<12>#L&RESERVEDB<12>#N&BTABLE<12>#P&RESERVEDC<12>#RiUSB_TypeDef<12>
<01>B<>0&CR#&CFR#&SR#iWWDG_TypeDef:
<01>
{|}~

__STM32F1xx_HAL_H 
X__HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
Y__HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
^__HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
___HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
e__HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
f__HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
m__HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
n__HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
u__HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
v__HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
}__HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
~__HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
<01>
__HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
<01>
__HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
<01>
__HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
<01>
__HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
<01>
__HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
<01>
__HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
<01>
__HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
<01>
__HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
<01>
__HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
<01>
__HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
<01>
__HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
<01>
__HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
<01>
__HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
<01>
__HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
<01>IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || ((FREQ) == HAL_TICK_FREQ_1KHZ))|p






../Drivers/STM32F1xx_HAL_Driver/Inc/../Core/Inc/stm32f1xx_hal.h
stm32f1xx_hal_conf.h

p
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]C:\Users\XerolySkinner\Desktop\MDK-ARM<19>
HAL_TICK_FREQ_10HZdHAL_TICK_FREQ_100HZ
HAL_TICK_FREQ_1KHZ
HAL_TICK_FREQ_DEFAULT
iHAL_TickFreqTypeDef<12>
7<03>
j
<00>
uwTick4


<01>
uwTickPrioj


<01>
uwTickFreq


7t
;
uwTickI
uwTickPrio]
uwTickFreq
<00><00><00>

'__STM32F1XX_H 
5STM32F1 
___STM32F1_CMSIS_VERSION_MAIN (0x04)
`__STM32F1_CMSIS_VERSION_SUB1 (0x03)
a__STM32F1_CMSIS_VERSION_SUB2 (0x03)
b__STM32F1_CMSIS_VERSION_RC (0x00)
c__STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24) |(__STM32F1_CMSIS_VERSION_SUB1 << 16) |(__STM32F1_CMSIS_VERSION_SUB2 << 8 ) |(__STM32F1_CMSIS_VERSION_RC))<03>

<01>
IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
<01>
SET_BIT(REG,BIT) ((REG) |= (BIT))
<01>
CLEAR_BIT(REG,BIT) ((REG) &= ~(BIT))
<01>
READ_BIT(REG,BIT) ((REG) & (BIT))
<01>
CLEAR_REG(REG) ((REG) = (0x0))
<01>
WRITE_REG(REG,VAL) ((REG) = (VAL))
<01>
READ_REG(REG) ((REG))
<01>
MODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
<01>
POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
<01>
ATOMIC_SET_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_CLEAR_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_MODIFY_REG(REG,CLEARMSK,SETMASK) do { uint32_t val; do { val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_SETH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_CLEARH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_MODIFYH_REG(REG,CLEARMSK,SETMASK) do { uint16_t val; do { val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)<03>
<00><00>






../Drivers/CMSIS/Device/ST/STM32F1xx/Include/../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx.h
stm32f103xe.h
stm32f1xx_hal.h

T
../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]C:\Users\XerolySkinner\Desktop\MDK-ARM<19>

RESETSET
iFlagStatus<12>
<01>
iITStatus<12>
<01>
<19>
DISABLEENABLE
iFunctionalState<12>
<01>
<19>
SUCCESSERROR
iErrorStatus(

<01>

<00><00><00>

STM32_HAL_LEGACY 
$AES_FLAG_RDERR CRYP_FLAG_RDERR
%AES_FLAG_WRERR CRYP_FLAG_WRERR
&AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
'AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
(AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
0ADC_RESOLUTION12b ADC_RESOLUTION_12B
1ADC_RESOLUTION10b ADC_RESOLUTION_10B
2ADC_RESOLUTION8b ADC_RESOLUTION_8B
3ADC_RESOLUTION6b ADC_RESOLUTION_6B
4OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
5OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
6EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
7EOC_SEQ_CONV ADC_EOC_SEQ_CONV
8EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
9REGULAR_GROUP ADC_REGULAR_GROUP
:INJECTED_GROUP ADC_INJECTED_GROUP
;REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
<AWD_EVENT ADC_AWD_EVENT
=AWD1_EVENT ADC_AWD1_EVENT
>AWD2_EVENT ADC_AWD2_EVENT
?AWD3_EVENT ADC_AWD3_EVENT
@OVR_EVENT ADC_OVR_EVENT
AJQOVF_EVENT ADC_JQOVF_EVENT
BALL_CHANNELS ADC_ALL_CHANNELS
CREGULAR_CHANNELS ADC_REGULAR_CHANNELS
DINJECTED_CHANNELS ADC_INJECTED_CHANNELS
ESYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
FSYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
GADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
HADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
IADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
JADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
KADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
LADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
MADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
NADC_EXTERNA
USART_CLOCK_DISABLED USART_CLOCK_DISABLE
<01>
USART_CLOCK_ENABLED USART_CLOCK_ENABLE
<01>
USARTNACK_ENABLED USART_NACK_ENABLE
<01>
USARTNACK_DISABLED USART_NACK_DISABLE
<01>
CFR_BASE WWDG_CFR_BASE
<01>
CAN_FilterFIFO0 CAN_FILTER_FIFO0
<01>
CAN_FilterFIFO1 CAN_FILTER_FIFO1
<01>
CAN_IT_RQCP0 CAN_IT_TME
<01>
CAN_IT_RQCP1 CAN_IT_TME
<01>
CAN_IT_RQCP2 CAN_IT_TME
<01>
INAK_TIMEOUT CAN_TIMEOUT_VALUE
<01>
SLAK_TIMEOUT CAN_TIMEOUT_VALUE
<01>
CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
<01>
CAN_TXSTATUS_OK ((uint8_t)0x01U)
<01>
CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
<01>
VLAN_TAG ETH_VLAN_TAG
<01>
MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
<01>
MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
<01>
JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
<01>
MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
<01>
MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
<01>
MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
<01>
DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
<01>
ETH_MMCCR 0x00000100U
<01>
ETH_MMCRIR 0x00000104U
<01>
ETH_MMCTIR 0x00000108U
<01>
ETH_MMCRIMR 0x0000010CU
<01>
ETH_MMCTIMR 0x00000110U
<01>
ETH_MMCTGFSCCR 0x0000014CU
<01>
ETH_MMCTGFMSCCR 0x00000150U
<01>
ETH_MMCTGFCR 0x00000168U
<01>
ETH_MMCRFCECR 0x00000194U
<01>
ETH_MMCRFAECR 0x00000198U
<01>
ETH_MMCRGUFCR 0x000001C4U
<01>
ETH_MAC_TXFIFO_FULL 0x02000000U
<01>
ETH_MAC_TXFIFONOT_EMPTY 0x01000000U
<01>
ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U
<01>
ETH_MAC_TXFIFO_IDLE 0x00000000U
<01>
ETH_MAC_TXFIFO_READ 0x00100000U
<01>
ETH_MAC_TXFIFO_WAITING 0x00200000U
<01>
ETH_MAC_TXFIFO_WRITING 0x00300000U
<01>
ETH_MAC_TRANSMISSION_PAUSE 0x00080000U
<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U
<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U
<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U
<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U
<01>
ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U
<01>
ETH_MAC_RXFIFO_EMPTY 0x00000000U
<01>
ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U
<01>
ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U
<01>
ETH_MAC_RXFIFO_FULL 0x00000300U
<01>
ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U
<01>
ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U
<01>
ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U
<01>
ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U
<01>
ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U
<01>
ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U
<01>
ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U
<01>
HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
<01>
DCMI_IT_OVF DCMI_IT_OVR
<01>
DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
<01>
DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
<01>
HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
<01>
HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
<01>
HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
<01>HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
<01>HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
<01>HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
<01>HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
<01>HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
<01>HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
<01>HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
<01>HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
<01>HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
<01>HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
<01>HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
<01>HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
<01>HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
<01>HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
<01>HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
<01>HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
<01>HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
<01>HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
<01>HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
<01>HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
<01>HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
<01>HAL_DBG_LowPowerConfig(Periph,cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
<01>HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
<01>HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
<01>HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
<01>HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
<01>HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
<01>FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
<01>FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
<01>FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
<01>HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
<01>HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
<01>HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
<01>HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
<01>HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
<01>HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
<01>HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
<01>HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
<01>HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus,cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
<01>HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
<01>HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
<01>HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
<01>HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
<01>HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
<01>HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
<01>HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
<01>HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
<01>HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
<01>HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
<01>HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
<01>HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
<01>HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
<01>HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
<01>HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
<01>HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
<01>HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
<01>HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
<01>HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
<01>HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
<01>PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
<01>PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
<01>PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
<01>PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
<01>PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
<01>PWR_MODE_EVENT_FALLING
__HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
<01>
__HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
<01>
__HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
<01>
__HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
<01>
__HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
<01>
__HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
<01>
__HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
<01>
__HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
<01>
__HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
<01>
__HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
<01>
__HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
<01>
__HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
<01>__HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
<01>__HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
<01>__HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
<01>__HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
<01>__HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
<01>__HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
<01>__HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
<01>__HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
<01>__HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
<01>__HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
<01>__HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
<01>__HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
<01>__HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
<01>__HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
<01>__HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
<01>__HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
<01>__HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
<01>__HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
<01>__HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
<01>__HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
<01>__HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
<01>__HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
<01>__HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
<01>__HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
<01>__HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
<01>__HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
<01>__HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
<01>__HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
<01>__HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
<01>__HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
<01>__HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
<01>__HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
<01>__HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
<01>__HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
<01>__HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
<01>__HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST))
<01>__HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
<01>__HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
<01>__HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
<01>__HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
<01>
__HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
<01>
__HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
<01>
__HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
<01>
__HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))ti






../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
stm32f1xx_hal_def.h


L../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]C:\Users\XerolySkinner\Desktop\MDK-ARMB<>(&OscillatorTypej
#&HSEStatej
#&HSEPredivValuej
#&LSEStatej
#&HSIStatej
#&HSICalibrationValuej
#&LSIStatej
#&PLL<10>#iRCC_OscInitTypeDef<12>
<01>B<>&PeriphClockSelectionj
#&RTCClock
RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
<01>
RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
<01>
RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
<01>
CR_REG_INDEX ((uint8_t)1)
<01>
BDCR_REG_INDEX ((uint8_t)2)
<01>
CSR_REG_INDEX ((uint8_t)3)
<01>
RCC_FLAG_MASK ((uint8_t)0x1F)
<01>
__HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
<01>
__HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
<01>
__HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
<01>
__HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
<01>
IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || ((__SOURCE__) == RCC_PLLSOURCE_HSE))
<01>
IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
<01>
IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || ((__HSE__) == RCC_HSE_BYPASS))
<01>
IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS))
<01>
IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
<01>
IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
<01>
IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
<01>
IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON))
<01>
IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
<01>
IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
<01>
IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
<01>
IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512))
<01>
IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || ((__PCLK__) == RCC_HCLK_DIV16))
<01>
IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
<01>
IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
<01>
IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))<00><00>






../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h
stm32f1xx_hal_def.h
stm32f1xx_hal_rcc_ex.h


<01>
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]C:\Users\XerolySkinner\Desktop\MDK-ARMB<>
&PLLStatej
#&PLLSourcej
#&PLLMULj
#iRCC_PLLInitTypeDef<12>
;B<>&ClockTypej
#&SYSCLKSourcej
#&AHBCLKDividerj
#&APB1CLKDividerj
#&APB2CLKDividerj
#iRCC_ClkInitTypeDef

P
<00><00><00>

STM32F1xx_HAL_GPIO_EX_H 
6AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0
7AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1
8AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2
9AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3
:AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4
;AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5
<AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6
=AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7
>AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8
?AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9
@AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10
AAFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11
BAFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12
CAFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13
DAFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14
EAFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15
GIS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || ((__PIN__) == AFIO_EVENTOUT_PIN_1) || ((__PIN__) == AFIO_EVENTOUT_PIN_2) || ((__PIN__) == AFIO_EVENTOUT_PIN_3) || ((__PIN__) == AFIO_EVENTOUT_PIN_4) || ((__PIN__) == AFIO_EVENTOUT_PIN_5) || ((__PIN__) == AFIO_EVENTOUT_PIN_6) || ((__PIN__) == AFIO_EVENTOUT_PIN_7) || ((__PIN__) == AFIO_EVENTOUT_PIN_8) || ((__PIN__) == AFIO_EVENTOUT_PIN_9) || ((__PIN__) == AFIO_EVENTOUT_PIN_10) || ((__PIN__) == AFIO_EVENTOUT_PIN_11) || ((__PIN__) == AFIO_EVENTOUT_PIN_12) || ((__PIN__) == AFIO_EVENTOUT_PIN_13) || ((__PIN__) == AFIO_EVENTOUT_PIN_14) || ((__PIN__) == AFIO_EVENTOUT_PIN_15))
_AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA
`AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB
aAFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC
bAFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD
cAFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE
eIS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || ((__PORT__) == AFIO_EVENTOUT_PORT_B) || ((__PORT__) == AFIO_EVENTOUT_PORT_C) || ((__PORT__) == AFIO_EVENTOUT_PORT_D) || ((__PORT__) == AFIO_EVENTOUT_PORT_E))
|__HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP)
<01>
__HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP)
<01>
__HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP)
<01>
__HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP)
<01>
__HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP)
<01>
__HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP)
<01>
__HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP)
<01>
__HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP)
<01>
__HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_
#F<>
__pointer_type_info&base
#F<>
__function_type_info&base<12>#F<>
__array_type_info&base<12>#F<>
__enum_type_info&base<12>#F<>
__fundamental_type_info&base<12>#F<>
__class_type_info&base<12>#F<>
__vmi_class_type_info&baseI#&flags<12>#&base_count<12>#<03><12>
&base_info<12>#F<>
__si_class_type_info&baseI#&base_type
#I0<18>__alignment_proxy0<10>0<10><00>
<01><<10>

<01>4d
this
z__resultd

<00>
<01>B<10>

<01>4d
this
3<10>lenz__resultd

B<>I0<12>&tinfo<12>#&offset_flags<12>#
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