MicrochipFor32/MX_FastSet/T439/MDK-ARM/template/usart.o

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..\Core\Src\usart.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]D:\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM__asm___7_usart_c_aa2567c7____REV16X>







..\Drivers\CMSIS\Include\cmsis_armcc.h
<03>


<01>
..\Core\Src\usart.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]D:\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM__asm___7_usart_c_aa2567c7____REVSHX>







..\Drivers\CMSIS\Include\cmsis_armcc.h
<03>


<01>
..\Core\Src\usart.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]D:\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM__asm___7_usart_c_aa2567c7____RRXX>







..\Drivers\CMSIS\Include\cmsis_armcc.h
<03>
&

`<00><><EFBFBD><EFBFBD>armcc+
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<07><07><07><07><07><07><07><07><08><08><08><08><08><08><08><08>`<00><><EFBFBD><EFBFBD>armcc+
|

	
<07><07><07><07><07><07><07><07><08><08><08><08><08><08><08><08>`<00><><EFBFBD><EFBFBD>armcc+
|

	
<07><07><07><07><07><07><07><07><08><08><08><08><08><08><08><08>`<00><><EFBFBD><EFBFBD>armcc+|

	
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<00><>B`<00><><EFBFBD><EFBFBD>armcc+|

	
<07><07><07><07><07><07><07><07><08><08><08><08><08><08><08><08>^A~<7E><02>
Axl~`<00><><EFBFBD><EFBFBD>armcc+|

	
<07><07><07><07><07><07><07><07><08><08><08><08><08><08><08><08><00>
../Core/Src/usart.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM<00>../Core/Src/usart.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARMphuart1<10>
<00>../Core/Src/usart.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM0?<3F>

MX_USART1_UART_Init
0<
../Core/Src/usart.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM^?<3F>
;HAL_UART_MspInit
^iuartHandle<10>:YGPIO_InitStruct!
<02>`<16>*Ytmpreg<10><02>t<16>(ZYtmpreg<10><02>t<00>../Core/Src/usart.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM?<3F>

YHAL_UART_MspDeInit
iuartHandle<10>4*






../Core/Src/usart.c

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__DATE__ "Apr 24 2023"
__TIME__ "02:34:46"
__STDC__ 1
__STDC_VERSION__ 199901L
__STDC_HOSTED__ 1
__STDC_ISO_10646__ 200607
__EDG__ 1
__EDG_VERSION__ 407
__EDG_SIZE_TYPE__ unsigned int
__EDG_PTRDIFF_TYPE__ int
__sizeof_int 4
__sizeof_long 4
__sizeof_ptr 4
__ARMCC_VERSION 5060960
__TARGET_CPU_CORTEX_M4_FP_SP 1
__TARGET_FPU_VFPV4_SP_D16 1
__UVISION_VERSION 537
_RTE_ 1
STM32F429xx 1
_RTE_ 1
USE_HAL_DRIVER 1
STM32F429xx 1
__CC_ARM 1
__arm 1
__arm__ 1
__TARGET_ARCH_7E_M 1
__TARGET_ARCH_ARM 0
__TARGET_ARCH_THUMB 4
__TARGET_ARCH_A64 0
__TARGET_ARCH_AARCH32 1
__TARGET_PROFILE_M 1
__TARGET_FEATURE_HALFWORD 1
__TARGET_FEATURE_THUMB 1
__TARGET_FEATURE_MULTIPLY 1
__TARGET_FEATURE_DSPMUL 1
__TARGET_FEATURE_DOUBLEWORD 1
__TARGET_FEATURE_DIVIDE 1
__TARGET_FEATURE_UNALIGNED 1
__TARGET_FEATURE_CLZ 1
__TARGET_FEATURE_DMB 1
__TARGET_FPU_VFPV4 1
__TARGET_FPU_VFP 1
__TARGET_FPU_VFP_SINGLE 1
__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 16
__APCS_INTERWORK 1
__FP_FAST_FMAF 1
__thumb 1
__thumb__ 1
__t32__ 1
__OPTIMISE_SPACE 1
__OPT_SMALL_ASSERT 1
__OPTIMISE_LEVEL 3
<00><00>huart1&<00><00>MX_USART1_UART_Init#@
<00>HAL_UART_MspInit%<00><00>HAL_UART_MspDeInit
&

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()*

__stdint_h 
__ARMCLIB_VERSION 5060044
__INT64 __int64
__INT64_C_SUFFIX__ ll
__PASTE2(x,y) x ## y
__PASTE(x,y) __PASTE2(x, y)
__INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))
__UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))
__LONGLONG long long
#__STDINT_DECLS %__CLIBNS
,__CLIBNS 
sINT8_MIN -128
tINT16_MIN -32768
uINT32_MIN (~0x7fffffff)
vINT64_MIN __INT64_C(~0x7fffffffffffffff)
yINT8_MAX 127
zINT16_MAX 32767
{INT32_MAX 2147483647
|INT64_MAX __INT64_C(9223372036854775807)
UINT8_MAX 255
<01>
UINT16_MAX 65535
<01>
UINT32_MAX 4294967295u
<01>
UINT64_MAX __UINT64_C(18446744073709551615)
<01>
INT_LEAST8_MIN -128
<01>
INT_LEAST16_MIN -32768
<01>
INT_LEAST32_MIN (~0x7fffffff)
<01>
INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff)
<01>
INT_LEAST8_MAX 127
<01>
INT_LEAST16_MAX 32767
<01>
INT_LEAST32_MAX 2147483647
<01>
INT_LEAST64_MAX __INT64_C(9223372036854775807)
<01>
UINT_LEAST8_MAX 255
<01>
UINT_LEAST16_MAX 65535
<01>
UINT_LEAST32_MAX 4294967295u
<01>
UINT_LEAST64_MAX __UIN
../Drivers/CMSIS/Include/cmsis_version.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM
012

__CMSIS_ARMCC_H 
,__ARM_ARCH_7EM__ 1
5__ASM __asm
8__INLINE __inline
;__STATIC_INLINE static __inline
>__STATIC_FORCEINLINE static __forceinline
A__NO_RETURN __declspec(noreturn)
D__USED __attribute__((used))
G__WEAK __attribute__((weak))
J__PACKED __attribute__((packed))
M__PACKED_STRUCT __packed struct
P__PACKED_UNION __packed union
S__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
V__UNALIGNED_UINT16_WRITE(addr,val) ((*((__packed uint16_t *)(addr))) = (val))
Y__UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
\__UNALIGNED_UINT32_WRITE(addr,val) ((*((__packed uint32_t *)(addr))) = (val))
___UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
b__ALIGNED(x) __attribute__((aligned(x)))
e__RESTRICT __restrict
<01>__enable_fault_irq __enable_fiq
<01>__disable_fault_irq __disable_fiq
<01>__NOP __nop
<01>__WFI __wfi
<01>__WFE __wfe
<01>__SEV __sev
<01>__ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U)
<01>__DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U)
<01>__DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0U)
<01>__REV __rev
<01>__ROR __ror
<01>__BKPT(value) __breakpoint(value)
<01>__RBIT __rbit
<01>__CLZ __clz
<01>__LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
<01>__LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
<01>__LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
<01>__STREXB(value,ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
<01>__STREXH(value,ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
<01>__STREXW(value,ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
<01>__CLREX __clrex
<01>__SSAT __ssat
<01>__USAT __usat
<01>__LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
<01>__LDRHT(ptr) ((uint16_t) __ldrt(ptr))
<01>__LDRT(ptr) ((uint32_t ) __ldrt(ptr))
<01>__STRBT(value,ptr) __strt(value, ptr)
<01>__STRHT(value,ptr) __strt(value, ptr)
<01>__STRT(value,ptr) __strt(value, ptr)
<01>__SADD8 __sadd8
<01>__QADD8 __qadd8
<01>__SHADD8 __shadd8
<01>__UADD8 __uadd8
<01>__UQADD8 __uqadd8
<01>__UHADD8 __uhadd8
<01>__SSUB8 __ssub8
<01>__QSUB8 __qsub8
<01>__SHSUB8 __shsub8
<01>__USUB8 __usub8
<01>__UQSUB8 __uqsub8
<01>__UHSUB8 __uhsub8
<01>__SADD16 __sadd16
<01>__QADD16 __qadd16
<01>__SHADD16 __shadd16
<01>__UADD16 __uadd16
<01>__UQADD16 __uqadd16
<01>__UHADD16 __uhadd16
<01>__SSUB16 __ssub16
<01>__QSUB16 __qsub16
<01>__SHSUB16 __shsub16
<01>__USUB16 __usub16
<01>__UQSUB16 __uqsub16
<01>__UHSUB16 __uhsub16
<01>__SASX __sasx
<01>__QASX __qasx
<01>__SHASX __shasx
<01>__UASX __uasx
<01>__UQASX __uqasx
<01>__UHASX __uhasx
<01>__SSAX __ssax
<01>__QSAX __qsax
<01>__SHSAX __shsax
<01>__USAX __usax
<01>__UQSAX __uqsax
<01>__UHSAX __uhsax
<01>__USAD8 __usad8
<01>__USADA8 __usada8
<01>__SSAT16 __ssat16
<01>__USAT16 __usat16
<01>__UXTB16 __uxtb16
<01>__UXTAB16 __uxtab16
<01>__SXTB16 __sxtb16
<01>__SXTAB16 __sxtab16
<01>__SMUAD __smuad
<01>__SMUADX __smuadx
<01>__SMLAD __smlad
<01>__SMLADX __smladx
<01>__SMLALD __smlald
<01>__SMLALDX __smlaldx
<01>__SMUSD __smusd
<01>__SMUSDX __smusdx
<01>__SMLSD __smlsd
<01>__SMLSDX __smlsdx
<01>__SMLSLD __smlsld
<01>__SMLSLDX __smlsldx
<01>__SEL __sel
<01>__QADD __qadd
<01>__QSUB __qsub
<01>__PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
<01>__PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
<01>__SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U) ) >> 32U))H>






../Drivers/CMSIS/Include/cmsis_armcc.h


4
../Drivers/CMSIS/Include/cmsis_armcc.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM;<3B>
<01>
__get_CONTROLb
a__resultb

Y__regControlb

P<<3C>
<01>
__set_CONTROL$b
controlY__regControlb

P;<3B>
<01>
__get_IPSRb
a__resultb

Y__regIPSRb

P;<3B>
<01>
__get_APSRb
a__resultb

Y__regAPSRb

P;<3B>
<01>
__get_xPSRb
a__resultb

Y__regXPSRb

P;<3B>
<01>
__get_PSPb
a__resultb

Y__regProcessStackPointerb

P<<3C>
<01>
__set_PSP$b
topOfProcStackY__regProcessStackPointerb

P;<3B>
<01>
__get_MSPb
a__resultb

Y__regMainStackPointerb

P<<3C>
<01>
__set_MSP$b
topOfMainStackY__regMainStackPointerb

P;<3B>
<01>
__get_PRIMASKb
a__resultb

Y__regPriMaskb

P<<3C>
<01>
__set_PRIMASK$b
priMaskY__regPriMaskb

P;<3B>
<01>__get_BASEPRIb
a__resultb

Y__regBasePrib

P<<3C>
<01>__set_BASEPRI$b
basePriY__regBasePrib

P<<3C>
<01>__set_BASEPRI_MAX$b
basePriY__regBasePriMaxb

P;<3B>	
<01>__get_FAULTMASKb
a__resultb

Y__regFaultMaskb

P<<3C>	
<01>__set_FAULTMASK$b
faultMaskY__regFaultMaskb

P;<3B>

<01>__get_FPSCRb
a__resultb

Y__regfpscrb

P<<3C>

<01>__set_FPSCR$b
fpscrY__regfpscrb

P
456

__CMSIS_COMPILER_H "<00><00>






../Drivers/CMSIS/Include/D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\cmsis_compiler.h
stdint.hcmsis_armcc.h


<01>
../Drivers/CMSIS/Include/cmsis_compiler.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM
89:

 ARM_MPU_ARMV7_H 
"ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
#ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
$ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
%ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
&ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
'ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
(ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
)ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
*ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
+ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
,ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
-ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
.ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
/ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
0ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
1ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
2ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
3ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
4ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
5ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
6ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
7ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
8ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
9ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
:ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
;ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
<ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
=ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
?ARM_MPU_AP_NONE 0U
@ARM_MPU_AP_PRIV 1U
AARM_MPU_AP_URO 2U
BARM_MPU_AP_FULL 3U
CARM_MPU_AP_PRO 5U
DARM_MPU_AP_RO 6U
KARM_MPU_RBAR(Region,BaseAddress) (((BaseAddress) & MPU_RBAR_ADDR_Msk) | ((Region) & MPU_RBAR_REGION_Msk) | (MPU_RBAR_VALID_Msk))
XARM_MPU_ACCESS_(TypeExtField,IsShareable,IsCacheable,IsBufferable) ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
gARM_MPU_RASR_EX(DisableExec,AccessPermission,AccessAttributes,SubRegionDisable,Size) ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
xARM_MPU_RASR(DisableExec,AccessPermission,TypeExtField,IsShareable,IsCacheable,IsBufferable,SubRegionDisable,Size) ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
<01>
ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
<01>
ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
<01>
ARM_MPU_ACCESS_NORMAL(OuterCp,InnerCp,IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
<01>
ARM_MPU_CACHEP_NOCACHE 0U
<01>
ARM_MPU_CACHEP_WB_WRA 1U
<01>
ARM_MPU_CACHEP_WT_NWA 2U
<01>
ARM_MPU_CACHEP_WB_NWA 3UH<






../Drivers/CMSIS/Include/mpu_armv7.h


`
../Drivers/CMSIS/Include/mpu_armv7.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM*<2A>
RBARb
#RASRb
#PARM_MPU_Region_t<12>
<01>
<<3C>
<01>
ARM_MPU_Enable$b
MPU_Control<<3C>
<01>
ARM_MPU_Disable<<3C>
<01>
ARM_MPU_ClrRegion$b
rnr<<3C>
<01>
ARM_MPU_SetRegion$b
rbar$b
rasr<<3C>
<01>
ARM_MPU_SetRegionEx$b
rnr$b
rbar$b
rasr<<3C>
<01>
orderedCpy$	dst$src$b
len\ib
tb
"b
"
#<<3C>
<01>ARM_MPU_Load$[table$b
cntsrowWordSize
<12>"W
<=>?

 __CORE_CM4_H_GENERIC "?
B__CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
C__CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
D__CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | __CM4_CMSIS_VERSION_SUB )
G__CORTEX_M (4U)
O__FPU_USED 1U<03>

<01>
__CORE_CM4_H_DEPENDANT 
<01>
__I volatile const
<01>
__O volatile
<01>
__IO volatile
<01>
__IM volatile const
<01>
__OM volatile
<01>
__IOM volatile
<01>APSR_N_Pos 31U
<01>APSR_N_Msk (1UL << APSR_N_Pos)
<01>APSR_Z_Pos 30U
<01>APSR_Z_Msk (1UL << APSR_Z_Pos)
<01>APSR_C_Pos 29U
<01>APSR_C_Msk (1UL << APSR_C_Pos)
<01>APSR_V_Pos 28U
<01>APSR_V_Msk (1UL << APSR_V_Pos)
<01>APSR_Q_Pos 27U
<01>APSR_Q_Msk (1UL << APSR_Q_Pos)
<01>APSR_GE_Pos 16U
<01>APSR_GE_Msk (0xFUL << APSR_GE_Pos)
<01>IPSR_ISR_Pos 0U
<01>IPSR_ISR_Msk (0x1FFUL )
<01>xPSR_N_Pos 31U
<01>xPSR_N_Msk (1UL << xPSR_N_Pos)
<01>xPSR_Z_Pos 30U
<01>xPSR_Z_Msk (1UL << xPSR_Z_Pos)
<01>xPSR_C_Pos 29U
<01>xPSR_C_Msk (1UL << xPSR_C_Pos)
<01>xPSR_V_Pos 28U
<01>xPSR_V_Msk (1UL << xPSR_V_Pos)
<01>xPSR_Q_Pos 27U
<01>xPSR_Q_Msk (1UL << xPSR_Q_Pos)
<01>xPSR_ICI_IT_2_Pos 25U
<01>xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)
<01>xPSR_T_Pos 24U
<01>xPSR_T_Msk (1UL << xPSR_T_Pos)
<01>xPSR_GE_Pos 16U
<01>xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
<01>xPSR_ICI_IT_1_Pos 10U
<01>xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)
<01>xPSR_ISR_Pos 0U
<01>xPSR_ISR_Msk (0x1FFUL )
<01>CONTROL_FPCA_Pos 2U
<01>CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
<01>CONTROL_SPSEL_Pos 1U
<01>CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
<01>CONTROL_nPRIV_Pos 0U
<01>CONTROL_nPRIV_Msk (1UL )
<01>NVIC_STIR_INTID_Pos 0U
<01>NVIC_STIR_INTID_Msk (0x1FFUL )
<01>SCB_CPUID_IMPLEMENTER_Pos 24U
<01>SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
<01>SCB_CPUID_VARIANT_Pos 20U
<01>SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
<01>SCB_CPUID_ARCHITECTURE_Pos 16U
<01>SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
<01>SCB_CPUID_PARTNO_Pos 4U
<01>SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
<01>SCB_CPUID_REVISION_Pos 0U
<01>SCB_CPUID_REVISION_Msk (0xFUL )
<01>SCB_ICSR_NMIPENDSET_Pos 31U
<01>SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
<01>SCB_ICSR_PENDSVSET_Pos 28U
<01>SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
<01>SCB_ICSR_PENDSVCLR_Pos 27U
<01>SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
<01>SCB_ICSR_PENDSTSET_Pos 26U
<01>SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
<01>SCB_ICSR_PENDSTCLR_Pos 25U
<01>SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
<01>SCB_ICSR_ISRPREEMPT_Pos 23U
<01>SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
<01>SCB_ICSR_ISRPENDING_Pos 22U
<01>SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
<01>SCB_ICSR_VECTPENDING_Pos 12U
<01>SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
<01>SCB_ICSR_RETTOBASE_Pos 11U
<01>SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
<01>SCB_ICSR_VECTACTIVE_Pos 0U
<01>SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
<01>SCB_VTOR_TBLOFF_Pos 7U
<01>SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
<01>SCB_AIRCR_VECTKEY_Pos 16U
<01>SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
<01>SCB_AIRCR_VECTKEYSTAT_Pos 16U
<01>SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
<01>SCB_AIRCR_ENDIANESS_Pos 15U
<01>SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
<01>SCB_AIRCR_PRIGROUP_Pos 8U
<01>SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
<01>SCB_AIRCR_SYSRESETREQ_Pos 2U
<01>SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
<01>SCB_AIRCR_VECTCLRACT
MPU_RASR_AP_Pos 24U
<01>
MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
<01>
MPU_RASR_TEX_Pos 19U
<01>
MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
<01>
MPU_RASR_S_Pos 18U
<01>
MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
<01>
MPU_RASR_C_Pos 17U
<01>
MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
<01>
MPU_RASR_B_Pos 16U
<01>
MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
<01>
MPU_RASR_SRD_Pos 8U
<01>
MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
<01>
MPU_RASR_SIZE_Pos 1U
<01>
MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
<01>
MPU_RASR_ENABLE_Pos 0U
<01>
MPU_RASR_ENABLE_Msk (1UL )
<01>
FPU_FPCCR_ASPEN_Pos 31U
<01>
FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
<01>
FPU_FPCCR_LSPEN_Pos 30U
<01>
FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
<01>
FPU_FPCCR_MONRDY_Pos 8U
<01>
FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
<01>
FPU_FPCCR_BFRDY_Pos 6U
<01>
FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
<01>
FPU_FPCCR_MMRDY_Pos 5U
<01>
FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
<01>
FPU_FPCCR_HFRDY_Pos 4U
<01>
FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
<01>
FPU_FPCCR_THREAD_Pos 3U
<01>
FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
<01>
FPU_FPCCR_USER_Pos 1U
<01>
FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
<01>
FPU_FPCCR_LSPACT_Pos 0U
<01>
FPU_FPCCR_LSPACT_Msk (1UL )
<01>
FPU_FPCAR_ADDRESS_Pos 3U
<01>
FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
<01>
FPU_FPDSCR_AHP_Pos 26U
<01>
FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
<01>
FPU_FPDSCR_DN_Pos 25U
<01>
FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
<01>
FPU_FPDSCR_FZ_Pos 24U
<01>
FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
<01>
FPU_FPDSCR_RMode_Pos 22U
<01>
FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
<01>
FPU_MVFR0_FP_rounding_modes_Pos 28U
<01>
FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
<01>
FPU_MVFR0_Short_vectors_Pos 24U
<01>
FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
<01>
FPU_MVFR0_Square_root_Pos 20U
<01>
FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
<01>
FPU_MVFR0_Divide_Pos 16U
<01>
FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
<01>
FPU_MVFR0_FP_excep_trapping_Pos 12U
<01>
FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
<01>
FPU_MVFR0_Double_precision_Pos 8U
<01>
FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
<01>
FPU_MVFR0_Single_precision_Pos 4U
<01>
FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
<01>
FPU_MVFR0_A_SIMD_registers_Pos 0U
<01>
FPU_MVFR0_A_SIMD_registers_Msk (0xFUL )
<01>
FPU_MVFR1_FP_fused_MAC_Pos 28U
<01>
FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
<01>
FPU_MVFR1_FP_HPFP_Pos 24U
<01>
FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
<01>
FPU_MVFR1_D_NaN_mode_Pos 4U
<01>
FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
<01>FPU_MVFR1_FtZ_mode_Pos 0U
<01>FPU_MVFR1_FtZ_mode_Msk (0xFUL )
<01>CoreDebug_DHCSR_DBGKEY_Pos 16U
<01>CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
<01>CoreDebug_DHCSR_S_RESET_ST_Pos 25U
<01>CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
<01>CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
<01>CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
<01>CoreDebug_DHCSR_S_LOCKUP_Pos 19U
<01>CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
<01>CoreDebug_DHCSR_S_SLEEP_Pos 18U
<01>CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
<01>CoreDebug_DHCSR_S_HALT_Pos 17U
<01>CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
<01>CoreDebug_DHCSR_S_REGRDY_Pos 16U
<01>CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
<01>CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
<01>CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
<01>CoreDebug_DHCSR_C_MASKINTS_Pos 3U
<01>CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
<01>CoreDebug_DHCSR_C_STEP_Pos 2U
<01>CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
<01>CoreDebug_DHCSR_C_HALT_Pos 1U
<01>CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
<01>CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
<01>CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL )
<01>CoreDebug_DCRSR_REGWnR_Pos 16U
<01>CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
<01>CoreDebug_DCRSR_REGSEL_Pos 0U
<01>CoreDebug_DCRSR_REGSEL_Msk (0x1FUL )
<01>CoreDebug_DEMCR_TRCENA_Pos 24U
<01>CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
<01>CoreDebug_DEMCR_MON_REQ_Pos 19U
<01>CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
<01>CoreDebug_DEMCR_MON_STEP_Pos 18U
<01>CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
<01>CoreDebug_DEMCR_MON_PEND_Pos 17U
<01>CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
<01>CoreDebug_DEMCR_MON_EN_Pos 16U
<01>CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
<01>CoreDebug_DEMCR_VC_HARDERR_Pos 10U
<01>CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
<01>CoreDebug_DEMCR_VC_INTERR_Pos 9U
<01>CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
<01>CoreDebug_DEMCR_VC_BUSERR_Pos 8U
<01>CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
<01>CoreDebug_DEMCR_VC_STATERR_Pos 7U
<01>CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
<01>CoreDebug_DEMCR_VC_CHKERR_Pos 6U
<01>CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
<01>CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
<01>CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
<01>CoreDebug_DEMCR_VC_MMERR_Pos 4U
<01>CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
<01>CoreDebug_DEMCR_VC_CORERESET_Pos 0U
<01>CoreDebug_DEMCR_VC_CORERESET_Msk (1UL )
<01>_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
<01>_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
<01>SCS_BASE (0xE000E000UL)
<01>ITM_BASE (0xE0000000UL)
<01>DWT_BASE (0xE0001000UL)
<01>TPI_BASE (0xE0040000UL)
<01>CoreDebug_BASE (0xE000EDF0UL)
<01>SysTick_BASE (SCS_BASE + 0x0010UL)
<01>NVIC_BASE (SCS_BASE + 0x0100UL)
<01>SCB_BASE (SCS_BASE + 0x0D00UL)
<01>SCnSCB ((SCnSCB_Type *) SCS_BASE )
<01>SCB ((SCB_Type *) SCB_BASE )
<01>SysTick ((SysTick_Type *) SysTick_BASE )
<01>NVIC ((NVIC_Type *) NVIC_BASE )
<01>ITM ((ITM_Type *) ITM_BASE )
<01>DWT ((DWT_Type *) DWT_BASE )
<01>TPI ((TPI_Type *) TPI_BASE )
<01>CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
<01>MPU_BASE (SCS_BASE + 0x0D90UL)
<01>MPU ((MPU_Type *) MPU_BASE )
<01>FPU_BASE (SCS_BASE + 0x0F30UL)
<01>FPU ((FPU_Type *) FPU_BASE )
<01>NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
<01>NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
<01>NVIC_EnableIRQ __NVIC_EnableIRQ
<01>NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
<01>NVIC_DisableIRQ __NVIC_DisableIRQ
<01>NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
<01>NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
<01>NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

../Drivers/CMSIS/Include/core_cm4.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM*<2A>!_reserved0b
#!GEb
#!_reserved1b
#!Qb
#
!Vb
#
!Cb
#
!Zb
#

!Nb
#
S<>b<12>wb
PAPSR_TypeD

<01>*<2A>!ISRb
#	!_reserved0b
#S<>bi
wb
PIPSR_Type<12>

<01>*<2A>!ISRb
#	!_reserved0b
#
!ICI_IT_1b
#!GEb
#!_reserved1b
#!Tb
#
!ICI_IT_2b
#!Qb
#
!Vb
#
!Cb
#
!Zb
#

!Nb
#
S<>b<12>
wb
PxPSR_Type<12>
<01>*<2A>!nPRIVb
#
!SPSELb
#
!FPCAb
#
!_reserved0b
#S<>b<12>wb
PCONTROL_Type
<01>*<2A><08><03>j
ISER-#<03>b

RESERVED0B# <03>j
ICER^#<23>
<03>b

RSERVED1t#<23>
<03>j
ISPR<12>#<23><03>b

RESERVED2<12>#<23><03>j
ICPR<12>#<23><03>b

RESERVED3<12>#<23><03>j
IABR<12>#<23><03>b

7RESERVED4#<23><03>p
<01>
IP)#<23><03>b

<01>RESERVED5>#<23>STIRj#<23>tb
tC
PNVIC_Type(
<01>*<2A><0B>
CPUID<12>#ICSRj#VTORj#AIRCRj#SCRj#CCRj#<03>	p
SHP<12>#SHCSRj#$CFSRj#(HFSRj#,DFSRj#0MMFARj#4BFARj#8AFSRj#<<03>
<12>

PFR?#@DFR<12>#HADR<12>#L<03>
<12>
MMFRi#P<03><12>
ISAR~#`<03>b

RESERVED0<12>#tCPACRj#<23>
b
t<12>PSCB_Type<12>
<01>*<2A><03>b

RESERVED0<12>#ICTR<12>#ACTLRj#PSCnSCB_Type<12>
<01>*<2A>CTRLj#LOADj#VALj#CALIB<12>#PSysTick_Type'
<01>S<>
u8pu16<12>u32jtR
*<2A><10> <03>
Z
PORT<12>#<03>
b

<01>RESERVED0<12>#<23>
TERj#<23><03>
b

RESERVED1<12>#<23>TPRj#<23><03>b

RESERVED2#<23>TCRj#<23><03>b

RESERVED3)#<23>IWRj#<23>IRR<12>#<23>IMCRj#<23><03>b

*RESERVED4k#<23>LARj#<23>LSR<12>#<23><03>b

RESERVED5<12>#<23>PID4<12>#<23>PID5<12>#<23>PID6<12>#<23>PID7<12>#<23>PID0<12>#<23>PID1<12>#<23>PID2<12>#<23>PID3<12>#<23>CID0<12>#<23>CID1<12>#<23>CID2<12>#<23>CID3<12>#<23>tqPITM_Type<12>
<01>*<2A>\CTRLj#CYCCNTj#CPICNTj#EXCCNTj#SLEEPCNTj#LSUCNTj#FOLDCNTj#PCSR<12>#COMP0j# MASK0j#$FUNCTION0j#(<03>b

RESERVED0
	#,COMP1j#0MASK1j#4FUNCTION1j#8<03>b

RESERVED1T	#<COMP2j#@MASK2j#DFUNCTION2j#H<03>b

RESERVED2<12>	#LCOMP3j#PMASK3j#TFUNCTION3j#XPDWT_Typeo
<01>*<2A><17>SSPSR<12>#CSPSRj#<03>b


RESERVED0
#ACPRj#<03>b

6RESERVED1;
#SPPRj#<23>
<03>b

<01>
RESERVED2d
#<23>
FFSR<12>#<23>FFCRj#<23>FSCR<12>#<23><03>b

<01>RESERVED3<12>
#<23>TRIGGER<12>#<23>FIFO0<12>#<23>ITATBCTR2<12>#<23><03>b

RESERVED4<12>
#<23>ITATBCTR0<12>#<23>FIFO1<12>#<23>ITCTRLj#<23><03>b

&RESERVED5C#<23>CLAIMSETj#<23>CLAIMCLRj#<23><03>b

RESERVED7<12>#<23>DEVID<12>#<23>DEVTYPE<12>#<23>PTPI_Type<12>	
<01>*<2A>,TYPE<12>#CTRLj#RNRj#RBARj#RASRj#RBAR_A1j#RASR_A1j#RBAR_A2j#RASR_A2j# RBAR_A3j#$RASR_A3j#(PMPU_Type<12>
<01>	*<2A><03>b

RESERVED0~#FPCCRj#FPCARj#FPDSCRj#MVFR0<12>#MVFR1<12>#PFPU_Typez
<01>
*<2A>DHCSRj#DCRSRj#DCRDRj#DEMCRj#PCoreDebug_Type<12>
<01>t%
qITM_RxBuffer>


<<3C>
<01>__NVIC_SetPriorityGrouping$b
PriorityGroup\reg_valueb
\PriorityGroupTmpb
;<3B>
<01>
__NVIC_GetPriorityGroupingb
a__resultb

<<3C>
<01>
__NVIC_EnableIRQ$IRQn;<3B>
<01>
__NVIC_GetEnableIRQb
$IRQna__resultb

<<3C>
<01>
__NVIC_DisableIRQ$IRQn;<3B>
<01>
__NVIC_GetPendingIRQb
$IRQna__resultb

<<3C>
<01>
__NVIC_SetPendingIRQ$IRQn<<3C>
<01>
__NVIC_ClearPendingIRQ$IRQn;<3B>
<01>__NVIC_GetActiveb
$IRQna__resultb

<<3C>
<01>__NVIC_SetPriority$IRQn$b
priority;<3B>
<01>__NVIC_GetPriorityb
$IRQna__resultb

;<3B> 
<01>NVIC_EncodePriorityb
$b
PriorityGroup$b
PreemptPriority$b
SubPrioritya__resultb

\PriorityGroupTmpb
\PreemptPriorityBitsb
\SubPriorityBitsb
<<3C>"
<01>NVIC_DecodePriority$b
Priority$b
PriorityGroup$pPreemptPriority$pSubPriority\PriorityGroupTmpb
\PreemptPriorityBitsb
\SubPriorityBitsb
"b
<<3C>"
<01>__NVIC_SetVector$IRQn$b
vector\vectors;<3B>#
<01>__NVIC_GetVectorb
$IRQna__resultb

\vectors<<3C>#
<01>"__NVIC_SystemReset;<3B>#
<01>SCB_GetFPUTypeb
a__resultb

\mvfr0b
;<3B>$
<01>SysTick_Configb
$b
ticksa__resultb

;<3B>$
<01>ITM_SendCharb
$b
cha__resultb

;<3B>%
<01>ITM_ReceiveChar%
a__result%

\ch%
;<3B>%
<01>ITM_CheckChar%
a__result%

<00>D
ITM_RxBuffer
ABCD

__SYSTEM_STM32F4XX_H `W






../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h


0

../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARMqSystemCoreClockb


C
<03>
<12>
qAHBPrescTable<12>

<03><12>
qAPBPrescTable


F4
<00>SystemCoreClock<00>AHBPrescTable
APBPrescTable
FGH

"__STM32F429xx_H 
/__CM4_REV 0x0001U
0__MPU_PRESENT 1U
1__NVIC_PRIO_BITS 4U
2__Vendor_SysTickConfig 0U
3__FPU_PRESENT 1U<03>
<03>
<03>

<01>FLASH_BASE 0x08000000UL
<01>CCMDATARAM_BASE 0x10000000UL
<01>SRAM1_BASE 0x20000000UL
<01>SRAM2_BASE 0x2001C000UL
<01>SRAM3_BASE 0x20020000UL
<01>PERIPH_BASE 0x40000000UL
<01>BKPSRAM_BASE 0x40024000UL
<01>FMC_R_BASE 0xA0000000UL
<01>SRAM1_BB_BASE 0x22000000UL
<01>SRAM2_BB_BASE 0x22380000UL
<01>SRAM3_BB_BASE 0x22400000UL
<01>PERIPH_BB_BASE 0x42000000UL
<01>BKPSRAM_BB_BASE 0x42480000UL
<01>FLASH_END 0x081FFFFFUL
<01>FLASH_OTP_BASE 0x1FFF7800UL
<01>FLASH_OTP_END 0x1FFF7A0FUL
<01>CCMDATARAM_END 0x1000FFFFUL
<01>SRAM_BASE SRAM1_BASE
<01>SRAM_BB_BASE SRAM1_BB_BASE
<01>APB1PERIPH_BASE PERIPH_BASE
<01>APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
<01>AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
<01>AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
<01>TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
<01>TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
<01>TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
<01>TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
<01>TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
<01>TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
<01>TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
<01>TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
<01>TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
<01>RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
<01>WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
<01>IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
<01>I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
<01>SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
<01>SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
<01>I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
<01>USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
<01>USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
<01>UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
<01>UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
<01>I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
<01>I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
<01>I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
<01>CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
<01>CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
<01>PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
<01>DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
<01>UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
<01>UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
<01>TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
<01>TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
<01>USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
<01>USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
<01>ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
<01>ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
<01>ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
<01>ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
<01>ADC_BASE ADC123_COMMON_BASE
<01>SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
<01>SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
<01>SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
<01>SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
<01>EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
<01>TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
<01>TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
<01>TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
<01>SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
<01>SPI6_BASE (APB2PERIPH_BASE + 0x5400UL)
<01>SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
<01>SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
<01>SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
<01>LTDC_BASE (APB2PERIPH_BASE + 0x6800UL)
<01>LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
<01>LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
<01>GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
<01>GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
<01>GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
<01>GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
<01>GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
<01>GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
<01>GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
<01>GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
<01>GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
<01>GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL)
<01>GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL)
<01>CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
<01>RCC_BASE (AHB1PERIPH_BASE + 0x38
ETH ((ETH_TypeDef *) ETH_BASE)
<01>
DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
<01>
DCMI ((DCMI_TypeDef *) DCMI_BASE)
<01>
RNG ((RNG_TypeDef *) RNG_BASE)
<01>
FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
<01>
FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
<01>
FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
<01>
FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
<01>
FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
<01>
DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
<01>
USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
<01>
USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
<01>
LSI_STARTUP_TIME 40U
<01>
ADC_MULTIMODE_SUPPORT 
<01>
ADC_SR_AWD_Pos (0U)
<01>
ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
<01>
ADC_SR_AWD ADC_SR_AWD_Msk
<01>
ADC_SR_EOC_Pos (1U)
<01>
ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
<01>
ADC_SR_EOC ADC_SR_EOC_Msk
<01>
ADC_SR_JEOC_Pos (2U)
<01>
ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
<01>
ADC_SR_JEOC ADC_SR_JEOC_Msk
<01>
ADC_SR_JSTRT_Pos (3U)
<01>
ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
<01>
ADC_SR_JSTRT ADC_SR_JSTRT_Msk
<01>
ADC_SR_STRT_Pos (4U)
<01>
ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
<01>
ADC_SR_STRT ADC_SR_STRT_Msk
<01>
ADC_SR_OVR_Pos (5U)
<01>
ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
<01>
ADC_SR_OVR ADC_SR_OVR_Msk
<01>
ADC_CR1_AWDCH_Pos (0U)
<01>
ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
<01>
ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
<01>
ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
<01>
ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
<01>
ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
<01>
ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
<01>
ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
<01>
ADC_CR1_EOCIE_Pos (5U)
<01>
ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
<01>
ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
<01>
ADC_CR1_AWDIE_Pos (6U)
<01>
ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
<01>
ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
<01>
ADC_CR1_JEOCIE_Pos (7U)
<01>
ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
<01>
ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
<01>
ADC_CR1_SCAN_Pos (8U)
<01>
ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
<01>
ADC_CR1_SCAN ADC_CR1_SCAN_Msk
<01>
ADC_CR1_AWDSGL_Pos (9U)
<01>
ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
<01>
ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
<01>
ADC_CR1_JAUTO_Pos (10U)
<01>
ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
<01>
ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
<01>
ADC_CR1_DISCEN_Pos (11U)
<01>
ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
<01>
ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
<01>
ADC_CR1_JDISCEN_Pos (12U)
<01>
ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
<01>
ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
<01>
ADC_CR1_DISCNUM_Pos (13U)
<01>
ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
<01>
ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
<01>
ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
<01>
ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
<01>
ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
<01>
ADC_CR1_JAWDEN_Pos (22U)
<01>
ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
<01>
ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
<01>
ADC_CR1_AWDEN_Pos (23U)
<01>
ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
<01>
ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
<01>
ADC_CR1_RES_Pos (24U)
<01>
ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
<01>
ADC_CR1_RES ADC_CR1_RES_Msk
<01>
ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
<01>
ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
<01>
ADC_CR1_OVRIE_Pos (26U)
<01>
ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
<01>
ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
<01>
ADC_CR2_ADON_Pos (0U)
<01>
ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
<01>
ADC_CR2_ADON ADC_CR2_ADON_Msk
<01>
ADC_CR2_CONT_Pos (1U)
<01>
ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
<01>
ADC_CR2_CONT ADC_CR2_CONT_Msk
<01>ADC_CR2_DMA_Pos (8U)
<01>ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
<01>ADC_CR2_DMA ADC_CR2_DMA_Msk
<01>ADC_CR2_DDS_Pos (9U)
<01>ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
<01>ADC_CR2_DDS ADC_CR2_DDS_Msk
<01>ADC_CR2_EOCS_Pos (10U)
<01>ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
<01>ADC_CR2_EOCS ADC_CR2_EOCS_Msk
<01>ADC_CR2_ALIGN_Pos (11U)
<01>ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
<01>ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
<01>ADC_CR2_JEXTSEL_Pos (16U)
<01>ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
<01>ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
<01>ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
<01>ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
<01>ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
<01>ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
<01>ADC_CR2_JEXTEN_Pos (20U)
<01>ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
<01>ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
<01>ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
<01>ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
<01>ADC_CR2_JSWSTART_Pos (22U)
<01>ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
<01>ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
<01>ADC_CR2_EXTSEL_Pos (24U)
<01>ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
<01>ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
<01>ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
<01>ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
<01>ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
<01>ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
<01>ADC_CR2_EXTEN_Pos (28U)
<01>ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
<01>ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
<01>ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
<01>ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
<01>ADC_CR2_SWSTART_Pos (30U)
<01>ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
<01>ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
<01>ADC_SMPR1_SMP10_Pos (0U)
<01>ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
<01>ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
<01>ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
<01>ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
<01>ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
<01>ADC_SMPR1_SMP11_Pos (3U)
<01>ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
<01>ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
<01>ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
<01>ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
<01>ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
<01>ADC_SMPR1_SMP12_Pos (6U)
<01>ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
<01>ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
<01>ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
<01>ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
<01>ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
<01>ADC_SMPR1_SMP13_Pos (9U)
<01>ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
<01>ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
<01>ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
<01>ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
<01>ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
<01>ADC_SMPR1_SMP14_Pos (12U)
<01>ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
<01>ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
<01>ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
<01>ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
<01>ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
<01>ADC_SMPR1_SMP15_Pos (15U)
<01>ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
<01>ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
<01>ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
<01>ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
<01>ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
<01>ADC_SMPR1_SMP16_Pos (18U)
<01>ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
<01>ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
<01>ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
<01>ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
<01>ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
<01>ADC_SMPR1_SMP17_Pos (21U)
<01>ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
<01>ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
<01>ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
<01>ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
<01>ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
<01>ADC_SMPR1_SMP18_Pos (24U)
<01>ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
<01>ADC_SMPR1_SMP18 A
../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM<13>
NonMaskableInt_IRQnrMemoryManagement_IRQntBusFault_IRQnuUsageFault_IRQnvSVCall_IRQn{DebugMonitor_IRQn|PendSV_IRQn~SysTick_IRQnWWDG_IRQnPVD_IRQn
TAMP_STAMP_IRQnRTC_WKUP_IRQnFLASH_IRQnRCC_IRQnEXTI0_IRQnEXTI1_IRQnEXTI2_IRQnEXTI3_IRQn	EXTI4_IRQn
DMA1_Stream0_IRQnDMA1_Stream1_IRQnDMA1_Stream2_IRQn
DMA1_Stream3_IRQnDMA1_Stream4_IRQnDMA1_Stream5_IRQnDMA1_Stream6_IRQnADC_IRQnCAN1_TX_IRQnCAN1_RX0_IRQnCAN1_RX1_IRQnCAN1_SCE_IRQnEXTI9_5_IRQnTIM1_BRK_TIM9_IRQnTIM1_UP_TIM10_IRQnTIM1_TRG_COM_TIM11_IRQnTIM1_CC_IRQnTIM2_IRQnTIM3_IRQnTIM4_IRQnI2C1_EV_IRQnI2C1_ER_IRQn I2C2_EV_IRQn!I2C2_ER_IRQn"SPI1_IRQn#SPI2_IRQn$USART1_IRQn%USART2_IRQn&USART3_IRQn'EXTI15_10_IRQn(RTC_Alarm_IRQn)OTG_FS_WKUP_IRQn*TIM8_BRK_TIM12_IRQn+TIM8_UP_TIM13_IRQn,TIM8_TRG_COM_TIM14_IRQn-TIM8_CC_IRQn.DMA1_Stream7_IRQn/FMC_IRQn0SDIO_IRQn1TIM5_IRQn2SPI3_IRQn3UART4_IRQn4UART5_IRQn5TIM6_DAC_IRQn6TIM7_IRQn7DMA2_Stream0_IRQn8DMA2_Stream1_IRQn9DMA2_Stream2_IRQn:DMA2_Stream3_IRQn;DMA2_Stream4_IRQn<ETH_IRQn=ETH_WKUP_IRQn>CAN2_TX_IRQn?CAN2_RX0_IRQn<00>CAN2_RX1_IRQn<00>CAN2_SCE_IRQn<00>OTG_FS_IRQn<00>DMA2_Stream5_IRQn<00>DMA2_Stream6_IRQn<00>DMA2_Stream7_IRQn<00>USART6_IRQn<00>I2C3_EV_IRQn<00>I2C3_ER_IRQn<00>OTG_HS_EP1_OUT_IRQn<00>OTG_HS_EP1_IN_IRQn<00>OTG_HS_WKUP_IRQn<00>OTG_HS_IRQn<00>DCMI_IRQn<00>HASH_RNG_IRQn<00>FPU_IRQn<00>UART7_IRQn<00>UART8_IRQn<00>SPI4_IRQn<00>SPI5_IRQn<00>SPI6_IRQn<00>SAI1_IRQn<00>LTDC_IRQn<00>LTDC_ER_IRQn<00>DMA2D_IRQn<00>PIRQn_Type<12>
<01>
*<2A>PSR
#CR1
#CR2
#SMPR1
#SMPR2
#JOFR1
#JOFR2
#JOFR3
#JOFR4
# HTR
#$LTR
#(SQR1
#,SQR2
#0SQR3
#4JSQR
#8JDR1
#<JDR2
#@JDR3
#DJDR4
#HDR
#Ltb
PADC_TypeDef
<01>
*<2A>CSR
#CCR
#CDR
#PADC_Common_TypeDef'
<01>
*<2A>TIR
#TDTR
#TDLR
#TDHR
#PCAN_TxMailBox_TypeDefh
<01>
*<2A>RIR
#RDTR
#RDLR
#RDHR
#PCAN_FIFOMailBox_TypeDef<12>
<01>
*<2A>FR1
#FR2
#PCAN_FilterRegister_TypeDef	
<01>
*<2A><15>MCR
#MSR
#TSR
#RF0R
#RF1R
#IER
#ESR
#BTR
#<03>b

WRESERVED0<12>	# <03><12>
sTxMailBox<12>	#<23><03><12>

sFIFOMailBox<12>	#<23><03>b

RESERVED1

#<23>FMR
#<23>FM1R
#<23>RESERVED2b
#<23>FS1R
#<23>RESERVED3b
#<23>FFA1R
#<23>RESERVED4b
#<23>FA1R
#<23><03>b

RESERVED5<12>
#<23><03>)	
sFilterRegister<12>
#<23>PCAN_TypeDefL	
<01>*<2A>DR
#IDR8#RESERVED0C
#RESERVED1R
#CR
#tC
PCRC_TypeDef<12>

<01>*<2A>8CR
#SWTRIGR
#DHR12R1
#DHR12L1
#DHR8R1
#DHR12R2
#DHR12L2
#DHR8R2
#DHR12RD
# DHR12LD
#$DHR8RD
#(DOR1
#,DOR2
#0SR
#4PDAC_TypeDefR
<01>*<2A>IDCODE
#CR
#APB1FZ
#APB2FZ
#PDBGMCU_TypeDef*
<01>*<2A>,CR
#SR
#RISR
#IER
#MISR
#ICR
#ESCR
#ESUR
#CWSTRTR
# CWSIZER
#$DR
#(PDCMI_TypeDefz
<01>*<2A>CR
#NDTR
#PAR
#M0AR
#M1AR
#FCR
#PDMA_Stream_TypeDef

<01>*<2A>LISR
#HISR
#LIFCR
#HIFCR
#PDMA_TypeDefz

<01>*<2A><1E>CR
#ISR
#IFCR
#FGMAR
#FGOR
#BGMAR
#BGOR
#FGPFCCR
#FGCOLR
# BGPFCCR
#$BGCOLR
#(FGCMAR
#,BGCMAR
#0OPFCCR
#4OCOLR
#8OMAR
#<OOR
#@NLR
#DLWR
#HAMTCR
#L<03>b

<01>
RESERVED<12>#P<03>

<01>
FGCLUT<12>#<23><03>

<01>
BGCLUT<12>#<23>PDMA2D_TypeDef<12>

<01>*<2A>'<27> MACCR
#MACFFR
#MACHTHR
#MACHTLR
#MACMIIAR
#MACMIIDR
#MACFCR
#MACVLANTR
#<03>b


RESERVED0<12># MACRWUFFR
#(MACPMTCSR
#,RESERVED1b
#0MACDBGR
#4MACSR
#8MACIMR
#<MACA0HR
#@MACA0LR
#DMACA1HR
#HMACA1LR
#LMACA2HR
#PMACA2LR
#TMACA3HR
#XMACA3LR
#\<03>!b

'RESERVED2<12>#`MMCCR
#<23>MMCRIR
#<23>MMCTIR
#<23>MMCRIMR
#<23>MMCTIMR
#<23><03>"b


RESERVED3#<23>MMCTGFSCCR
#<23>MMCTGFMSCCR
#<23><03>"b

RESERVED4I#<23>MMCTGFCR
#<23><03>#b

	RESERVED5w#<23>MMCRFCECR
#<23>MMCRFAECR
#<23><03>#b

	RESERVED6<12>#<23>MMCRGUFCR
#<23><03>#b

<01>RESERVED7<12>#<23>PTPTSCR
#<23>PTPSSIR
#<23>PTPTSHR
#<23>PTPTSLR
#<23>PTPTSHUR
#<23>PTPTSLUR
#<23>PTPTSAR
#<23>PTPTTHR
#<23>PTPTTLR
#<23>RESERVED8
#<23>PTPTSSR
#<23><03>%b

<01>RESERVED9<12>#<23>DMABMR
#<23> DMATPDR
#<23> DMARPDR
#<23> DMARDLAR
#<23> DMATDLAR
#<23> DMASR
#<23> DMAOMR
#<23> DMAIER
#<23> DMAMFBOCR
#<23> DMARSWTR
#<23> <03>'b

RESERVED10w#<23> DMACHTDR
#<23> DMACHRDR
#<23> DMACHTBAR
#<23> DMACHRBAR
#<23> PETH_TypeDef-
<01>*<2A>(IMR
#EMR
#RTSR
#FTSR
#SWIER
#PR
#PEXTI_TypeDef<12>
<01>*<2A>)ACR
#KEYR
#OPTKEYR
#SR
#CR
#OPTCR
#OPTCR1
#PFLASH_TypeDefO
<01>*<2A>) <03>)

BTCR<12>#PFMC_Bank1_TypeDef<12>
<01>*<2A>*<03>*

BWTR<12>#PFMC_Bank1E_TypeDef<12>
<01>*<2A>+8PCR2
#SR2
#PMEM2
#PATT2
#RESERVED0b
#ECCR2
#RESERVED1b
#RESERVED2b
#PCR3
# SR3
#$PMEM3
#(PATT3
#,RESERVED3b
#0ECCR3
#4PFMC_Bank2_3_TypeDef(
<01>*<2A>,PCR4
#SR4
#PMEM4
#PATT4
#PIO4
#PFMC_Bank4_TypeDef
<01>*<2A>-<03>,


SDCRq#<03>-


SDTR<12>#SDCMR
#SDRTR
#SDSR
#PFMC_Bank5_6_TypeDefm
<01>*<2A>.(MODER
#OTYPER
#OSPEEDR
#PUPDR
#IDR
#ODR
#BSRR
#LCKR
#<03>.


AFRG# PGPIO_TypeDef<12>
<01>*<2A>/$MEMRMP
#PMC
#<03>/

EXTICR<12>#<03>/b


RESERVED<12>#CMPCR
# PSYSCFG_TypeDefq
<01>*<2A>0(CR1
#CR2
#OAR1
#OAR2
#DR
#SR1
#SR2
#CCR
#TRISE
# FLTR
#$PI2C_TypeDef<12>
<01>*<2A>1KR
#PR
#RLR
#SR
#PIWDG_TypeDefp
<01>*<2A>3L<03>1b


RESERVED0<12>#SSCR
#BPCR
#AWCR
#TWCR
#GCR
#<03>2b


RESERVED1#SRCR
#$<03>2b

RESERVED26#(BCCR
#,<03>2b

RESERVED3^#0IER
#4ISR
#8ICR
#<LIPCR
#@CPSR
#DCDSR
#HPLTDC_TypeDef<12>
<01>*<2A>5DCR
#WHPCR
#WVPCR
#CKCR
#PFCR
#CACR
#DCCR
#BFCR
#<03>4b


RESERVED0:# CFBAR
#(CFBLR
#,CFBLNR
#0<03>5b

RESERVED1~#4CLUTWR
#@PLTDC_Layer_TypeDef<12>
<01>*<2A>5CR
#CSR
#PPWR_TypeDef<12>
<01>*<2A>:<3A>
CR
#PLLCFGR
#CFGR
#CIR
#AHB1RSTR
#AHB2RSTR
#AHB3R
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM<13>
HAL_TICK_FREQ_10HZdHAL_TICK_FREQ_100HZ
HAL_TICK_FREQ_1KHZ
HAL_TICK_FREQ_DEFAULT
PHAL_TickFreqTypeDef<12>
7tb
quwTickH


quwTickPriob


quwTickFreq-


7<00>
N
uwTick[
uwTickPrion
uwTickFreq
OPQ

&__STM32F4xx_H 
4STM32F4 
n__STM32F4xx_CMSIS_VERSION_MAIN (0x02U)
o__STM32F4xx_CMSIS_VERSION_SUB1 (0x06U)
p__STM32F4xx_CMSIS_VERSION_SUB2 (0x08U)
q__STM32F4xx_CMSIS_VERSION_RC (0x00U)
r__STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24) |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16) |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 ) |(__STM32F4xx_CMSIS_VERSION_RC))<03>

<01>
IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
<01>
SET_BIT(REG,BIT) ((REG) |= (BIT))
<01>
CLEAR_BIT(REG,BIT) ((REG) &= ~(BIT))
<01>
READ_BIT(REG,BIT) ((REG) & (BIT))
<01>
CLEAR_REG(REG) ((REG) = (0x0))
<01>
WRITE_REG(REG,VAL) ((REG) = (VAL))
<01>
READ_REG(REG) ((REG))
<01>
MODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
<01>
POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
<01>
ATOMIC_SET_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_CLEAR_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_MODIFY_REG(REG,CLEARMSK,SETMASK) do { uint32_t val; do { val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)
<01>ATOMIC_SETH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)
<01>ATOMIC_CLEARH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)
<01>ATOMIC_MODIFYH_REG(REG,CLEARMSK,SETMASK) do { uint16_t val; do { val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)<03><00><00>






../Drivers/CMSIS/Device/ST/STM32F4xx/Include/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx.h
stm32f429xx.h
stm32f4xx_hal.h

h

../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM<13>

RESETSET
PFlagStatus<12>
<01>
PITStatus<12>
<01>
<13>
DISABLEENABLE
PFunctionalState


<01>
<13>
SUCCESSERROR
PErrorStatus<

<01>

STU

STM32_HAL_LEGACY 
#AES_FLAG_RDERR CRYP_FLAG_RDERR
$AES_FLAG_WRERR CRYP_FLAG_WRERR
%AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
&AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
'AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
9ADC_RESOLUTION12b ADC_RESOLUTION_12B
:ADC_RESOLUTION10b ADC_RESOLUTION_10B
;ADC_RESOLUTION8b ADC_RESOLUTION_8B
<ADC_RESOLUTION6b ADC_RESOLUTION_6B
=OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
>OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
?EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
@EOC_SEQ_CONV ADC_EOC_SEQ_CONV
AEOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
BREGULAR_GROUP ADC_REGULAR_GROUP
CINJECTED_GROUP ADC_INJECTED_GROUP
DREGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
EAWD_EVENT ADC_AWD_EVENT
FAWD1_EVENT ADC_AWD1_EVENT
GAWD2_EVENT ADC_AWD2_EVENT
HAWD3_EVENT ADC_AWD3_EVENT
IOVR_EVENT ADC_OVR_EVENT
JJQOVF_EVENT ADC_JQOVF_EVENT
KALL_CHANNELS ADC_ALL_CHANNELS
LREGULAR_CHANNELS ADC_REGULAR_CHANNELS
MINJECTED_CHANNELS ADC_INJECTED_CHANNELS
NSYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
OSYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
PADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
QADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
RADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
SADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
TADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
UADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
VADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
WADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
XADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
YADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
ZADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
[ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
\ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
]ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
^ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
_ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
`ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
bHAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
cHAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
dHAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
eHAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
fHAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
gHAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
hHAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
|__HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
<01>
COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
<01>
COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
<01>
COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
<01>
COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
<01>
COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
<01>
COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
<01>
COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
<01>
COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
<01>
COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
<01>
COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
<01>
__HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
<01>
HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
<01>
HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
<01>
CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
<01>
CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
<01>DAC1_CHANNEL_1 DAC_CHANNEL_1
<01>DAC1_CHANNEL_2 DAC_CHANNEL_2
<01>DAC2_CHANNEL_1 DAC_CHANNEL_1
<01>DAC_WAVE_NONE 0x00000000U
<01>DAC_WAVE_NOISE DAC_CR_WAVE1_0
<01>DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
<01>DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
<01>DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
<01>DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
<01>HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
<01>HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
<01>HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
<01>HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
<01>HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
<01>HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
<01>HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
<01>HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
<01>HAL_REMAPDMA_
TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
<01>
TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
<01>
UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
<01>
UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
<01>
UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
<01>
UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
<01>
__HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
<01>
__HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
<01>
__DIV_SAMPLING16 UART_DIV_SAMPLING16
<01>
__DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
<01>
__DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
<01>
__UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
<01>
__DIV_SAMPLING8 UART_DIV_SAMPLING8
<01>
__DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
<01>
__DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
<01>
__UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
<01>
__DIV_LPUART UART_DIV_LPUART
<01>
UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
<01>
UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
<01>
USART_CLOCK_DISABLED USART_CLOCK_DISABLE
<01>
USART_CLOCK_ENABLED USART_CLOCK_ENABLE
<01>
USARTNACK_ENABLED USART_NACK_ENABLE
<01>
USARTNACK_DISABLED USART_NACK_DISABLE
<01>
CFR_BASE WWDG_CFR_BASE
<01>
CAN_FilterFIFO0 CAN_FILTER_FIFO0
<01>
CAN_FilterFIFO1 CAN_FILTER_FIFO1
<01>
CAN_IT_RQCP0 CAN_IT_TME
<01>
CAN_IT_RQCP1 CAN_IT_TME
<01>
CAN_IT_RQCP2 CAN_IT_TME
<01>
INAK_TIMEOUT CAN_TIMEOUT_VALUE
<01>
SLAK_TIMEOUT CAN_TIMEOUT_VALUE
<01>
CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
<01>
CAN_TXSTATUS_OK ((uint8_t)0x01U)
<01>
CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
<01>
VLAN_TAG ETH_VLAN_TAG
<01>
MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
<01>
MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
<01>
JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
<01>
MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
<01>
MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
<01>
MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
<01>
DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
<01>
ETH_MMCCR 0x00000100U
<01>
ETH_MMCRIR 0x00000104U
<01>
ETH_MMCTIR 0x00000108U
<01>
ETH_MMCRIMR 0x0000010CU
<01>
ETH_MMCTIMR 0x00000110U
<01>
ETH_MMCTGFSCCR 0x0000014CU
<01>
ETH_MMCTGFMSCCR 0x00000150U
<01>
ETH_MMCTGFCR 0x00000168U
<01>
ETH_MMCRFCECR 0x00000194U
<01>
ETH_MMCRFAECR 0x00000198U
<01>
ETH_MMCRGUFCR 0x000001C4U
<01>
ETH_MAC_TXFIFO_FULL 0x02000000U
<01>
ETH_MAC_TXFIFONOT_EMPTY 0x01000000U
<01>
ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U
<01>
ETH_MAC_TXFIFO_IDLE 0x00000000U
<01>
ETH_MAC_TXFIFO_READ 0x00100000U
<01>
ETH_MAC_TXFIFO_WAITING 0x00200000U
<01>
ETH_MAC_TXFIFO_WRITING 0x00300000U
<01>
ETH_MAC_TRANSMISSION_PAUSE 0x00080000U
<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U
<01>ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U
<01>ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U
<01>ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U
<01>ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U
<01>ETH_MAC_RXFIFO_EMPTY 0x00000000U
<01>ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U
<01>ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U
<01>ETH_MAC_RXFIFO_FULL 0x00000300U
<01>ETH_MAC_READCONTROLLER_IDLE 0x00000000U
<01>ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U
<01>ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U
<01>ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U
<01>ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U
<01>ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U
<01>ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U
<01>ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U
<01>ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U
<01>ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U
<01>HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
<01>DCMI_IT_OVF DCMI_IT_OVR
<01>DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
<01>DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
<01>HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
<01>HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
<01>HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
<01>DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
<01>DMA2D_RGB888 DMA2D_OUTPUT_RGB888
<01>DMA2D_RGB565 DMA2D_OUTPUT_RGB565
<01>DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
<01>DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
<01>CM_ARGB8888 DMA2D_INPUT_ARGB8888
<01>CM_RGB888 DMA2D_INPUT_RGB888
<01>CM_RGB565 DMA2D_INPUT_RGB565
<01>CM_ARGB1555 DMA2D_INPUT_ARGB1555
<01>CM_ARGB4444 DMA2D_INPUT_ARGB4444
<01>CM_L8 DMA2D_INPUT_L8
<01>CM_AL44 DMA2D_INPUT_AL44
<01>CM_AL88 DMA2D_INPUT_AL88
<01>CM_L4 DMA2D_INPUT_L4
<01>CM_A8 DMA2D_INPUT_A8
<01>CM_A4 DMA2D_INPUT_A4
<01>HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort
<01>HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
<01>HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler
<01>HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
<01>HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
<01>HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
<01>HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
<01>HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
<01>HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
<01>HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
<01>HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
<01>HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
<01>HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
<01>HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
<01>HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
<01>HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
<01>HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
<01>HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
<01>HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
<01>HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
<01>HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
<01>HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
<01>HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
<01>HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
<01>HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
<01>HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
<01>HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
<01>HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
<01>HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
<01>HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
<01>HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
<01>HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
<01>HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
<01>HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
<01>HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
<01>HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
<01>HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
<01>HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
<01>HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
<01>HAL_DBG_LowPowerConfig(Periph,cmd) (((cmd )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
<01>HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
<01>HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_En
../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM
WXY

__stddef_h 
__ARMCLIB_VERSION 5060044
__STDDEF_DECLS __CLIBNS
 __CLIBNS SNULL
TNULL 0
[offsetof(t,memb) ((__CLIBNS size_t)__INTADDR__(&(((t *)0)->memb)))XM






D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.h



D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]intunsigned intunsigned shortlong doublePptrdiff_t<12>
&Psize_t<12>
.Pwchar_t<12>
@Pmax_align_t<12>
_
[\]

__STM32F4xx_HAL_DEF 
9UNUSED(X) (void)X
;HAL_MAX_DELAY 0xFFFFFFFFU
=HAL_IS_BIT_SET(REG,BIT) (((REG) & (BIT)) == (BIT))
>HAL_IS_BIT_CLR(REG,BIT) (((REG) & (BIT)) == 0U)
@__HAL_LINKDMA(__HANDLE__,__PPP_DMA_FIELD__,__DMA_HANDLE__) do{ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); (__DMA_HANDLE__).Parent = (__HANDLE__); } while(0U)
U__HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
[__HAL_LOCK(__HANDLE__) do{ if((__HANDLE__)->Lock == HAL_LOCKED) { return HAL_BUSY; } else { (__HANDLE__)->Lock = HAL_LOCKED; } }while (0U)
g__HAL_UNLOCK(__HANDLE__) do{ (__HANDLE__)->Lock = HAL_UNLOCKED; }while (0U)
<01>
__ALIGN_END 
<01>
__ALIGN_BEGIN __align(4)
<01>
__RAM_FUNC 
<01>
__NOINLINE __attribute__ ( (noinline) )<00><00>






../Drivers/STM32F4xx_HAL_Driver/Inc/../Drivers/CMSIS/Device/ST/STM32F4xx/Include/D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\stm32f4xx_hal_def.h
stm32f4xx.hLegacy/stm32_hal_legacy.h
stddef.h

X

../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM<13>
HAL_OKHAL_ERROR
HAL_BUSYHAL_TIMEOUTPHAL_StatusTypeDef<12>
,<13>
HAL_UNLOCKEDHAL_LOCKED
PHAL_LockTypeDef 

5
_`a

__STM32F4xx_HAL_RCC_EX_H 
<01>RCC_PERIPHCLK_I2S 0x00000001U
<01>RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
<01>RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
<01>RCC_PERIPHCLK_LTDC 0x00000008U
<01>RCC_PERIPHCLK_TIM 0x00000010U
<01>RCC_PERIPHCLK_RTC 0x00000020U
<01>RCC_PERIPHCLK_PLLI2S 0x00000040U
<01>RCC_I2SCLKSOURCE_PLLI2S 0x00000000U
<01>RCC_I2SCLKSOURCE_EXT 0x00000001U
<01>RCC_PLLSAIDIVR_2 0x00000000U
<01>RCC_PLLSAIDIVR_4 0x00010000U
<01>RCC_PLLSAIDIVR_8 0x00020000U
<01>RCC_PLLSAIDIVR_16 0x00030000U
<01>RCC_SAIACLKSOURCE_PLLSAI 0x00000000U
<01>RCC_SAIACLKSOURCE_PLLI2S 0x00100000U
<01>RCC_SAIACLKSOURCE_EXT 0x00200000U
<01>RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U
<01>RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U
<01>RCC_SAIBCLKSOURCE_EXT 0x00800000U
<01>RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
<01>RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
<01>RCC_MCO2SOURCE_SYSCLK 0x00000000U
<01>RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
<01>RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
<01>RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
<01>__HAL_RCC_BKPSRAM_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_CRC_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_GPIOD_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_GPIOE_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_GPIOI_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_GPIOF_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_GPIOG_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_GPIOJ_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_GPIOK_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_DMA2D_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_ETHMAC_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_ETHMACTX_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_ETHMACRX_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN); tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_ETHMACPTP_CLK_ENABLE() do
__HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
<01>
__HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
<01>
__HAL_RCC_TIM6_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_TIM7_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_TIM12_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_TIM13_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_TIM14_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_TIM14_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_USART3_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_UART4_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_UART5_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_CAN1_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_CAN2_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_DAC_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_UART7_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_UART8_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_TIM2_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_TIM3_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_TIM4_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_SPI3_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_I2C3_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
<01>__HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
<01>__HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
<01>__HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
<01>__HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
<01>__HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
<01>__HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
<01>__HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
<01>__HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
<01>__HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
<01>__HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
<01>__HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
<01>__HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
<01>__HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
<01>__HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
<01>__HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
<01>__HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
<01>__HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
<01>__HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
<01>__HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
<01>__HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
<01>__HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
<01>__HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
<01>__HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
<01>__HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
<01>__HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
<01>__HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
<01>__HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
<01>__HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
<01>__HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
<01>__HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
<01>__HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
<01>__HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
<01>__HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
<01>__HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
<01>__HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
<01>__HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
<01>__HAL_RCC_TIM3_IS_CLK_DISAB
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM*<2A>PLLStateb
#PLLSourceb
#PLLMb
#PLLNb
#PLLPb
#PLLQb
#PRCC_PLLInitTypeDef<12>
I*<2A>PLLI2SNb
#PLLI2SRb
#PLLI2SQb
#PRCC_PLLI2SInitTypeDefO

<01>*<2A>PLLSAINb
#PLLSAIQb
#PLLSAIRb
#PRCC_PLLSAIInitTypeDef<12>

<01>*<2A>0PeriphClockSelectionb
#PLLI2S<12>
#PLLSAI<12>
#PLLI2SDivQb
#PLLSAIDivQb
# PLLSAIDivRb
#$RTCClockSelectionb
#(TIMPresSelectionC
#,PRCC_PeriphCLKInitTypeDef<12>

<01>
cde

__STM32F4xx_HAL_RCC_H 
jRCC_OSCILLATORTYPE_NONE 0x00000000U
kRCC_OSCILLATORTYPE_HSE 0x00000001U
lRCC_OSCILLATORTYPE_HSI 0x00000002U
mRCC_OSCILLATORTYPE_LSE 0x00000004U
nRCC_OSCILLATORTYPE_LSI 0x00000008U
vRCC_HSE_OFF 0x00000000U
wRCC_HSE_ON RCC_CR_HSEON
xRCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
<01>
RCC_LSE_OFF 0x00000000U
<01>
RCC_LSE_ON RCC_BDCR_LSEON
<01>
RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
<01>
RCC_HSI_OFF ((uint8_t)0x00)
<01>
RCC_HSI_ON ((uint8_t)0x01)
<01>
RCC_HSICALIBRATION_DEFAULT 0x10U
<01>
RCC_LSI_OFF ((uint8_t)0x00)
<01>
RCC_LSI_ON ((uint8_t)0x01)
<01>
RCC_PLL_NONE ((uint8_t)0x00)
<01>
RCC_PLL_OFF ((uint8_t)0x01)
<01>
RCC_PLL_ON ((uint8_t)0x02)
<01>
RCC_PLLP_DIV2 0x00000002U
<01>
RCC_PLLP_DIV4 0x00000004U
<01>
RCC_PLLP_DIV6 0x00000006U
<01>
RCC_PLLP_DIV8 0x00000008U
<01>
RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
<01>
RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
<01>
RCC_CLOCKTYPE_SYSCLK 0x00000001U
<01>
RCC_CLOCKTYPE_HCLK 0x00000002U
<01>
RCC_CLOCKTYPE_PCLK1 0x00000004U
<01>
RCC_CLOCKTYPE_PCLK2 0x00000008U
<01>
RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
<01>
RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
<01>
RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
<01>
RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
<01>
RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
<01>
RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
<01>
RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
<01>
RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1))
<01>
RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
<01>
RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
<01>
RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
<01>
RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
<01>
RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
<01>
RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
<01>
RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
<01>
RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
<01>
RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
<01>
RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
<01>
RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
<01>
RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
<01>
RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
<01>
RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
<01>
RCC_RTCCLKSOURCE_NO_CLK 0x00000000U
<01>
RCC_RTCCLKSOURCE_LSE 0x00000100U
<01>
RCC_RTCCLKSOURCE_LSI 0x00000200U
<01>RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U
<01>RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
<01>RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
<01>RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
<01>RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
<01>RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
<01>RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
<01>RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
<01>RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
<01>RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
<01>RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
<01>RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
<01>RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
<01>RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
<01>RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
<01>RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
<01>RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
<01>RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
<01>RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
<01>RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
<01>RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
<01>RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
<01>RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
<01>RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
<01>RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
<01>RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
<01>RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
<01>RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
<01>RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
<01>RCC_RTCCLKSOURCE_HSE_DIV30 0x0
RCC_OFFSET (RCC_BASE - PERIPH_BASE)
<01>
RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
<01>
RCC_HSION_BIT_NUMBER 0x00U
<01>
RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
<01>
RCC_CSSON_BIT_NUMBER 0x13U
<01>
RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
<01>
RCC_PLLON_BIT_NUMBER 0x18U
<01>
RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
<01>
RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
<01>
RCC_RTCEN_BIT_NUMBER 0x0FU
<01>
RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
<01>
RCC_BDRST_BIT_NUMBER 0x10U
<01>
RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
<01>
RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
<01>
RCC_LSION_BIT_NUMBER 0x00U
<01>
RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
<01>
RCC_CR_BYTE2_ADDRESS 0x40023802U
<01>
RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
<01>
RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
<01>
RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
<01>
RCC_DBP_TIMEOUT_VALUE 2U
<01>
RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
<01>
HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
<01>
HSI_TIMEOUT_VALUE 2U
<01>
LSI_TIMEOUT_VALUE 2U
<01>
CLOCKSWITCH_TIMEOUT_VALUE 5000U
<01>
IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
<01>
IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || ((HSE) == RCC_HSE_BYPASS))
<01>
IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || ((LSE) == RCC_LSE_BYPASS))
<01>
IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
<01>
IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
<01>
IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
<01>
IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || ((SOURCE) == RCC_PLLSOURCE_HSE))
<01>
IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
<01>
IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
<01>IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
<01>IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
<01>IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
<01>IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || ((HCLK) == RCC_SYSCLK_DIV512))
<01>IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
<01>IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || ((PCLK) == RCC_HCLK_DIV16))
<01>IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
<01>IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
<01>IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_5))
<01>IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)<00><00>






../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h
stm32f4xx_hal_def.h
stm32f4xx_hal_rcc_ex.h



../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM*<2A>0OscillatorTypeb
#HSEStateb
#LSEStateb
#HSIStateb
#HSICalibrationValueb
#LSIStateb
#PLL5
#PRCC_OscInitTypeDef<12>
F*<2A>ClockTypeb
#SYSCLKSourceb
#AHBCLKDividerb
#APB1CLKDividerb
#APB2CLKDividerb
#PRCC_ClkInitTypeDefy

\
ghi

__STM32F4xx_HAL_GPIO_EX_H 
5GPIO_AF0_RTC_50Hz ((uint8_t)0x00)
6GPIO_AF0_MCO ((uint8_t)0x00)
7GPIO_AF0_TAMPER ((uint8_t)0x00)
8GPIO_AF0_SWJ ((uint8_t)0x00)
9GPIO_AF0_TRACE ((uint8_t)0x00)
>GPIO_AF1_TIM1 ((uint8_t)0x01)
?GPIO_AF1_TIM2 ((uint8_t)0x01)
DGPIO_AF2_TIM3 ((uint8_t)0x02)
EGPIO_AF2_TIM4 ((uint8_t)0x02)
FGPIO_AF2_TIM5 ((uint8_t)0x02)
KGPIO_AF3_TIM8 ((uint8_t)0x03)
LGPIO_AF3_TIM9 ((uint8_t)0x03)
MGPIO_AF3_TIM10 ((uint8_t)0x03)
NGPIO_AF3_TIM11 ((uint8_t)0x03)
SGPIO_AF4_I2C1 ((uint8_t)0x04)
TGPIO_AF4_I2C2 ((uint8_t)0x04)
UGPIO_AF4_I2C3 ((uint8_t)0x04)
ZGPIO_AF5_SPI1 ((uint8_t)0x05)
[GPIO_AF5_SPI2 ((uint8_t)0x05)
\GPIO_AF5_SPI3 ((uint8_t)0x05)
]GPIO_AF5_SPI4 ((uint8_t)0x05)
^GPIO_AF5_SPI5 ((uint8_t)0x05)
_GPIO_AF5_SPI6 ((uint8_t)0x05)
`GPIO_AF5_I2S3ext ((uint8_t)0x05)
eGPIO_AF6_SPI3 ((uint8_t)0x06)
fGPIO_AF6_I2S2ext ((uint8_t)0x06)
gGPIO_AF6_SAI1 ((uint8_t)0x06)
lGPIO_AF7_USART1 ((uint8_t)0x07)
mGPIO_AF7_USART2 ((uint8_t)0x07)
nGPIO_AF7_USART3 ((uint8_t)0x07)
oGPIO_AF7_I2S3ext ((uint8_t)0x07)
tGPIO_AF8_UART4 ((uint8_t)0x08)
uGPIO_AF8_UART5 ((uint8_t)0x08)
vGPIO_AF8_USART6 ((uint8_t)0x08)
wGPIO_AF8_UART7 ((uint8_t)0x08)
xGPIO_AF8_UART8 ((uint8_t)0x08)
}GPIO_AF9_CAN1 ((uint8_t)0x09)
~GPIO_AF9_CAN2 ((uint8_t)0x09)
GPIO_AF9_TIM12 ((uint8_t)0x09)
<01>
GPIO_AF9_TIM13 ((uint8_t)0x09)
<01>
GPIO_AF9_TIM14 ((uint8_t)0x09)
<01>
GPIO_AF9_LTDC ((uint8_t)0x09)
<01>
GPIO_AF10_OTG_FS ((uint8_t)0x0A)
<01>
GPIO_AF10_OTG_HS ((uint8_t)0x0A)
<01>
GPIO_AF11_ETH ((uint8_t)0x0B)
<01>
GPIO_AF12_FMC ((uint8_t)0x0C)
<01>
GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C)
<01>
GPIO_AF12_SDIO ((uint8_t)0x0C)
<01>
GPIO_AF13_DCMI ((uint8_t)0x0D)
<01>
GPIO_AF14_LTDC ((uint8_t)0x0E)
<01>
GPIO_AF15_EVENTOUT ((uint8_t)0x0F)
<01>	GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U : ((__GPIOx__) == (GPIOB))? 1U : ((__GPIOx__) == (GPIOC))? 2U : ((__GPIOx__) == (GPIOD))? 3U : ((__GPIOx__) == (GPIOE))? 4U : ((__GPIOx__) == (GPIOF))? 5U : ((__GPIOx__) == (GPIOG))? 6U : ((__GPIOx__) == (GPIOH))? 7U : ((__GPIOx__) == (GPIOI))? 8U : ((__GPIOx__) == (GPIOJ))? 9U : 10U)
<01>
IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || ((AF) == GPIO_AF14_LTDC))tj






../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h
stm32f4xx_hal_def.h


<01>
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM
klm

__STM32F4xx_HAL_GPIO_H 
UGPIO_PIN_0 ((uint16_t)0x0001)
VGPIO_PIN_1 ((uint16_t)0x0002)
WGPIO_PIN_2 ((uint16_t)0x0004)
XGPIO_PIN_3 ((uint16_t)0x0008)
YGPIO_PIN_4 ((uint16_t)0x0010)
ZGPIO_PIN_5 ((uint16_t)0x0020)
[GPIO_PIN_6 ((uint16_t)0x0040)
\GPIO_PIN_7 ((uint16_t)0x0080)
]GPIO_PIN_8 ((uint16_t)0x0100)
^GPIO_PIN_9 ((uint16_t)0x0200)
_GPIO_PIN_10 ((uint16_t)0x0400)
`GPIO_PIN_11 ((uint16_t)0x0800)
aGPIO_PIN_12 ((uint16_t)0x1000)
bGPIO_PIN_13 ((uint16_t)0x2000)
cGPIO_PIN_14 ((uint16_t)0x4000)
dGPIO_PIN_15 ((uint16_t)0x8000)
eGPIO_PIN_All ((uint16_t)0xFFFF)
gGPIO_PIN_MASK 0x0000FFFFU
uGPIO_MODE_INPUT MODE_INPUT
vGPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP)
wGPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD)
xGPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP)
yGPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD)
{GPIO_MODE_ANALOG MODE_ANALOG
}GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING)
~GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)
GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)
<01>
GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)
<01>
GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)
<01>
GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)
<01>
GPIO_SPEED_FREQ_LOW 0x00000000U
<01>
GPIO_SPEED_FREQ_MEDIUM 0x00000001U
<01>
GPIO_SPEED_FREQ_HIGH 0x00000002U
<01>
GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U
<01>
GPIO_NOPULL 0x00000000U
<01>
GPIO_PULLUP 0x00000001U
<01>
GPIO_PULLDOWN 0x00000002U
<01>
__HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
<01>
__HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
<01>
__HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
<01>
__HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
<01>
__HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))<03>

<01>
GPIO_MODE_Pos 0U
<01>
GPIO_MODE (0x3UL << GPIO_MODE_Pos)
<01>MODE_INPUT (0x0UL << GPIO_MODE_Pos)
<01>MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)
<01>MODE_AF (0x2UL << GPIO_MODE_Pos)
<01>MODE_ANALOG (0x3UL << GPIO_MODE_Pos)
<01>OUTPUT_TYPE_Pos 4U
<01>OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)
<01>OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)
<01>OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)
<01>EXTI_MODE_Pos 16U
<01>EXTI_MODE (0x3UL << EXTI_MODE_Pos)
<01>EXTI_IT (0x1UL << EXTI_MODE_Pos)
<01>EXTI_EVT (0x2UL << EXTI_MODE_Pos)
<01>TRIGGER_MODE_Pos 20U
<01>TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)
<01>TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)
<01>TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)
<01>IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
<01>IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))
<01>IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) || ((MODE) == GPIO_MODE_OUTPUT_PP) || ((MODE) == GPIO_MODE_OUTPUT_OD) || ((MODE) == GPIO_MODE_AF_PP) || ((MODE) == GPIO_MODE_AF_OD) || ((MODE) == GPIO_MODE_IT_RISING) || ((MODE) == GPIO_MODE_IT_FALLING) || ((MODE) == GPIO_MODE_IT_RISING_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING) || ((MODE) == GPIO_MODE_EVT_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING_FALLING) || ((MODE) == GPIO_MODE_ANALOG))
<01>IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
<01>IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || ((PULL) == GPIO_PULLDOWN))<00><00>






../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h
stm32f4xx_hal_def.h
stm32f4xx_hal_gpio_ex.h


t

../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM*<2A>Pinb
#Modeb
#Pullb
#Speedb
#Alternateb
#PGPIO_InitTypeDef<12>
><13>
GPIO_PIN_RESETGPIO_PIN_SET
PGPIO_PinState9

G
opq

STM32f4xx_HAL_EXTI_H 
VEXTI_LINE_0 (EXTI_GPIO | 0x00u)
WEXTI_LINE_1 (EXTI_GPIO | 0x01u)
XEXTI_LINE_2 (EXTI_GPIO | 0x02u)
YEXTI_LINE_3 (EXTI_GPIO | 0x03u)
ZEXTI_LINE_4 (EXTI_GPIO | 0x04u)
[EXTI_LINE_5 (EXTI_GPIO | 0x05u)
\EXTI_LINE_6 (EXTI_GPIO | 0x06u)
]EXTI_LINE_7 (EXTI_GPIO | 0x07u)
^EXTI_LINE_8 (EXTI_GPIO | 0x08u)
_EXTI_LINE_9 (EXTI_GPIO | 0x09u)
`EXTI_LINE_10 (EXTI_GPIO | 0x0Au)
aEXTI_LINE_11 (EXTI_GPIO | 0x0Bu)
bEXTI_LINE_12 (EXTI_GPIO | 0x0Cu)
cEXTI_LINE_13 (EXTI_GPIO | 0x0Du)
dEXTI_LINE_14 (EXTI_GPIO | 0x0Eu)
eEXTI_LINE_15 (EXTI_GPIO | 0x0Fu)
fEXTI_LINE_16 (EXTI_CONFIG | 0x10u)
gEXTI_LINE_17 (EXTI_CONFIG | 0x11u)
iEXTI_LINE_18 (EXTI_CONFIG | 0x12u)
nEXTI_LINE_19 (EXTI_CONFIG | 0x13u)
sEXTI_LINE_20 (EXTI_CONFIG | 0x14u)
wEXTI_LINE_21 (EXTI_CONFIG | 0x15u)
xEXTI_LINE_22 (EXTI_CONFIG | 0x16u)
<01>
EXTI_MODE_NONE 0x00000000u
<01>
EXTI_MODE_INTERRUPT 0x00000001u
<01>
EXTI_MODE_EVENT 0x00000002u
<01>
EXTI_TRIGGER_NONE 0x00000000u
<01>
EXTI_TRIGGER_RISING 0x00000001u
<01>
EXTI_TRIGGER_FALLING 0x00000002u
<01>
EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
<01>
EXTI_GPIOA 0x00000000u
<01>
EXTI_GPIOB 0x00000001u
<01>
EXTI_GPIOC 0x00000002u
<01>
EXTI_GPIOD 0x00000003u
<01>
EXTI_GPIOE 0x00000004u
<01>
EXTI_GPIOF 0x00000005u
<01>
EXTI_GPIOG 0x00000006u
<01>
EXTI_GPIOH 0x00000007u
<01>
EXTI_GPIOI 0x00000008u
<01>
EXTI_GPIOJ 0x00000009u
<01>
EXTI_GPIOK 0x0000000Au
<01>
EXTI_PROPERTY_SHIFT 24u
<01>
EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
<01>
EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
<01>
EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
<01>
EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
<01>
EXTI_PIN_MASK 0x0000001Fu
<01>
EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
<01>
EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
<01>
EXTI_LINE_NB 23UL
<01>
IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
<01>
IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
<01>
IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
<01>
IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
<01>IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
<01>IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) || ((__PORT__) == EXTI_GPIOD) || ((__PORT__) == EXTI_GPIOE) || ((__PORT__) == EXTI_GPIOF) || ((__PORT__) == EXTI_GPIOG) || ((__PORT__) == EXTI_GPIOH) || ((__PORT__) == EXTI_GPIOI) || ((__PORT__) == EXTI_GPIOJ) || ((__PORT__) == EXTI_GPIOK))
<01>IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)pg






../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h
stm32f4xx_hal_def.h


<01>

../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM<13>

HAL_EXTI_COMMON_CB_IDPEXTI_CallbackIDTypeDef<12>
/*<2A>Lineb
#O<>"
PendingCallback#
#PEXTI_HandleTypeDef


8*<2A>Lineb
#Modeb
#Triggerb
#GPIOSelb
#PEXTI_ConfigTypeDefY

H
stu

__STM32F4xx_HAL_DMA_EX_H ti






../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h
stm32f4xx_hal_def.h




../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM<13>

MEMORY0MEMORY1
PHAL_DMA_MemoryTypeDef<12>
3
wxy

__STM32F4xx_HAL_DMA_H 
<01>
HAL_DMA_ERROR_NONE 0x00000000U
<01>
HAL_DMA_ERROR_TE 0x00000001U
<01>
HAL_DMA_ERROR_FE 0x00000002U
<01>
HAL_DMA_ERROR_DME 0x00000004U
<01>
HAL_DMA_ERROR_TIMEOUT 0x00000020U
<01>
HAL_DMA_ERROR_PARAM 0x00000040U
<01>
HAL_DMA_ERROR_NO_XFER 0x00000080U
<01>
HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U
<01>
DMA_CHANNEL_0 0x00000000U
<01>
DMA_CHANNEL_1 0x02000000U
<01>
DMA_CHANNEL_2 0x04000000U
<01>
DMA_CHANNEL_3 0x06000000U
<01>
DMA_CHANNEL_4 0x08000000U
<01>
DMA_CHANNEL_5 0x0A000000U
<01>
DMA_CHANNEL_6 0x0C000000U
<01>
DMA_CHANNEL_7 0x0E000000U
<01>
DMA_PERIPH_TO_MEMORY 0x00000000U
<01>
DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)
<01>
DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)
<01>
DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)
<01>
DMA_PINC_DISABLE 0x00000000U
<01>
DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)
<01>
DMA_MINC_DISABLE 0x00000000U
<01>DMA_PDATAALIGN_BYTE 0x00000000U
<01>DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)
<01>DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)
<01>DMA_MDATAALIGN_BYTE 0x00000000U
<01>DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)
<01>DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)
<01>DMA_NORMAL 0x00000000U
<01>DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)
<01>DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)
<01>DMA_PRIORITY_LOW 0x00000000U
<01>DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)
<01>DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)
<01>DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)
<01>DMA_FIFOMODE_DISABLE 0x00000000U
<01>DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)
<01>DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U
<01>DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)
<01>DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)
<01>DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)
<01>DMA_MBURST_SINGLE 0x00000000U
<01>DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
<01>DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
<01>DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
<01>DMA_PBURST_SINGLE 0x00000000U
<01>DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
<01>DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
<01>DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
<01>DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
<01>DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
<01>DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
<01>DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
<01>DMA_IT_FE 0x00000080U
<01>DMA_FLAG_FEIF0_4 0x00000001U
<01>DMA_FLAG_DMEIF0_4 0x00000004U
<01>DMA_FLAG_TEIF0_4 0x00000008U
<01>DMA_FLAG_HTIF0_4 0x00000010U
<01>DMA_FLAG_TCIF0_4 0x00000020U
<01>DMA_FLAG_FEIF1_5 0x00000040U
<01>DMA_FLAG_DMEIF1_5 0x00000100U
<01>DMA_FLAG_TEIF1_5 0x00000200U
<01>DMA_FLAG_HTIF1_5 0x00000400U
<01>DMA_FLAG_TCIF1_5 0x00000800U
<01>DMA_FLAG_FEIF2_6 0x00010000U
<01>DMA_FLAG_DMEIF2_6 0x00040000U
<01>DMA_FLAG_TEIF2_6 0x00080000U
<01>DMA_FLAG_HTIF2_6 0x00100000U
<01>DMA_FLAG_TCIF2_6 0x00200000U
<01>DMA_FLAG_FEIF3_7 0x00400000U
<01>DMA_FLAG_DMEIF3_7 0x01000000U
<01>DMA_FLAG_TEIF3_7 0x02000000U
<01>DMA_FLAG_HTIF3_7 0x04000000U
<01>DMA_FLAG_TCIF3_7 0x08000000U
<01>__HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
<01>__HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
<01>__HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
<01>__HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
<01>__HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 : ((uint32_t)((__HANDLE__)->Instance
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARMuvoid"<12>"tb
PDMA_InitTypeDefw

`PHAL_DMA_StateTypeDefj
nPHAL_DMA_LevelCompleteTypeDef<12>
wPHAL_DMA_CallbackIDTypeDef1
<01>
PDMA_HandleTypeDef
<01>
*<2A>0Channelb
#Directionb
#PeriphIncb
#MemIncb
#PeriphDataAlignmentb
#MemDataAlignmentb
#Modeb
#Priorityb
#FIFOModeb
# FIFOThresholdb
#$MemBurstb
#(PeriphBurstb
#,<13>
HAL_DMA_STATE_RESETHAL_DMA_STATE_READY
HAL_DMA_STATE_BUSYHAL_DMA_STATE_TIMEOUTHAL_DMA_STATE_ERRORHAL_DMA_STATE_ABORT<13>
HAL_DMA_FULL_TRANSFERHAL_DMA_HALF_TRANSFER
<13>
HAL_DMA_XFER_CPLT_CB_IDHAL_DMA_XFER_HALFCPLT_CB_ID
HAL_DMA_XFER_M1CPLT_CB_IDHAL_DMA_XFER_M1HALFCPLT_CB_IDHAL_DMA_XFER_ERROR_CB_IDHAL_DMA_XFER_ABORT_CB_IDHAL_DMA_XFER_ALL_CB_ID)<29>__DMA_HandleTypeDef`Instance<12>#Init<12>#LockC
#4State<12>#5Parent<12>#8O<38>%<12>"]XferCpltCallbacke#<O<>	%<12>"<12>XferHalfCpltCallback<12>#@O<>	%<12>"<12>XferM1CpltCallback<12>#DO<44>	%<12>"<12>XferM1HalfCpltCallback<12>#HO<48>
%<12>"<12>XferErrorCallback
#LO<4C>
%<12>"XferAbortCallback&#PErrorCode<12>#TStreamBaseAddressb
#XStreamIndexb
#\"_
t<12>
{|}

__STM32F4xx_HAL_CORTEX_H 
XNVIC_PRIORITYGROUP_0 0x00000007U
ZNVIC_PRIORITYGROUP_1 0x00000006U
\NVIC_PRIORITYGROUP_2 0x00000005U
^NVIC_PRIORITYGROUP_3 0x00000004U
`NVIC_PRIORITYGROUP_4 0x00000003U
iSYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
jSYSTICK_CLKSOURCE_HCLK 0x00000004U
tMPU_HFNMI_PRIVDEF_NONE 0x00000000U
uMPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
vMPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
wMPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
<01>
MPU_REGION_ENABLE ((uint8_t)0x01)
<01>
MPU_REGION_DISABLE ((uint8_t)0x00)
<01>
MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
<01>
MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
<01>
MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
<01>
MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
<01>
MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
<01>
MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
<01>
MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
<01>
MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
<01>
MPU_TEX_LEVEL0 ((uint8_t)0x00)
<01>
MPU_TEX_LEVEL1 ((uint8_t)0x01)
<01>
MPU_TEX_LEVEL2 ((uint8_t)0x02)
<01>
MPU_REGION_SIZE_32B ((uint8_t)0x04)
<01>
MPU_REGION_SIZE_64B ((uint8_t)0x05)
<01>
MPU_REGION_SIZE_128B ((uint8_t)0x06)
<01>
MPU_REGION_SIZE_256B ((uint8_t)0x07)
<01>
MPU_REGION_SIZE_512B ((uint8_t)0x08)
<01>
MPU_REGION_SIZE_1KB ((uint8_t)0x09)
<01>
MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
<01>
MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
<01>
MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
<01>
MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
<01>
MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
<01>
MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
<01>
MPU_REGION_SIZE_128KB ((uint8_t)0x10)
<01>
MPU_REGION_SIZE_256KB ((uint8_t)0x11)
<01>
MPU_REGION_SIZE_512KB ((uint8_t)0x12)
<01>
MPU_REGION_SIZE_1MB ((uint8_t)0x13)
<01>
MPU_REGION_SIZE_2MB ((uint8_t)0x14)
<01>
MPU_REGION_SIZE_4MB ((uint8_t)0x15)
<01>
MPU_REGION_SIZE_8MB ((uint8_t)0x16)
<01>
MPU_REGION_SIZE_16MB ((uint8_t)0x17)
<01>
MPU_REGION_SIZE_32MB ((uint8_t)0x18)
<01>
MPU_REGION_SIZE_64MB ((uint8_t)0x19)
<01>
MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
<01>
MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
<01>
MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
<01>
MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
<01>
MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
<01>
MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
<01>
MPU_REGION_NO_ACCESS ((uint8_t)0x00)
<01>
MPU_REGION_PRIV_RW ((uint8_t)0x01)
<01>
MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
<01>
MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
<01>
MPU_REGION_PRIV_RO ((uint8_t)0x05)
<01>
MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
<01>
MPU_REGION_NUMBER0 ((uint8_t)0x00)
<01>
MPU_REGION_NUMBER1 ((uint8_t)0x01)
<01>
MPU_REGION_NUMBER2 ((uint8_t)0x02)
<01>
MPU_REGION_NUMBER3 ((uint8_t)0x03)
<01>
MPU_REGION_NUMBER4 ((uint8_t)0x04)
<01>
MPU_REGION_NUMBER5 ((uint8_t)0x05)
<01>
MPU_REGION_NUMBER6 ((uint8_t)0x06)
<01>
MPU_REGION_NUMBER7 ((uint8_t)0x07)
<01>IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || ((GROUP) == NVIC_PRIORITYGROUP_4))
<01>IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
<01>IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
<01>IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
<01>IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
<01>IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE))
<01>IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
<01>IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
<01>IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
<01>IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
<01>IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || ((TYPE) == MPU_TEX_LEVEL1) || ((TYPE) == MPU_TEX_LEVEL2))
<01>IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_P
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM*<2A>EnableC
#NumberC
#
BaseAddressb
#SizeC
#SubRegionDisableC
#	TypeExtFieldC
#
AccessPermissionC
#DisableExecC
#IsShareableC
#
IsCacheableC
#IsBufferableC
#PMPU_Region_InitTypeDef<12>
E
<00><00>

__STM32F4xx_HAL_FLASH_EX_H 
<01>
FLASH_TYPEERASE_SECTORS 0x00000000U
<01>
FLASH_TYPEERASE_MASSERASE 0x00000001U
<01>
FLASH_VOLTAGE_RANGE_1 0x00000000U
<01>
FLASH_VOLTAGE_RANGE_2 0x00000001U
<01>
FLASH_VOLTAGE_RANGE_3 0x00000002U
<01>
FLASH_VOLTAGE_RANGE_4 0x00000003U
<01>
OB_WRPSTATE_DISABLE 0x00000000U
<01>
OB_WRPSTATE_ENABLE 0x00000001U
<01>
OPTIONBYTE_WRP 0x00000001U
<01>
OPTIONBYTE_RDP 0x00000002U
<01>
OPTIONBYTE_USER 0x00000004U
<01>
OPTIONBYTE_BOR 0x00000008U
<01>
OB_RDP_LEVEL_0 ((uint8_t)0xAA)
<01>
OB_RDP_LEVEL_1 ((uint8_t)0x55)
<01>
OB_RDP_LEVEL_2 ((uint8_t)0xCC)
<01>
OB_IWDG_SW ((uint8_t)0x20)
<01>
OB_IWDG_HW ((uint8_t)0x00)
<01>
OB_STOP_NO_RST ((uint8_t)0x40)
<01>
OB_STOP_RST ((uint8_t)0x00)
<01>
OB_STDBY_NO_RST ((uint8_t)0x80)
<01>
OB_STDBY_RST ((uint8_t)0x00)
<01>
OB_BOR_LEVEL3 ((uint8_t)0x00)
<01>
OB_BOR_LEVEL2 ((uint8_t)0x04)
<01>
OB_BOR_LEVEL1 ((uint8_t)0x08)
<01>
OB_BOR_OFF ((uint8_t)0x0C)
<01>
OB_PCROP_STATE_DISABLE 0x00000000U
<01>
OB_PCROP_STATE_ENABLE 0x00000001U
<01>
OPTIONBYTE_PCROP 0x00000001U
<01>
OPTIONBYTE_BOOTCONFIG 0x00000002U
<01>FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
<01>FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
<01>FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
<01>FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
<01>FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
<01>FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
<01>FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
<01>FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
<01>FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
<01>FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS
<01>FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS
<01>FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS
<01>FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS
<01>FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS
<01>FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS
<01>FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS
<01>FLASH_BANK_1 1U
<01>FLASH_BANK_2 2U
<01>FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2)
<01>FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2)
<01>FLASH_SECTOR_0 0U
<01>FLASH_SECTOR_1 1U
<01>FLASH_SECTOR_2 2U
<01>FLASH_SECTOR_3 3U
<01>FLASH_SECTOR_4 4U
<01>FLASH_SECTOR_5 5U
<01>FLASH_SECTOR_6 6U
<01>FLASH_SECTOR_7 7U
<01>FLASH_SECTOR_8 8U
<01>FLASH_SECTOR_9 9U
<01>FLASH_SECTOR_10 10U
<01>FLASH_SECTOR_11 11U
<01>FLASH_SECTOR_12 12U
<01>FLASH_SECTOR_13 13U
<01>FLASH_SECTOR_14 14U
<01>FLASH_SECTOR_15 15U
<01>FLASH_SECTOR_16 16U
<01>FLASH_SECTOR_17 17U
<01>FLASH_SECTOR_18 18U
<01>FLASH_SECTOR_19 19U
<01>FLASH_SECTOR_20 20U
<01>FLASH_SECTOR_21 21U
<01>FLASH_SECTOR_22 22U
<01>FLASH_SECTOR_23 23U
<01>OB_WRP_SECTOR_0 0x00000001U
<01>OB_WRP_SECTOR_1 0x00000002U
<01>OB_WRP_SECTOR_2 0x00000004U
<01>OB_WRP_SECTOR_3 0x00000008U
<01>OB_WRP_SECTOR_4 0x00000010U
<01>OB_WRP_SECTOR_5 0x00000020U
<01>OB_WRP_SECTOR_6 0x00000040U
<01>OB_WRP_SECTOR_7 0x00000080U
<01>OB_WRP_SECTOR_8 0x00000100U
<01>OB_WRP_SECTOR_9 0x00000200U
<01>OB_WRP_SECTOR_10 0x00000400U
<01>OB_WRP_SECTOR_11 0x00000800U
<01>OB_WRP_SECTOR_12 0x00000001U << 12U
<01>OB_WRP_SECTOR_13 0x00000002U << 12U
<01>OB_WRP_SECTOR_14 0x00000004U << 12U
<01>OB_WRP_SECTOR_15 0x00000008U << 12U
<01>OB_WRP_SECTOR_16 0x00000010U << 12U
<01>OB_WRP_SECTOR_17 0x00000020U << 12U
<01>OB_WRP_SECTOR_18 0x00000040U << 12U
<01>OB_WRP_SECTOR_19 0x00000080U << 12U
<01>OB_WRP_SECTOR_20 0x00000100U << 12U
<01>OB_WRP_SECTOR_21 0x00000200U << 12U
<01>OB_WRP_SECTOR_22 0x00000400U << 12U
<01>OB_WRP_SECTOR_23 0x00000800U << 12U
<01>OB_WRP_SECTOR_All 0x00000FFFU << 12U
<01>OB_PCROP_SECTOR_0 0x00000001U
<01>OB_PCROP_SECTOR_1 0x00000002U
<01>OB_PCROP_SECTOR_2 0x00000004U
<01>OB_PCROP_SECTOR_3 0x00000008U
<01>OB_PCROP_SECTOR_4 0x00000010U
<01>OB_PCROP_SECTOR_5 0x00000020U
<01>OB_PCROP_SECTOR_6 0x00000040U
<01>OB_PCROP_SECTOR_7 0x00000080U
<01>OB_PCROP_SECTOR_8 0x00000100U
<01>OB_PCROP_SECTOR_9 0x00000200U
<01>OB_PCROP_SECTOR_10 0x00000400U
<01>OB_PCROP_SECTOR_11 0x00000800U
<01>OB_PCROP_SECTOR_12 0x00000001U
<01>OB_PCROP_SECTOR_13 0x00000002U
<01>OB_PCROP_SECTOR_14 0x00000004U
<01>OB_PCROP_SECTOR_15 0x00000008U
<01>OB_PCROP_SECTOR_16 0x00000010U
<01>OB_PCROP_SECTOR_17 0x00000020U
<01>OB_PCROP_SECTOR_18 0x00000040U
<01>OB_PCROP_SECTOR_19 0x00000080U
<01>OB_PCROP_S
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM*<2A>TypeEraseb
#Banksb
#Sectorb
#NbSectorsb
#VoltageRangeb
#PFLASH_EraseInitTypeDef<12>
>*<2A>OptionTypeb
#WRPStateb
#WRPSectorb
#Banksb
#RDPLevelb
#BORLevelb
#USERConfigC
#PFLASH_OBProgramInitTypeDefS

Y*<2A>OptionTypeb
#PCROPStateb
#Banksb
#SectorsBank1R
#SectorsBank2R
#BootConfigC
#PFLASH_AdvOBProgramInitTypeDef<12>

<01>

<00><00><00>

__STM32F4xx_FLASH_RAMFUNC_H dY






../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h


<01>
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM
<00><00><00>

__STM32F4xx_HAL_FLASH_H 
XHAL_FLASH_ERROR_NONE 0x00000000U
YHAL_FLASH_ERROR_RD 0x00000001U
ZHAL_FLASH_ERROR_PGS 0x00000002U
[HAL_FLASH_ERROR_PGP 0x00000004U
\HAL_FLASH_ERROR_PGA 0x00000008U
]HAL_FLASH_ERROR_WRP 0x00000010U
^HAL_FLASH_ERROR_OPERATION 0x00000020U
fFLASH_TYPEPROGRAM_BYTE 0x00000000U
gFLASH_TYPEPROGRAM_HALFWORD 0x00000001U
hFLASH_TYPEPROGRAM_WORD 0x00000002U
iFLASH_TYPEPROGRAM_DOUBLEWORD 0x00000003U
rFLASH_FLAG_EOP FLASH_SR_EOP
sFLASH_FLAG_OPERR FLASH_SR_SOP
tFLASH_FLAG_WRPERR FLASH_SR_WRPERR
uFLASH_FLAG_PGAERR FLASH_SR_PGAERR
vFLASH_FLAG_PGPERR FLASH_SR_PGPERR
wFLASH_FLAG_PGSERR FLASH_SR_PGSERR
yFLASH_FLAG_RDERR FLASH_SR_RDERR
{FLASH_FLAG_BSY FLASH_SR_BSY
<01>
FLASH_IT_EOP FLASH_CR_EOPIE
<01>
FLASH_IT_ERR 0x02000000U
<01>
FLASH_PSIZE_BYTE 0x00000000U
<01>
FLASH_PSIZE_HALF_WORD 0x00000100U
<01>
FLASH_PSIZE_WORD 0x00000200U
<01>
FLASH_PSIZE_DOUBLE_WORD 0x00000300U
<01>
CR_PSIZE_MASK 0xFFFFFCFFU
<01>
RDP_KEY ((uint16_t)0x00A5)
<01>
FLASH_KEY1 0x45670123U
<01>
FLASH_KEY2 0xCDEF89ABU
<01>
FLASH_OPT_KEY1 0x08192A3BU
<01>
FLASH_OPT_KEY2 0x4C5D6E7FU
<01>
__HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
<01>
__HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
<01>
__HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)
<01>
__HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
<01>
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN)
<01>
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN))
<01>
__HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN)
<01>
__HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN))
<01>
__HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; FLASH->ACR &= ~FLASH_ACR_ICRST; }while(0U)
<01>
__HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; FLASH->ACR &= ~FLASH_ACR_DCRST; }while(0U)
<01>
__HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
<01>__HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
<01>__HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)))
<01>__HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))<03><03>
<01>ACR_BYTE0_ADDRESS 0x40023C00U
<01>OPTCR_BYTE0_ADDRESS 0x40023C14U
<01>OPTCR_BYTE1_ADDRESS 0x40023C15U
<01>OPTCR_BYTE2_ADDRESS 0x40023C16U
<01>OPTCR_BYTE3_ADDRESS 0x40023C17U
<01>IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_BYTE) || ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || ((VALUE) == FLASH_TYPEPROGRAM_WORD) || ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))<00><00>






../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h
stm32f4xx_hal_def.h
stm32f4xx_hal_flash_ex.h
stm32f4xx_hal_flash_ramfunc.h



../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM<13>
FLASH_PROC_NONEFLASH_PROC_SECTERASE
FLASH_PROC_MASSERASEFLASH_PROC_PROGRAMPFLASH_ProcedureTypeDef<12>
3*<2A> ProcedureOnGoing<12>
#NbSectorsToErase<12>
#VoltageForErase<12>
#Sector<12>
#Bank<12>
#Address<12>
#LockC
#ErrorCode<12>
#t0
tb
tC
PFLASH_ProcessTypeDefN

J
<00><00><00>

__STM32F4xx_HAL_PWR_EX_H 
0PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR_MRUDS
1PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
9PWR_FLAG_ODRDY PWR_CSR_ODRDY
:PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY
;PWR_FLAG_UDRDY PWR_CSR_UDSWRDY
HPWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS
JPWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1
LPWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0
<01>
__HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { __IO uint32_t tmpreg = 0x00U; MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); UNUSED(tmpreg); } while(0U)
<01>
__HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE)
<01>
__HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)
<01>
__HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)
<01>
__HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)
<01>
__HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)
<01>
__HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN))
<01>
__HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
<01>
__HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
<01>
FPDS_BIT_NUMBER PWR_CR_FPDS_Pos
<01>
CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
<01>
ODEN_BIT_NUMBER PWR_CR_ODEN_Pos
<01>
CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U))
<01>
ODSWEN_BIT_NUMBER PWR_CR_ODSWEN_Pos
<01>CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))
<01>MRLVDS_BIT_NUMBER PWR_CR_MRLVDS_Pos
<01>CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))
<01>LPLVDS_BIT_NUMBER PWR_CR_LPLVDS_Pos
<01>CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U))
<01>BRE_BIT_NUMBER PWR_CSR_BRE_Pos
<01>CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
<01>IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
<01>IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
<01>IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)ti






../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h
stm32f4xx_hal_def.h


<01>
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM
<00><00><00>

__STM32F4xx_HAL_PWR_H 
CPWR_WAKEUP_PIN1 0x00000100U
KPWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
LPWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
MPWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
NPWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
OPWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
PPWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
QPWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
RPWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
[PWR_PVD_MODE_NORMAL 0x00000000U
\PWR_PVD_MODE_IT_RISING 0x00010001U
]PWR_PVD_MODE_IT_FALLING 0x00010002U
^PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U
_PWR_PVD_MODE_EVENT_RISING 0x00020001U
`PWR_PVD_MODE_EVENT_FALLING 0x00020002U
aPWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U
jPWR_MAINREGULATOR_ON 0x00000000U
kPWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
sPWR_SLEEPENTRY_WFI ((uint8_t)0x01)
tPWR_SLEEPENTRY_WFE ((uint8_t)0x02)
|PWR_STOPENTRY_WFI ((uint8_t)0x01)
}PWR_STOPENTRY_WFE ((uint8_t)0x02)
<01>
PWR_FLAG_WU PWR_CSR_WUF
<01>
PWR_FLAG_SB PWR_CSR_SBF
<01>
PWR_FLAG_PVDO PWR_CSR_PVDO
<01>
PWR_FLAG_BRR PWR_CSR_BRR
<01>
PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
<01>
__HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
<01>
__HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
<01>
__HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
<01>
__HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
<01>
__HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
<01>
__HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
<01>
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
<01>
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
<01>
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
<01>
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
<01>
__HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); }while(0U)
<01>
__HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); }while(0U)
<01>
__HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
<01>__HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
<01>__HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))<03>
<01>PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16)
<01>PWR_OFFSET (PWR_BASE - PERIPH_BASE)
<01>PWR_CR_OFFSET 0x00U
<01>PWR_CSR_OFFSET 0x04U
<01>PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
<01>PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
<01>DBP_BIT_NUMBER PWR_CR_DBP_Pos
<01>CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
<01>PVDE_BIT_NUMBER PWR_CR_PVDE_Pos
<01>CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
<01>VOS_BIT_NUMBER PWR_CR_VOS_Pos
<01>CR_VOS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U))
<01>EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos
<01>CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
<01>IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
<01>IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL))
<01>IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
<01>IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
<01>IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))<00>
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM*<2A>
PVDLevelb
#Modeb
#PPWR_PVDTypeDef<12>
5
<00><00><00>

__STM32F4xx_HAL_UART_H 
<01>
HAL_UART_ERROR_NONE 0x00000000U
<01>
HAL_UART_ERROR_PE 0x00000001U
<01>
HAL_UART_ERROR_NE 0x00000002U
<01>
HAL_UART_ERROR_FE 0x00000004U
<01>
HAL_UART_ERROR_ORE 0x00000008U
<01>
HAL_UART_ERROR_DMA 0x00000010U
<01>UART_WORDLENGTH_8B 0x00000000U
<01>UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
<01>UART_STOPBITS_1 0x00000000U
<01>UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
<01>UART_PARITY_NONE 0x00000000U
<01>UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
<01>UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
<01>UART_HWCONTROL_NONE 0x00000000U
<01>UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
<01>UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
<01>UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
<01>UART_MODE_RX ((uint32_t)USART_CR1_RE)
<01>UART_MODE_TX ((uint32_t)USART_CR1_TE)
<01>UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
<01>UART_STATE_DISABLE 0x00000000U
<01>UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
<01>UART_OVERSAMPLING_16 0x00000000U
<01>UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
<01>UART_LINBREAKDETECTLENGTH_10B 0x00000000U
<01>UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
<01>UART_WAKEUPMETHOD_IDLELINE 0x00000000U
<01>UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
<01>UART_FLAG_CTS ((uint32_t)USART_SR_CTS)
<01>UART_FLAG_LBD ((uint32_t)USART_SR_LBD)
<01>UART_FLAG_TXE ((uint32_t)USART_SR_TXE)
<01>UART_FLAG_TC ((uint32_t)USART_SR_TC)
<01>UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
<01>UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
<01>UART_FLAG_ORE ((uint32_t)USART_SR_ORE)
<01>UART_FLAG_NE ((uint32_t)USART_SR_NE)
<01>UART_FLAG_FE ((uint32_t)USART_SR_FE)
<01>UART_FLAG_PE ((uint32_t)USART_SR_PE)
<01>UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
<01>UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
<01>UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
<01>UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
<01>UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
<01>UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
<01>UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
<01>UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
<01>HAL_UART_RECEPTION_STANDARD (0x00000000U)
<01>HAL_UART_RECEPTION_TOIDLE (0x00000001U)
<01>__HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ (__HANDLE__)->gState = HAL_UART_STATE_RESET; (__HANDLE__)->RxState = HAL_UART_STATE_RESET; } while(0U)
<01>__HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
<01>__HAL_UART_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
<01>__HAL_UART_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
<01>__HAL_UART_CLEAR_PEFLAG(__HANDLE__) do{ __IO uint32_t tmpreg = 0x00U; tmpreg = (__HANDLE__)->Instance->SR; tmpreg = (__HANDLE__)->Instance->DR; UNUSED(tmpreg); } while(0U)
<01>__HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
<01>__HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
<01>__HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
<01>__HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
<01>__HAL_UART_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
<01>__HAL_UART_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__
../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM*<2A>BaudRateb
#WordLengthb
#StopBitsb
#Parityb
#Modeb
#HwFlowCtlb
#OverSamplingb
#PUART_InitTypeDef<12>
K<13>
HAL_UART_STATE_RESETHAL_UART_STATE_READY HAL_UART_STATE_BUSY$HAL_UART_STATE_BUSY_TX!HAL_UART_STATE_BUSY_RX"HAL_UART_STATE_BUSY_TX_RX#HAL_UART_STATE_TIMEOUT<0B>HAL_UART_STATE_ERROR<0B>PHAL_UART_StateTypeDefm

<01>
PHAL_UART_RxTypeTypeDefb

<01>
)<29>__UART_HandleTypeDefDInstance<12>#InitU
#pTxBuffPtr<12># TxXferSizeR
#$TxXferCount<12>#&pRxBuffPtr<12>#(RxXferSizeR
#,RxXferCount<12>#.ReceptionType<12>#0hdmatx<12>#4hdmarx<12>#8LockC
#<gState<12>#=RxState<12>#>ErrorCode<12>#@"%#C
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PUART_HandleTypeDef{
<01>

<00><00><00>

__STM32F4xx_HAL_CONF_H 
&HAL_MODULE_ENABLED 
CHAL_UART_MODULE_ENABLED 
THAL_GPIO_MODULE_ENABLED 
UHAL_EXTI_MODULE_ENABLED 
VHAL_DMA_MODULE_ENABLED 
WHAL_RCC_MODULE_ENABLED 
XHAL_FLASH_MODULE_ENABLED 
YHAL_PWR_MODULE_ENABLED 
ZHAL_CORTEX_MODULE_ENABLED 
cHSE_VALUE 25000000U
gHSE_STARTUP_TIMEOUT 100U
pHSI_VALUE ((uint32_t)16000000U)
wLSI_VALUE 32000U
LSE_VALUE 32768U
<01>
LSE_STARTUP_TIMEOUT 5000U
<01>
EXTERNAL_CLOCK_VALUE 12288000U
<01>
VDD_VALUE 3300U
<01>
TICK_INT_PRIORITY 0U
<01>
USE_RTOS 0U
<01>
PREFETCH_ENABLE 1U
<01>
INSTRUCTION_CACHE_ENABLE 1U
<01>
DATA_CACHE_ENABLE 1U
<01>
USE_HAL_ADC_REGISTER_CALLBACKS 0U
<01>
USE_HAL_CAN_REGISTER_CALLBACKS 0U
<01>
USE_HAL_CEC_REGISTER_CALLBACKS 0U
<01>
USE_HAL_CRYP_REGISTER_CALLBACKS 0U
<01>
USE_HAL_DAC_REGISTER_CALLBACKS 0U
<01>
USE_HAL_DCMI_REGISTER_CALLBACKS 0U
<01>
USE_HAL_DFSDM_REGISTER_CALLBACKS 0U
<01>
USE_HAL_DMA2D_REGISTER_CALLBACKS 0U
<01>
USE_HAL_DSI_REGISTER_CALLBACKS 0U
<01>
USE_HAL_ETH_REGISTER_CALLBACKS 0U
<01>
USE_HAL_HASH_REGISTER_CALLBACKS 0U
<01>
USE_HAL_HCD_REGISTER_CALLBACKS 0U
<01>
USE_HAL_I2C_REGISTER_CALLBACKS 0U
<01>
USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U
<01>
USE_HAL_FMPSMBUS_REGISTER_CALLBACKS 0U
<01>
USE_HAL_I2S_REGISTER_CALLBACKS 0U
<01>
USE_HAL_IRDA_REGISTER_CALLBACKS 0U
<01>
USE_HAL_LPTIM_REGISTER_CALLBACKS 0U
<01>
USE_HAL_LTDC_REGISTER_CALLBACKS 0U
<01>
USE_HAL_MMC_REGISTER_CALLBACKS 0U
<01>
USE_HAL_NAND_REGISTER_CALLBACKS 0U
<01>
USE_HAL_NOR_REGISTER_CALLBACKS 0U
<01>
USE_HAL_PCCARD_REGISTER_CALLBACKS 0U
<01>
USE_HAL_PCD_REGISTER_CALLBACKS 0U
<01>
USE_HAL_QSPI_REGISTER_CALLBACKS 0U
<01>
USE_HAL_RNG_REGISTER_CALLBACKS 0U
<01>
USE_HAL_RTC_REGISTER_CALLBACKS 0U
<01>
USE_HAL_SAI_REGISTER_CALLBACKS 0U
<01>
USE_HAL_SD_REGISTER_CALLBACKS 0U
<01>
USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U
<01>
USE_HAL_SDRAM_REGISTER_CALLBACKS 0U
<01>
USE_HAL_SRAM_REGISTER_CALLBACKS 0U
<01>
USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U
<01>
USE_HAL_SMBUS_REGISTER_CALLBACKS 0U
<01>
USE_HAL_SPI_REGISTER_CALLBACKS 0U
<01>
USE_HAL_TIM_REGISTER_CALLBACKS 0U
<01>
USE_HAL_UART_REGISTER_CALLBACKS 0U
<01>
USE_HAL_USART_REGISTER_CALLBACKS 0U
<01>
USE_HAL_WWDG_REGISTER_CALLBACKS 0U
<01>
MAC_ADDR0 2U
<01>
MAC_ADDR1 0U
<01>
MAC_ADDR2 0U
<01>
MAC_ADDR3 0U
<01>
MAC_ADDR4 0U
<01>
MAC_ADDR5 0U
<01>
ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
<01>
ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
<01>
ETH_RXBUFNB 4U
<01>
ETH_TXBUFNB 4U
<01>
DP83848_PHY_ADDRESS 0x01U
<01>
PHY_RESET_DELAY 0x000000FFU
<01>
PHY_CONFIG_DELAY 0x00000FFFU
<01>
PHY_READ_TO 0x0000FFFFU
<01>
PHY_WRITE_TO 0x0000FFFFU
<01>
PHY_BCR ((uint16_t)0x0000U)
<01>
PHY_BSR ((uint16_t)0x0001U)
<01>
PHY_RESET ((uint16_t)0x8000U)
<01>
PHY_LOOPBACK ((uint16_t)0x4000U)
<01>
PHY_FULLDUPLEX_100M ((uint16_t)0x2100U)
<01>
PHY_HALFDUPLEX_100M ((uint16_t)0x2000U)
<01>
PHY_FULLDUPLEX_10M ((uint16_t)0x0100U)
<01>
PHY_HALFDUPLEX_10M ((uint16_t)0x0000U)
<01>
PHY_AUTONEGOTIATION ((uint16_t)0x1000U)
<01>
PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U)
<01>
PHY_POWERDOWN ((uint16_t)0x0800U)
<01>
PHY_ISOLATE ((uint16_t)0x0400U)
<01>
PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U)
<01>
PHY_LINKED_STATUS ((uint16_t)0x0004U)
<01>
PHY_JABBER_DETECTION ((uint16_t)0x0002U)
<01>
PHY_SR ((uint16_t)0x10U)
<01>PHY_SPEED_STATUS ((uint16_t)0x0002U)
<01>PHY
../Core/Inc/stm32f4xx_hal_conf.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM
<00><00><00>

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../Core/Inc/../Drivers/STM32F4xx_HAL_Driver/Inc/main.h
stm32f4xx_hal.h

<01>
../Core/Inc/main.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM
<00><00><00>

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../Core/Inc/usart.h
main.h


<01>
../Core/Inc/usart.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM
<00><00><00>
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../Core/Inc/../Core/Src/usart.cusart.h


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../Core/Src/usart.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM"<10>tb

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