MicrochipFor32/MX_FastSet/T103C8T6/MDK-ARM/template/mainsystem.o

ELF



(
<00>	4(

@<40>pG<70><47>pGO<47>0pGpG<70><47>
IH<><48><EFBFBD><EFBFBD>


<00>
bsp_System\\MainSystem.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]D:\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\GitHub\MicrochipFor32\MX_FastSet\T103C8T6\MDK-ARM__asm___14_MainSystem_cpp_com___Z7__REV16jX>







..\Drivers\CMSIS\Include\cmsis_armcc.h
<03>


<01>
bsp_System\\MainSystem.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]D:\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\GitHub\MicrochipFor32\MX_FastSet\T103C8T6\MDK-ARM__asm___14_MainSystem_cpp_com___Z7__REVSHsX>







..\Drivers\CMSIS\Include\cmsis_armcc.h
<03>


<01>
bsp_System\\MainSystem.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]D:\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\GitHub\MicrochipFor32\MX_FastSet\T103C8T6\MDK-ARM__asm___14_MainSystem_cpp_com___Z5__RRXjX>







..\Drivers\CMSIS\Include\cmsis_armcc.h
<03>
&

0<00><><EFBFBD><EFBFBD>armcc+
|

	
0<00><><EFBFBD><EFBFBD>armcc+
|

	
0<00><><EFBFBD><EFBFBD>armcc+
|

	
0<00><><EFBFBD><EFBFBD>armcc+|

	
0<00><><EFBFBD><EFBFBD>armcc+|

	
0<00><><EFBFBD><EFBFBD>armcc+|

	
<00>bsp_System\MainSystem.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103C8T6\MDK-ARM<00>bsp_System\MainSystem.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103C8T6\MDK-ARM<00>
com<10>
<00>bsp_System\MainSystem.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103C8T6\MDK-ARMV<>

1MainInit
<00>bsp_System\MainSystem.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103C8T6\MDK-ARMV<>

:MainSystem
<0






bsp_System\MainSystem.cpp

L1





bsp_System\MainSystem.cpp
	2



L1





bsp_System\MainSystem.cpp
:



}}
__DATE__ "Apr 24 2023"
__TIME__ "02:25:58"
__STDC__ 1
__cplusplus 199711L
_BOOL 1
__ARRAY_OPERATORS 1
__IMPLICIT_INCLUDE 1
__RTTI 1
__EDG_RUNTIME_USES_NAMESPACES 1
__EDG_IA64_ABI 1
__EDG_IA64_ABI_VARIANT_CTORS_AND_DTORS_RETURN_THIS 1
__EDG_IA64_ABI_USE_INT_STATIC_INIT_GUARD 1
__EDG_TYPE_TRAITS_ENABLED 1
__EDG__ 1
__EDG_VERSION__ 407
__EDG_SIZE_TYPE__ unsigned int
__EDG_PTRDIFF_TYPE__ int
__sizeof_int 4
__sizeof_long 4
__sizeof_ptr 4
__ARMCC_VERSION 5060960
__TARGET_CPU_CORTEX_M3 1
__TARGET_FPU_SOFTVFP 1
__TARGET_FPU_SOFTVFP 1
__UVISION_VERSION 537
_RTE_ 1
STM32F10X_MD 1
_RTE_ 1
USE_HAL_DRIVER 1
STM32F103xB 1
__CC_ARM 1
__arm 1
__arm__ 1
__TARGET_ARCH_7_M 1
__TARGET_ARCH_ARM 0
__TARGET_ARCH_THUMB 4
__TARGET_ARCH_A64 0
__TARGET_ARCH_AARCH32 1
__TARGET_PROFILE_M 1
__TARGET_FEATURE_HALFWORD 1
__TARGET_FEATURE_THUMB 1
__TARGET_FEATURE_MULTIPLY 1
__TARGET_FEATURE_DOUBLEWORD 1
__TARGET_FEATURE_DIVIDE 1
__TARGET_FEATURE_UNALIGNED 1
__TARGET_FEATURE_CLZ 1
__TARGET_FEATURE_DMB 1
__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0
__APCS_INTERWORK 1
__thumb 1
__thumb__ 1
__t32__ 1
__OPTIMISE_SPACE 1
__OPT_SMALL_ASSERT 1
__OPTIMISE_LEVEL 3
__SOFTFP__ 1
<00><00>com<00><00>MainInit<00><00>MainSystem
&

%

.


()*

'__DEBUG__ 
+_STM32_HAL_ 
.BPS_CONFIG_VERSION "1.0.0"
3EQ_CheckBox 0
7EQ_NumBox 0
>EQ_BITERABI 0x000
BEQ_BITERABIS 0x00
Itext(format,__VA_ARGS__...) com.print(format, ## __VA_ARGS__)4)






bsp_System\User.h


<01>bsp_System\User.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103C8T6\MDK-ARM
,-.

__stdint_h 
__ARMCLIB_VERSION 5060044
__INT64 __int64
__INT64_C_SUFFIX__ ll
__PASTE2(x,y) x ## y
__PASTE(x,y) __PASTE2(x, y)
__INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))
__UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))
__LONGLONG long long
#__STDINT_DECLS %__CLIBNS
)__CLIBNS std::<02>__INT64<02>__LONGLONGXM






D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h


D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]
unsigned charunsigned shortunsigned intunsigned long long
signed charshortintlong long<00>
<01>stdiint8_t<12>
8 iint16_t<12>
9 iint32_t<12>
: iint64_t<12>
; iuint8_t<12>
> iuint16_t<12>
? iuint32_t<12>
@ iuint64_t<12>
A iint_least8_t<12>
G iint_least16_t<12>
H iint_least32_t<12>
I iint_least64_t<12>
J iuint_least8_t<12>
M iuint_least16_t<12>
N iuint_least32_t<12>
O iuint_least64_t<12>
P iint_fast8_t<12>
U iint_fast16_t<12>
V iint_fast32_t<12>
W iint_fast64_t<12>
X iuint_fast8_t<12>
[ iuint_fast16

<01>__set_FPSCR3j
fpscr
HIJ

__CMSIS_COMPILER_H "<00><00>






../Drivers/CMSIS/Include/D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\cmsis_compiler.h
stdint.hcmsis_armcc.h


<01>../Drivers/CMSIS/Include/cmsis_compiler.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103C8T6\MDK-ARM
LMNO

 __CORE_CM3_H_GENERIC "?
B__CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
C__CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
D__CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | __CM3_CMSIS_VERSION_SUB )
G__CORTEX_M (3U)
L__FPU_USED 0Us
__CORE_CM3_H_DEPENDANT 
<01>
__I volatile
<01>
__O volatile
<01>
__IO volatile
<01>
__IM volatile const
<01>
__OM volatile
<01>
__IOM volatile
<01>
APSR_N_Pos 31U
<01>
APSR_N_Msk (1UL << APSR_N_Pos)
<01>
APSR_Z_Pos 30U
<01>
APSR_Z_Msk (1UL << APSR_Z_Pos)
<01>
APSR_C_Pos 29U
<01>
APSR_C_Msk (1UL << APSR_C_Pos)
<01>
APSR_V_Pos 28U
<01>
APSR_V_Msk (1UL << APSR_V_Pos)
<01>
APSR_Q_Pos 27U
<01>
APSR_Q_Msk (1UL << APSR_Q_Pos)
<01>
IPSR_ISR_Pos 0U
<01>
IPSR_ISR_Msk (0x1FFUL )
<01>xPSR_N_Pos 31U
<01>xPSR_N_Msk (1UL << xPSR_N_Pos)
<01>xPSR_Z_Pos 30U
<01>xPSR_Z_Msk (1UL << xPSR_Z_Pos)
<01>xPSR_C_Pos 29U
<01>xPSR_C_Msk (1UL << xPSR_C_Pos)
<01>xPSR_V_Pos 28U
<01>xPSR_V_Msk (1UL << xPSR_V_Pos)
<01>xPSR_Q_Pos 27U
<01>xPSR_Q_Msk (1UL << xPSR_Q_Pos)
<01>xPSR_ICI_IT_2_Pos 25U
<01>xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)
<01>xPSR_T_Pos 24U
<01>xPSR_T_Msk (1UL << xPSR_T_Pos)
<01>xPSR_ICI_IT_1_Pos 10U
<01>xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)
<01>xPSR_ISR_Pos 0U
<01>xPSR_ISR_Msk (0x1FFUL )
<01>CONTROL_SPSEL_Pos 1U
<01>CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
<01>CONTROL_nPRIV_Pos 0U
<01>CONTROL_nPRIV_Msk (1UL )
<01>NVIC_STIR_INTID_Pos 0U
<01>NVIC_STIR_INTID_Msk (0x1FFUL )
<01>SCB_CPUID_IMPLEMENTER_Pos 24U
<01>SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
<01>SCB_CPUID_VARIANT_Pos 20U
<01>SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
<01>SCB_CPUID_ARCHITECTURE_Pos 16U
<01>SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
<01>SCB_CPUID_PARTNO_Pos 4U
<01>SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
<01>SCB_CPUID_REVISION_Pos 0U
<01>SCB_CPUID_REVISION_Msk (0xFUL )
<01>SCB_ICSR_NMIPENDSET_Pos 31U
<01>SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
<01>SCB_ICSR_PENDSVSET_Pos 28U
<01>SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
<01>SCB_ICSR_PENDSVCLR_Pos 27U
<01>SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
<01>SCB_ICSR_PENDSTSET_Pos 26U
<01>SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
<01>SCB_ICSR_PENDSTCLR_Pos 25U
<01>SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
<01>SCB_ICSR_ISRPREEMPT_Pos 23U
<01>SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
<01>SCB_ICSR_ISRPENDING_Pos 22U
<01>SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
<01>SCB_ICSR_VECTPENDING_Pos 12U
<01>SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
<01>SCB_ICSR_RETTOBASE_Pos 11U
<01>SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
<01>SCB_ICSR_VECTACTIVE_Pos 0U
<01>SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
<01>SCB_VTOR_TBLBASE_Pos 29U
<01>SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)
<01>SCB_VTOR_TBLOFF_Pos 7U
<01>SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
<01>SCB_AIRCR_VECTKEY_Pos 16U
<01>SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
<01>SCB_AIRCR_VECTKEYSTAT_Pos 16U
<01>SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
<01>SCB_AIRCR_ENDIANESS_Pos 15U
<01>SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
<01>SCB_AIRCR_PRIGROUP_Pos 8U
<01>SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
<01>SCB_AIRCR_SYSRESETREQ_Pos 2U
<01>SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
<01>SCB_AIRCR_VECTCLRACTIVE_Pos 1U
<01>SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
<01>SCB_AIRCR_VECTRESET_Pos 0U
<01>SCB_AIRCR_VECTRESET_Msk (1UL )
<01>SCB_SCR_SEVONPEND_Pos 4U
<01>SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
<01>SCB_SCR_SLEEPDEEP_Pos 2U
<01>SCB_SCR_SL
CoreDebug_DHCSR_S_REGRDY_Pos 16U
<01>
CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
<01>
CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
<01>
CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
<01>
CoreDebug_DHCSR_C_MASKINTS_Pos 3U
<01>
CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
<01>
CoreDebug_DHCSR_C_STEP_Pos 2U
<01>
CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
<01>
CoreDebug_DHCSR_C_HALT_Pos 1U
<01>
CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
<01>
CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
<01>
CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL )
<01>
CoreDebug_DCRSR_REGWnR_Pos 16U
<01>
CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
<01>
CoreDebug_DCRSR_REGSEL_Pos 0U
<01>
CoreDebug_DCRSR_REGSEL_Msk (0x1FUL )
<01>
CoreDebug_DEMCR_TRCENA_Pos 24U
<01>
CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
<01>
CoreDebug_DEMCR_MON_REQ_Pos 19U
<01>
CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
<01>
CoreDebug_DEMCR_MON_STEP_Pos 18U
<01>
CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
<01>
CoreDebug_DEMCR_MON_PEND_Pos 17U
<01>
CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
<01>
CoreDebug_DEMCR_MON_EN_Pos 16U
<01>
CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
<01>
CoreDebug_DEMCR_VC_HARDERR_Pos 10U
<01>
CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
<01>
CoreDebug_DEMCR_VC_INTERR_Pos 9U
<01>
CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
<01>
CoreDebug_DEMCR_VC_BUSERR_Pos 8U
<01>
CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
<01>
CoreDebug_DEMCR_VC_STATERR_Pos 7U
<01>
CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
<01>
CoreDebug_DEMCR_VC_CHKERR_Pos 6U
<01>
CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
<01>
CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
<01>
CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
<01>
CoreDebug_DEMCR_VC_MMERR_Pos 4U
<01>
CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
<01>
CoreDebug_DEMCR_VC_CORERESET_Pos 0U
<01>
CoreDebug_DEMCR_VC_CORERESET_Msk (1UL )
<01>
_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
<01>
_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
<01>
SCS_BASE (0xE000E000UL)
<01>
ITM_BASE (0xE0000000UL)
<01>
DWT_BASE (0xE0001000UL)
<01>
TPI_BASE (0xE0040000UL)
<01>
CoreDebug_BASE (0xE000EDF0UL)
<01>
SysTick_BASE (SCS_BASE + 0x0010UL)
<01>
NVIC_BASE (SCS_BASE + 0x0100UL)
<01>
SCB_BASE (SCS_BASE + 0x0D00UL)
<01>
SCnSCB ((SCnSCB_Type *) SCS_BASE )
<01>
SCB ((SCB_Type *) SCB_BASE )
<01>
SysTick ((SysTick_Type *) SysTick_BASE )
<01>
NVIC ((NVIC_Type *) NVIC_BASE )
<01>
ITM ((ITM_Type *) ITM_BASE )
<01>
DWT ((DWT_Type *) DWT_BASE )
<01>
TPI ((TPI_Type *) TPI_BASE )
<01>
CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
<01>NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
<01>NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
<01>NVIC_EnableIRQ __NVIC_EnableIRQ
<01>NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
<01>NVIC_DisableIRQ __NVIC_DisableIRQ
<01>NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
<01>NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
<01>NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
<01>NVIC_GetActive __NVIC_GetActive
<01>NVIC_SetPriority __NVIC_SetPriority
<01>NVIC_GetPriority __NVIC_GetPriority
<01>NVIC_SystemReset __NVIC_SystemReset
<01>NVIC_SetVector __NVIC_SetVector
<01>NVIC_GetVector __NVIC_GetVector
<01>NVIC_USER_IRQ_OFFSET 16
<01>EXC_RETURN_HANDLER (0xFFFFFFF1UL)
<01>EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL)
<01>EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL)
<01>ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)<00><00>






../Drivers/CMSIS/Include/D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\core_cm3.h
stdint.hcmsis_version.h
cmsis_compiler.h


`../Drivers/CMSIS/Include/core_cm3.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103C8T6\MDK-ARMl<>'b<12>'wj
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#	)_reserved0j
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<01>l<>'b<12>'wj
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#iCONTROL_Type~
<01>B<><08><03>(
&ISER<12>#<03>j

&RESERVED0# <03>(
&ICER#<23>
<03>j

&RSERVED12#<23>
<03>(
&ISPRN#<23><03>j

&RESERVED2d#<23><03>(
&ICPR<12>#<23><03>j

&RESERVED3<12>#<23><03>(
&IABR<12>#<23><03>j

7&RESERVED4<12>#<23><03>/
<01>
&IP<12>#<23><03>j

<01>&RESERVED5<12>#<23>&STIR(#<23><00>
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<00>
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iNVIC_Type<12>
<01>B<>
<EFBFBD>
&CPUID<12>#&ICSR(#&VTOR(#&AIRCR(#&SCR(#&CCR(#<03>	/
&SHP<12>#&SHCSR(#$&CFSR(#(&HFSR(#,&DFSR(#0&MMFAR(#4&BFAR(#8&AFSR(#<<03>
<12>

&PFR<12>#@&DFR<12>#H&ADR<12>#L<03>
<12>
&MMFR)#P<03>
<12>
&ISAR>#`<03>
j

&RESERVED0S#t&CPACR(#<23>
j
<00>
~iSCB_TypeH
<01>B<><03>j

&RESERVED0<12>#&ICTR<12>#&ACTLR(#iSCnSCB_Type<12>
<01>B<>&CTRL(#&LOAD(#&VAL(#&CALIB<12>#iSysTick_Type<12>
<01>B<><10> <20>
<12><03>7
&PORT<#<03>j

<01>&RESERVED0Q#<23>
&TER(#<23><03>
j

&RESERVED1{#<23>&TPR(#<23><03>
j

&RESERVED2<12>#<23>&TCR(#<23><03>
j

&RESERVED3<12>#<23>&IWR(#<23>&IRR<12>#<23>&IMCR(#<23><03>j

*&RESERVED4#<23>&LAR(#<23>&LSR<12>#<23><03>j

&RESERVED5D#<23>&PID4<12>#<23>&PID5<12>#<23>&PID6<12>#<23>&PID7<12>#<23>&PID0<12>#<23>&PID1<12>#<23>&PID2<12>#<23>&PID3<12>#<23>&CID0<12>#<23>&CID1<12>#<23>&CID2<12>#<23>&CID3<12>#<23>l<>'u8/'u16'u32(<00>
Z
iITM_Type2
<01>B<>\&CTRL(#&CYCCNT(#&CPICNT(#&EXCCNT(#&SLEEPCNT(#&LSUCNT(#&FOLDCNT(#&PCSR<12>#&COMP0(# &MASK0(#$&FUNCTION0(#(<03>j

&RESERVED0<12>#,&COMP1(#0&MASK1(#4&FUNCTION1(#8<03>j

&RESERVED1	#<&COMP2(#@&MASK2(#D&FUNCTION2(#H<03>j

&RESERVED2^	#L&COMP3(#P&MASK3(#T&FUNCTION3(#XiDWT_Type2
<01>B<><17>&SSPSR<12>#&CSPSR(#<03>j


&RESERVED0<12>	#&ACPR(#<03>j

6&RESERVED1<12>	#&SPPR(#<23>
<03>j

<01>
&RESERVED2'
#<23>
&FFSR<12>#<23>&FFCR(#<23>&FSCR<12>#<23><03>j

<01>&RESERVED3l
#<23>&TRIGGER<12>#<23>&FIFO0<12>#<23>&ITATBCTR2<12>#<23><03>j

&RESERVED4<12>
#<23>&ITATBCTR0<12>#<23>&FIFO1<12>#<23>&ITCTRL(#<23><03>j

&&RESERVED5#<23>&CLAIMSET(#<23>&CLAIMCLR(#<23><03>j

&RESERVED7E#<23>&DEVID<12>#<23>&DEVTYPE<12>#<23>iTPI_Type<12>	
<01>B<>&DHCSR(#&DCRSR(#&DCRDR(#&DEMCR(#iCoreDebug_Type<12>
<01>	<03>
-
<00>
ITM_RxBuffer<12>

S<>
<01>__NVIC_SetPriorityGrouping3j
PriorityGroupureg_valuej
uPriorityGroupTmpj
R<>
<01>__NVIC_GetPriorityGroupingj
z__resultj

S<>
<01>__NVIC_EnableIRQ3IRQnR<>
<01>__NVIC_GetEnableIRQj
3IRQnz__resultj

S<>
<01>__NVIC_DisableIRQ3IRQnR<>
<01>__NVIC_GetPendingIRQj
3IRQnz__resultj

S<>
<01>__NVIC_SetPendingIRQ3IRQnS<>
<01>__NVIC_ClearPendingIRQ3IRQnR<>
<01>__NVIC_GetActivej
3IRQnz__resultj

S<>
<01>__NVIC_SetPriority3IRQn3j
priorityR<>
<01>__NVIC_GetPriorityj
3IRQnz__resultj

R<>
<01>
NVIC_EncodePriorityj
3j
PriorityGroup3j
PreemptPriority3j
SubPriorityz__resultj

uPriorityGroupTmpj
uPreemptPriorityBitsj
uSubPriorityBitsj
S<>
<01>
NVIC_DecodePriority3j
Priority3j
PriorityGroup3<12>pPreemptPriority3<12>pSubPriorityuPriorityGroupTmpj
uPreemptPriorityBitsj
uSubPriorityBitsj
0j
S<> 
<01>
__NVIC_SetVector3IRQn3j
vectoruvectors<12>R<> 
<01>
__NVIC_GetVectorj
3IRQnz__resultj

uvectors<12>S<> 
<01>
"__NVIC_SystemResetR<>!
<01>SCB_GetFPUTypej
z__resultj

R<>!
<01>SysTick_Configj
3j
ticksz__resultj

R<>!
<01>ITM_SendCharj
3j
chz__resultj

R<>"
<01>ITM_ReceiveChar-
z__result-

uch-
R<>"
<01>ITM_CheckChar-
z__result-

d<00>ITM_RxBuffer
QRST

 __SYSTEM_STM32F10X_H `W






../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h


8
../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103C8T6\MDK-ARM<00>
SystemCoreClockj


K
<03><12>
<00>
AHBPrescTable<12>

<03><12>
<00>
APBPrescTable


F<
<00>SystemCoreClock
AHBPrescTable"
APBPrescTable
VWX

&__STM32F103xB_H 
2__CM3_REV 0x0200U
3__MPU_PRESENT 0U
4__NVIC_PRIO_BITS 4U
5__Vendor_SysTickConfig 0U<03>
<03>
<03>

<01>FLASH_BASE 0x08000000UL
<01>FLASH_BANK1_END 0x0801FFFFUL
<01>SRAM_BASE 0x20000000UL
<01>PERIPH_BASE 0x40000000UL
<01>SRAM_BB_BASE 0x22000000UL
<01>PERIPH_BB_BASE 0x42000000UL
<01>APB1PERIPH_BASE PERIPH_BASE
<01>APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
<01>AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
<01>TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)
<01>TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)
<01>TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)
<01>RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)
<01>WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)
<01>IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)
<01>SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)
<01>USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)
<01>USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)
<01>I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)
<01>I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)
<01>CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL)
<01>BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL)
<01>PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)
<01>AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL)
<01>EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)
<01>GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL)
<01>GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL)
<01>GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL)
<01>GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL)
<01>GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL)
<01>ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL)
<01>ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL)
<01>TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)
<01>SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)
<01>USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)
<01>DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
<01>DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL)
<01>DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL)
<01>DMA1_Channel3_BASE (AHBPERIPH_BAS
RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos)
<01>
RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk
<01>
RCC_APB2ENR_IOPAEN_Pos (2U)
<01>
RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos)
<01>
RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk
<01>
RCC_APB2ENR_IOPBEN_Pos (3U)
<01>
RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos)
<01>
RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk
<01>
RCC_APB2ENR_IOPCEN_Pos (4U)
<01>
RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos)
<01>
RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk
<01>
RCC_APB2ENR_IOPDEN_Pos (5U)
<01>
RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos)
<01>
RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk
<01>
RCC_APB2ENR_ADC1EN_Pos (9U)
<01>
RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
<01>
RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
<01>
RCC_APB2ENR_ADC2EN_Pos (10U)
<01>
RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
<01>
RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
<01>
RCC_APB2ENR_TIM1EN_Pos (11U)
<01>
RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
<01>
RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
<01>
RCC_APB2ENR_SPI1EN_Pos (12U)
<01>
RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
<01>
RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
<01>
RCC_APB2ENR_USART1EN_Pos (14U)
<01>
RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
<01>
RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
<01>
RCC_APB2ENR_IOPEEN_Pos (6U)
<01>
RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos)
<01>
RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk
<01>
RCC_APB1ENR_TIM2EN_Pos (0U)
<01>
RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
<01>
RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
<01>
RCC_APB1ENR_TIM3EN_Pos (1U)
<01>
RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
<01>
RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
<01>
RCC_APB1ENR_WWDGEN_Pos (11U)
<01>
RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
<01>
RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
<01>
RCC_APB1ENR_USART2EN_Pos (17U)
<01>
RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
<01>
RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
<01>
RCC_APB1ENR_I2C1EN_Pos (21U)
<01>
RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
<01>
RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
<01>
RCC_APB1ENR_CAN1EN_Pos (25U)
<01>
RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
<01>
RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
<01>
RCC_APB1ENR_BKPEN_Pos (27U)
<01>
RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos)
<01>
RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk
<01>
RCC_APB1ENR_PWREN_Pos (28U)
<01>
RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
<01>
RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
<01>
RCC_APB1ENR_TIM4EN_Pos (2U)
<01>
RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
<01>
RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
<01>
RCC_APB1ENR_SPI2EN_Pos (14U)
<01>
RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
<01>
RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
<01>
RCC_APB1ENR_USART3EN_Pos (18U)
<01>
RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
<01>
RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
<01>
RCC_APB1ENR_I2C2EN_Pos (22U)
<01>
RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
<01>
RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
<01>
RCC_APB1ENR_USBEN_Pos (23U)
<01>
RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos)
<01>
RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk
<01>
RCC_BDCR_LSEON_Pos (0U)
<01>
RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
<01>
RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
<01>
RCC_BDCR_LSERDY_Pos (1U)
<01>
RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
<01>
RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
<01>
RCC_BDCR_LSEBYP_Pos (2U)
<01>
RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
<01>
RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
<01>
RCC_BDCR_RTCSEL_Pos (8U)
<01>
RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
<01>
RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
<01>
RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
<01>
RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
<01>
RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U
<01>
RCC_BDCR_RTCSEL_LSE 0x00000100U
<01>
RCC_BDCR_RTCSEL_LSI 0x00000200U
<01>
RCC_BDCR_RTCSEL_HSE 0x00000300U
<01>
RCC_BDCR_RTCEN_Pos (15U)
<01>
RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
<01>
RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
<01>
RCC_BDCR_BDRST_Pos (16U)
<01>
RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
<01>
RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
<01>
RCC_CSR_LSION_Pos (0U)
<01>
RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
<01>
RCC_CSR_LSION RCC_CSR_LSION_Msk
<01>
RCC_CSR_LSIRDY_Pos (1U)
<01>
RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
<01>
RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
<01>
RCC_CSR_RMVF_Pos (24U)
<01>RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
<01>RCC_CSR_RMVF RCC_CSR_RMVF_Msk
<01>RCC_CSR_PINRSTF_Pos (26U)
<01>RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
<01>RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
<01>RCC_CSR_PORRSTF_Pos (27U)
<01>RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
<01>RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
<01>RCC_CSR_SFTRSTF_Pos (28U)
<01>RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
<01>RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
<01>RCC_CSR_IWDGRSTF_Pos (29U)
<01>RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
<01>RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
<01>RCC_CSR_WWDGRSTF_Pos (30U)
<01>RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
<01>RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
<01>RCC_CSR_LPWRRSTF_Pos (31U)
<01>RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
<01>RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
<01>GPIO_CRL_MODE_Pos (0U)
<01>GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos)
<01>GPIO_CRL_MODE GPIO_CRL_MODE_Msk
<01>GPIO_CRL_MODE0_Pos (0U)
<01>GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos)
<01>GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk
<01>GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos)
<01>GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos)
<01>GPIO_CRL_MODE1_Pos (4U)
<01>GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos)
<01>GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk
<01>GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos)
<01>GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos)
<01>GPIO_CRL_MODE2_Pos (8U)
<01>GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos)
<01>GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk
<01>GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos)
<01>GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos)
<01>GPIO_CRL_MODE3_Pos (12U)
<01>GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos)
<01>GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk
<01>GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos)
<01>GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos)
<01>GPIO_CRL_MODE4_Pos (16U)
<01>GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos)
<01>GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk
<01>GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos)
<01>GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos)
<01>GPIO_CRL_MODE5_Pos (20U)
<01>GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos)
<01>GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk
<01>GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos)
<01>GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos)
<01>GPIO_CRL_MODE6_Pos (24U)
<01>GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos)
<01>GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk
<01>GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos)
<01>GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos)
<01>GPIO_CRL_MODE7_Pos (28U)
<01>GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos)
<01>GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk
<01>GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos)
<01>GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos)
<01>GPIO_CRL_CNF_Pos (2U)
<01>GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos)
<01>GPIO_CRL_CNF GPIO_CRL_CNF_Msk
<01>GPIO_CRL_CNF0_Pos (2U)
<01>GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos)
<01>GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk
<01>GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos)
<01>GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos)
<01>GPIO_CRL_CNF1_Pos (6U)
<01>GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos)
<01>GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk
<01>GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos)
<01>GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos)
<01>GPIO_CRL_CNF2_Pos (10U)
<01>GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos)
<01>GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk
<01>GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos)
<01>GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos)
<01>GPIO_CRL_CNF3_Pos (14U)
<01>GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos)
<01>GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk
<01>GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos)
<01>GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos)
<01>GPIO_CRL_CNF4_Pos (18U)
<01>GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos)
<01>GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk
<01>GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos)
<01>GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos)
<01>GPIO_CRL_CNF5_Pos (22U)
<01>GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos)
<01>GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk
<01>GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos)
<01>GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos)
<01>GPIO_CRL_CNF6_Pos (26U)
<01>GPIO
DMA1_Channel1_IRQnDMA1_Channel2_IRQnDMA1_Channel3_IRQn
DMA1_Channel4_IRQnDMA1_Channel5_IRQnDMA1_Channel6_IRQnDMA1_Channel7_IRQnADC1_2_IRQnUSB_HP_CAN1_TX_IRQnUSB_LP_CAN1_RX0_IRQnCAN1_RX1_IRQnCAN1_SCE_IRQnEXTI9_5_IRQnTIM1_BRK_IRQnTIM1_UP_IRQnTIM1_TRG_COM_IRQnTIM1_CC_IRQnTIM2_IRQnTIM3_IRQnTIM4_IRQnI2C1_EV_IRQnI2C1_ER_IRQn I2C2_EV_IRQn!I2C2_ER_IRQn"SPI1_IRQn#SPI2_IRQn$USART1_IRQn%USART2_IRQn&USART3_IRQn'EXTI15_10_IRQn(RTC_Alarm_IRQn)USBWakeUp_IRQn*iIRQn_Type<12>
~B<>
P&SR#&CR1#&CR2#&SMPR1#&SMPR2#&JOFR1#&JOFR2#&JOFR3#&JOFR4# &HTR#$&LTR#(&SQR1#,&SQR2#0&SQR3#4&JSQR#8&JDR1#<&JDR2#@&JDR3#D&JDR4#H&DR#L<00>
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iADC_TypeDef*
<01>
B<>P&SR#&CR1#&CR2#<03>
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&RESERVED\#&DR#LiADC_Common_TypeDef8
<01>
B<>8&RESERVED0j
#&DR1#&DR2#&DR3#&DR4#&DR5#&DR6#&DR7#&DR8# &DR9#$&DR10#(&RTCCR#,&CR#0&CSR#4iBKP_TypeDef<12>
<01>
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&TIR#&TDTR#&TDLR#&TDHR#iCAN_TxMailBox_TypeDefZ
<01>
B<>
&RIR#&RDTR#&RDLR#&RDHR#iCAN_FIFOMailBox_TypeDef<12>
<01>
B<>&FR1#&FR2#iCAN_FilterRegister_TypeDef
<01>
B<><11>&MCR#&MSR#&TSR#&RF0R#&RF1R#&IER#&ESR#&BTR#<03>j

W&RESERVED0<12># <03><12>
&sTxMailBox<12>#<23><03><12>

&sFIFOMailBox<12>#<23><03>j

&RESERVED1<12>#<23>&FMR#<23>&FM1R#<23>&RESERVED2j
#<23>&FS1R#<23>&RESERVED3j
#<23>&FFA1R#<23>&RESERVED4j
#<23>&FA1R#<23><03>j

&RESERVED5<12>#<23><03>

&sFilterRegister<12>#<23>iCAN_TypeDef>
<01>B<>&DR#&IDR*	#&RESERVED0K
#&RESERVED1Z
#&CR#<00>
K
iCRC_TypeDef<12>
<01>B<>&IDCODE#&CR#iDBGMCU_TypeDefE	
<01>B<>&CCR#&CNDTR#&CPAR#&CMAR#iDMA_Channel_TypeDefy	
<01>B<>&ISR#&IFCR#iDMA_TypeDef<12>	
<01>B<>&IMR#&EMR#&RTSR#&FTSR#&SWIER#&PR#iEXTI_TypeDef<12>	
<01>B<>$&ACR#&KEYR#&OPTKEYR#&SR#&CR#&AR#&RESERVED#&OBR#&WRPR# iFLASH_TypeDefY

<01>B<>&RDPE#&USERE#&Data0E#&Data1E#&WRP0E#&WRP1E#
&WRP2E#&WRP3E#<00>
Z
iOB_TypeDef<12>

<01>B<>&CRL#&CRH#&IDR#&ODR#&BSRR#&BRR#&LCKR#iGPIO_TypeDef_
<01>B<> &EVCR#&MAPR#<03>
&EXTICR<12>#&RESERVED0j
#&MAPR2#iAFIO_TypeDef<12>
<01>B<>$&CR1#&CR2#&OAR1#&OAR2#&DR#&SR1#&SR2#&CCR#&TRISE# iI2C_TypeDef1
<01>B<>&KR#&PR#&RLR#&SR#iIWDG_TypeDef<12>
<01>B<>&CR#&CSR#iPWR_TypeDef<12>
<01>B<>(&CR#&CFGR#&CIR#&APB2RSTR#&APB1RSTR#&AHBENR#&APB2ENR#&APB1ENR#&BDCR# &CSR#$iRCC_TypeDef!

<01>B<>(&CRH#&CRL#&PRLH#&PRLL#&DIVH#&DIVL#&CNTH#&CNTL#&ALRH# &ALRL#$iRTC_TypeDef<12>

<01>B<> &CR1#&CR2#&SR#&DR#&CRCPR#&RXCRCR#&TXCRCR#&I2SCFGR#iSPI_TypeDefM
<01>B<>T&CR1#&CR2#&SMCR#&DIER#&SR#&EGR#&CCMR1#&CCMR2#&CCER# &CNT#$&PSC#(&ARR#,&RCR#0&CCR1#4&CCR2#8&CCR3#<&CCR4#@&BDTR#D&DCR#H&DMAR#L&OR#PiTIM_TypeDef<12>
<01>B<> &SR#&DR#&BRR#&CR1#&CR2#&CR3#&GTPR#iUSART_TypeDef<12>
<01>B<>#T&EP0RE#&RESERVED0E#&EP1RE#&RESERVED1E#&EP2RE#&RESERVED2E#
&EP3RE#&RESERVED3E#&EP4RE#&RESERVED4E#&EP5RE#&RESERVED5E#&EP6RE#&RESERVED6E#&EP7RE#<03>"E
&RESERVED7#&CNTRE#@&RESERVED8E#B&ISTRE#D&RESERVED9E#F&FNRE#H&RESERVEDAE#J&DADDRE#L&RESERVEDBE#N&BTABLEE#P&RESERVEDCE#RiUSB_TypeDef:
<01>B<>#&CR#&CFR#&SR#iWWDG_TypeDef<12>
<01>
Z[\]

__STM32F1xx_HAL_H 
X__HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
Y__HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
^__HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
___HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
e__HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
f__HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
<01>
__HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
<01>
__HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
<01>
__HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
<01>
__HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
<01>
__HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
<01>
__HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
<01>
__HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
<01>
__HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
<01>
__HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
<01>
__HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
<01>
__HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
<01>
__HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
<01>IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || ((FREQ) == HAL_TICK_FREQ_1KHZ))|p






../Drivers/STM32F1xx_HAL_Driver/Inc/../Core/Inc/stm32f1xx_hal.h
stm32f1xx_hal_conf.h

<01>
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103C8T6\MDK-ARM<19>
HAL_TICK_FREQ_10HZdHAL_TICK_FREQ_100HZ
HAL_TICK_FREQ_1KHZ
HAL_TICK_FREQ_DEFAULT
iHAL_TickFreqTypeDef<12>
7<03>
j
<00>
uwTickL


<01>
uwTickPrioj


<01>
uwTickFreq1


7<00>
S
uwTicka
uwTickPriou
uwTickFreq
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'__STM32F1XX_H 
5STM32F1 
___STM32F1_CMSIS_VERSION_MAIN (0x04)
`__STM32F1_CMSIS_VERSION_SUB1 (0x03)
a__STM32F1_CMSIS_VERSION_SUB2 (0x03)
b__STM32F1_CMSIS_VERSION_RC (0x00)
c__STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24) |(__STM32F1_CMSIS_VERSION_SUB1 << 16) |(__STM32F1_CMSIS_VERSION_SUB2 << 8 ) |(__STM32F1_CMSIS_VERSION_RC))<03>

<01>
IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
<01>
SET_BIT(REG,BIT) ((REG) |= (BIT))
<01>
CLEAR_BIT(REG,BIT) ((REG) &= ~(BIT))
<01>
READ_BIT(REG,BIT) ((REG) & (BIT))
<01>
CLEAR_REG(REG) ((REG) = (0x0))
<01>
WRITE_REG(REG,VAL) ((REG) = (VAL))
<01>
READ_REG(REG) ((REG))
<01>
MODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
<01>
POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
<01>
ATOMIC_SET_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_CLEAR_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_MODIFY_REG(REG,CLEARMSK,SETMASK) do { uint32_t val; do { val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_SETH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_CLEARH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_MODIFYH_REG(REG,CLEARMSK,SETMASK) do { uint16_t val; do { val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)<03>
<00><00>






../Drivers/CMSIS/Device/ST/STM32F1xx/Include/../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx.h
stm32f103xb.h
stm32f1xx_hal.h

l
../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103C8T6\MDK-ARM<19>

RESETSET
iFlagStatus<12>
<01>
iITStatus<12>
<01>
<19>
DISABLEENABLE
iFunctionalState

<01>
<19>
SUCCESSERROR
iErrorStatus@

<01>

cde

STM32_HAL_LEGACY 
$AES_FLAG_RDERR CRYP_FLAG_RDERR
%AES_FLAG_WRERR CRYP_FLAG_WRERR
&AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
'AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
(AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
0ADC_RESOLUTION12b ADC_RESOLUTION_12B
1ADC_RESOLUTION10b ADC_RESOLUTION_10B
2ADC_RESOLUTION8b ADC_RESOLUTION_8B
3ADC_RESOLUTION6b ADC_RESOLUTION_6B
4OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
5OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
6EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
7EOC_SEQ_CONV ADC_EOC_SEQ_CONV
8EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
9REGULAR_GROUP ADC_REGULAR_GROUP
:INJECTED_GROUP ADC_INJECTED_GROUP
;REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
<AWD_EVENT ADC_AWD_EVENT
=AWD1_EVENT ADC_AWD1_EVENT
>AWD2_EVENT ADC_AWD2_EVENT
?AWD3_EVENT ADC_AWD3_EVENT
@OVR_EVENT ADC_OVR_EVENT
AJQOVF_EVENT ADC_JQOVF_EVENT
BALL_CHANNELS ADC_ALL_CHANNELS
CREGULAR_CHANNELS ADC_REGULAR_CHANNELS
DINJECTED_CHANNELS ADC_INJECTED_CHANNELS
ESYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
FSYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
GADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
HADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
IADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
JADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
KADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
LADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
MADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCO
USART_CLOCK_DISABLED USART_CLOCK_DISABLE
<01>
USART_CLOCK_ENABLED USART_CLOCK_ENABLE
<01>
USARTNACK_ENABLED USART_NACK_ENABLE
<01>
USARTNACK_DISABLED USART_NACK_DISABLE
<01>
CFR_BASE WWDG_CFR_BASE
<01>
CAN_FilterFIFO0 CAN_FILTER_FIFO0
<01>
CAN_FilterFIFO1 CAN_FILTER_FIFO1
<01>
CAN_IT_RQCP0 CAN_IT_TME
<01>
CAN_IT_RQCP1 CAN_IT_TME
<01>
CAN_IT_RQCP2 CAN_IT_TME
<01>
INAK_TIMEOUT CAN_TIMEOUT_VALUE
<01>
SLAK_TIMEOUT CAN_TIMEOUT_VALUE
<01>
CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
<01>
CAN_TXSTATUS_OK ((uint8_t)0x01U)
<01>
CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
<01>
VLAN_TAG ETH_VLAN_TAG
<01>
MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
<01>
MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
<01>
JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
<01>
MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
<01>
MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
<01>
MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
<01>
DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
<01>
ETH_MMCCR 0x00000100U
<01>
ETH_MMCRIR 0x00000104U
<01>
ETH_MMCTIR 0x00000108U
<01>
ETH_MMCRIMR 0x0000010CU
<01>
ETH_MMCTIMR 0x00000110U
<01>
ETH_MMCTGFSCCR 0x0000014CU
<01>
ETH_MMCTGFMSCCR 0x00000150U
<01>
ETH_MMCTGFCR 0x00000168U
<01>
ETH_MMCRFCECR 0x00000194U
<01>
ETH_MMCRFAECR 0x00000198U
<01>
ETH_MMCRGUFCR 0x000001C4U
<01>
ETH_MAC_TXFIFO_FULL 0x02000000U
<01>
ETH_MAC_TXFIFONOT_EMPTY 0x01000000U
<01>
ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U
<01>
ETH_MAC_TXFIFO_IDLE 0x00000000U
<01>
ETH_MAC_TXFIFO_READ 0x00100000U
<01>
ETH_MAC_TXFIFO_WAITING 0x00200000U
<01>
ETH_MAC_TXFIFO_WRITING 0x00300000U
<01>
ETH_MAC_TRANSMISSION_PAUSE 0x00080000U
<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U
<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U
<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U
<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U
<01>
ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U
<01>
ETH_MAC_RXFIFO_EMPTY 0x00000000U
<01>
ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U
<01>
ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U
<01>
ETH_MAC_RXFIFO_FULL 0x00000300U
<01>
ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U
<01>
ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U
<01>
ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U
<01>
ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U
<01>
ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U
<01>
ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U
<01>
ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U
<01>
HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
<01>
DCMI_IT_OVF DCMI_IT_OVR
<01>
DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
<01>
DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
<01>
HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
<01>
HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
<01>
HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
<01>HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
<01>HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
<01>HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
<01>HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
<01>HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
<01>HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
<01>HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
<01>HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
<01>HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
<01>HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
<01>HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
<01>HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
<01>HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
<01>HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
<01>HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
<01>HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
<01>HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
<01>HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
<01>HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
<01>HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
<01>HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
<01>HAL_DBG_LowPowerConfig(Periph,cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
<01>HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
<01>HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
<01>HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
<01>HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
<01>HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
<01>FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
<01>FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
<01>FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
<01>HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
<01>HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
<01>HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
<01>HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
<01>HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
<01>HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
<01>HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
<01>HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
<01>HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus,cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
<01>HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
<01>HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
<01>HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
<01>HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
<01>HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
<01>HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
<01>HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
<01>HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
<01>HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
<01>HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
<01>HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
<01>HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
<01>HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
<01>HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
<01>HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
<01>HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
<01>HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
<01>HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
<01>HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
<01>HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
<01>PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
<01>PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
<01>PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
<01>PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
<01>PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
<01>PWR_MODE_EVENT_FALLING
__HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
<01>
__HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
<01>
__HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
<01>
__HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
<01>__HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
<01>__HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
<01>__HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
<01>__HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
<01>__HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
<01>__HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
<01>__HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
<01>__HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
<01>__HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
<01>__HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
<01>__HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
<01>__HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
<01>__HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
<01>__HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
<01>__HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
<01>__HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
<01>__HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
<01>__HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
<01>
__HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
<01>
__HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
<01>
__HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
<01>
__HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))ti






../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
stm32f1xx_hal_def.h


,../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103C8T6\MDK-ARMB<>(&OscillatorTypej
#&HSEStatej
#&HSEPredivValuej
#&LSEStatej
#&HSIStatej
#&HSICalibrationValuej
#&LSIStatej
#&PLL
#iRCC_OscInitTypeDef<12>
<01>B<>&PeriphClockSelectionj
#&RTCClockSelectionj
#&AdcClockSelectionj
#&UsbClockSelectionj
#iRCC_PeriphCLKInitTypeDef<12>

<01>
stu

__STM32F1xx_HAL_RCC_H 
_RCC_PLLSOURCE_HSI_DIV2 0x00000000U
`RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC
iRCC_OSCILLATORTYPE_NONE 0x00000000U
jRCC_OSCILLATORTYPE_HSE 0x00000001U
kRCC_OSCILLATORTYPE_HSI 0x00000002U
lRCC_OSCILLATORTYPE_LSE 0x00000004U
mRCC_OSCILLATORTYPE_LSI 0x00000008U
uRCC_HSE_OFF 0x00000000U
vRCC_HSE_ON RCC_CR_HSEON
wRCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
RCC_LSE_OFF 0x00000000U
<01>
RCC_LSE_ON RCC_BDCR_LSEON
<01>
RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
<01>
RCC_HSI_OFF 0x00000000U
<01>
RCC_HSI_ON RCC_CR_HSION
<01>
RCC_HSICALIBRATION_DEFAULT 0x10U
<01>
RCC_LSI_OFF 0x00000000U
<01>
RCC_LSI_ON RCC_CSR_LSION
<01>
RCC_PLL_NONE 0x00000000U
<01>
RCC_PLL_OFF 0x00000001U
<01>
RCC_PLL_ON 0x00000002U
<01>
RCC_CLOCKTYPE_SYSCLK 0x00000001U
<01>
RCC_CLOCKTYPE_HCLK 0x00000002U
<01>
RCC_CLOCKTYPE_PCLK1 0x00000004U
<01>
RCC_CLOCKTYPE_PCLK2 0x00000008U
<01>
RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
<01>
RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
<01>
RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
<01>
RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
<01>
RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
<01>
RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
<01>
RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
<01>
RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
<01>
RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
<01>
RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
<01>
RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
<01>
RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
<01>
RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
<01>
RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
<01>
RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
<01>

RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
<01>
RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
<01>
RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
<01>
CR_REG_INDEX ((uint8_t)1)
<01>
BDCR_REG_INDEX ((uint8_t)2)
<01>
CSR_REG_INDEX ((uint8_t)3)
<01>
RCC_FLAG_MASK ((uint8_t)0x1F)
<01>
__HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
<01>
__HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
<01>
__HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
<01>
__HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
<01>
IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || ((__SOURCE__) == RCC_PLLSOURCE_HSE))
<01>
IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
<01>
IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || ((__HSE__) == RCC_HSE_BYPASS))
<01>
IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS))
<01>
IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
<01>
IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
<01>
IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
<01>
IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON))
<01>
IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
<01>
IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
<01>
IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
<01>
IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512))
<01>
IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || ((__PCLK__) == RCC_HCLK_DIV16))
<01>
IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
<01>
IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
<01>
IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))<00><00>






../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h
stm32f1xx_hal_def.h
stm32f1xx_hal_rcc_ex.h


<01>
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103C8T6\MDK-ARMB<>&PLLStatej
#&PLLSourcej
#&PLLMULj
#iRCC_PLLInitTypeDef<12>
;B<>&ClockTypej
#&SYSCLKSourcej
#&AHBCLKDividerj
#&APB1CLKDividerj
#&APB2CLKDividerj
#iRCC_ClkInitTypeDef(

P
wxy

STM32F1xx_HAL_GPIO_EX_H 
6AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0
7AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1
8AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2
9AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3
:AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4
;AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5
<AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6
=AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7
>AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8
?AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9
@AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10
AAFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11
BAFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12
CAFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13
DAFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14
EAFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15
GIS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || ((__PIN__) == AFIO_EVENTOUT_PIN_1) || ((__PIN__) == AFIO_EVENTOUT_PIN_2) || ((__PIN__) == AFIO_EVENTOUT_PIN_3) || ((__PIN__) == AFIO_EVENTOUT_PIN_4) || ((__PIN__) == AFIO_EVENTOUT_PIN_5) || ((__PIN__) == AFIO_EVENTOUT_PIN_6) || ((__PIN__) == AFIO_EVENTOUT_PIN_7) || ((__PIN__) == AFIO_EVENTOUT_PIN_8) || ((__PIN__) == AFIO_EVENTOUT_PIN_9) || ((__PIN__) == AFIO_EVENTOUT_PIN_10) || ((__PIN__) == AFIO_EVENTOUT_PIN_11) || ((__PIN__) == AFIO_EVENTOUT_PIN_12) || ((__PIN__) == AFIO_EVENTOUT_PIN_13) || ((__PIN__) == AFIO_EVENTOUT_PIN_14) || ((__PIN__) == AFIO_EVENTOUT_PIN_15))
_AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA
`AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB
aAFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC
bAFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD
cAFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE
eIS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || ((__PORT__) == AFIO_EVENTOUT_PORT_B) || ((__PORT__) == AFIO_EVENTOUT_PORT_C) || ((__PORT__) == AFIO_EVENTOUT_PORT_D) || ((__PORT__) == AFIO_EVENTOUT_PORT_E))
|__HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP)
<01>
__HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP)
<01>
__HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP)
<01>
__HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP)
<01>
__HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP)
<01>
__HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP)
<01>
__HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP)
<01>
__HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP)
<01>
__HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
<01>
__HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTI

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Input Comments:p24e0-3Component: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide mainsystem.oComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]ArmCC --cpp --split_sections --debug -c -otemplate\mainsystem.o --depend=template\mainsystem.d --cpu=Cortex-M3 --apcs=interwork -O3 --diag_suppress=9931 -I../Core/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I.\bsp_System -I.\bsp_Device -I.\RTE\_template -ID:\SOFTWARE\Keil_v5\ARM\PACK\ARM\CMSIS\5.9.0\CMSIS\Core\Include -ID:\SOFTWARE\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\1.0.5\Device\Include -D__UVISION_VERSION=537 -D_RTE_ -DSTM32F10X_MD -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F103xB --omf_browse=template\mainsystem.crf bsp_System\MainSystem.cpp<00>+
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d-dnd?<00><02><00><02>.ARM.attributes.strtab.shstrtab.rel.debug_pubnames.rel.debug_frame.rel.debug_line.rel.debug_info.rel.init_array.rel.ARM.exidx.reli.__sti___14_MainSystem_cpp_com.symtab.comment.arm_vfe_header__ARM_grp..debug_abbrev.group.2_8M0000_tpM4SoO0Naf_000000__ARM_grp.MainSystem.cpp.2_Y01000_QnT4QnzaEbe_300000__ARM_grp.bsp_PrintArt.h.2_csn100_ogt3gUTKPxb_f10000__ARM_grp.usart.h.2_VXJ200_DSK7FlQHY9a_X10000__ARM_grp.stdlib.h.2_kS1000_zG_qQ8KJUMb_e00000__ARM_grp.string.h.2_NN2000_y6vTOAkyuK9_n00000__ARM_grp.stdarg.h.2_A$0000_GVPHKELl1X9_300000__ARM_grp.gpio.h.2_QR0000_sug4ycqfM8b_300000__ARM_grp.main.h.2_cT0000_IQqIIJdOp$9_300000__ARM_grp.stm32f1xx_hal_conf.h.2_0b2000_7YjWqhbOP3a_300000__ARM_grp.stm32f1xx_hal_uart.h.2_oJo100_0fizOk53NB4_V00000__ARM_grp.stm32f1xx_hal_pwr.h.2_sK2000_NB$h5MBIIPc_800000__ARM_grp.stm32f1xx_hal_flash.h.2_0b2000_G_A$PUBup$9_c00000__ARM_grp.stm32f1xx_hal_flash_ex.h.2_Aq3000_TQOCyNXlt82_i00000__ARM_grp.stm32f1xx_hal_cortex.h.2_kg1000_OIG$8M02V85_300000__ARM_grp.stm32f1xx_hal_dma.h.2_oKl100_TWYXwMNta7e_C00000__ARM_grp.stm32f1xx_hal_dma_ex.h.2_A12000_fSRHYfnJkq1_300000__ARM_grp.stm32f1xx_hal_exti.h.2_kn2000_GP0vjNkvZ$6_b00000__ARM_grp.stm32f1xx_hal_gpio.h.2_ot2000_ZvNOsQJxel6_a00000__ARM_grp.stm32f1xx_hal_gpio_ex.h.2_4Q3000__k9G3pWg__5_300000__ARM_grp.stm32f1xx_hal_rcc.h.2_kfc000_wdQsCUwBI45_e00000__ARM_grp.stm32f1xx_hal_rcc_ex.h.2_sLa000_Xf8pCVEpdU2_t00000__ARM_grp.stm32f1xx_hal_def.h.2_wk1000_TUtaPF_WF02_300000__ARM_grp.stddef.h.2_0Y0000_H5ygNXOhgn0_300000__ARM_grp.stm32_hal_legacy.h.2_c2P000_QcaucrdSgp4_300000__ARM_grp.stm32f1xx.h.2_8S1000_3nxZf72rIh6_300000__ARM_grp.stm32f1xx_hal.h.2_LB3000_00oK6BIW_R5_h00000__ARM_grp.stm32f103xb.h.2_sqA200_h6oPZC$r0Aa_k00000__ARM_grp.system_stm32f1xx.h.2_uo2000_VwZCrwloHs3_h00000__ARM_grp.core_cm3.h.2_P1U200_cRElSsEvaO4_b40000__ARM_grp.cmsis_compiler.h.2_gV0000_J7bVfNRUqQ6_300000__ARM_grp.cmsis_armcc.h.2_Mu2000_lAHUQCxB2ad_O00000__ARM_grp.cmsis_version.h.2_8X0000_1TzyqZ7N_t6_300000__ARM_grp.CallBack.h.2_AR0000__vKttCL_Me9_300000__ARM_grp.vartable.h.2_QW0000_o7_ZAkLB3A0_300000__ARM_grp.stdio.h.2_Ml1000_U_UtJvXZoKb_700000__ARM_grp.varint.h.2_Mw1000_6a8aHY6ey6d_e00000__ARM_grp.stdint.h.2_Ia1000_2R4Eswy5qxe_300000__ARM_grp.User.h.2_MW0000_7dELeg0rKMf_300000.debug_abbrev__ARM_asm.debug_abbrev.1.debug_macinfo.debug_loc.bssi.MainSystemi.MainInit.rrx_text.revsh_text.rev16_textLib$$Request$$cpplibLib$$Request$$armlibhuart1_ZN18bsp_PrintArt_STM32C1EP20__UART_HandleTypeDef__ARM_grp..debug_pubnames$usart.h$.2_VXJ200_DSK7FlQHY9a_X10000__ARM_grp..debug_pubnames$system_stm32f1xx.h$.2_uo2000_VwZCrwloHs3_h00000__ARM_grp..debug_pubnames$string.h$.2_NN2000_y6vTOAkyuK9_n00000__ARM_grp..debug_pubnames$stm32f1xx_hal.h$.2_LB3000_00oK6BIW_R5_h00000__ARM_grp..debug_pubnames$core_cm3.h$.2_P1U200_cRElSsEvaO4_b40000__ARM_grp..debug_macinfo$vartable.h$.2_QW0000_o7_ZAkLB3A0_300000__ARM_grp..debug_macinfo$varint.h$.2_Mw1000_6a8aHY6ey6d_e00000__ARM_grp..debug_macinfo$usart.h$.2_VXJ200_DSK7FlQHY9a_X10000__ARM_grp..debug_macinfo$system_stm32f1xx.h$.2_uo2000_VwZCrwloHs3_h00000__ARM_grp..debug_macinfo$string.h$.2_NN2000_y6vTOAkyuK9_n00000__ARM_grp..debug_macinfo$stm32f1xx_hal_uart.h$.2_oJo100_0fizOk53NB4_V00000__ARM_grp..debug_macinfo$stm32f1xx_hal_rcc_ex.h$.2_sLa000_Xf8pCVEpdU2_t00000__ARM_grp..debug_macinfo$stm32f1xx_hal_rcc.h$.2_kfc000_wdQsCUwBI45_e00000__ARM_grp..debug_macinfo$stm32f1xx_hal_pwr.h$.2_sK2000_NB$h5MBIIPc_800000__ARM_grp..debug_macinfo$stm32f1xx_hal_gpio_ex.h$.2_4Q3000__k9G3pWg__5_300000__ARM_grp..debug_macinfo$stm32f1xx_hal_gpio.h$.2_ot2000_ZvNOsQJxel6_a00000__AR
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