MicrochipFor32/MX_FastSet/T439/MDK-ARM/template/callback.o

ELF



(
<00>m4(<00><00>@<40>pG<70><47>pGO<47>0pG<70>
bsp_System\\Callback.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]D:\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM__asm___12_Callback_cpp___Z7__REV16jX>







..\Drivers\CMSIS\Include\cmsis_armcc.h
<03>


<01>
bsp_System\\Callback.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]D:\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM__asm___12_Callback_cpp___Z7__REVSHsX>







..\Drivers\CMSIS\Include\cmsis_armcc.h
<03>


<01>
bsp_System\\Callback.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]D:\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM__asm___12_Callback_cpp___Z5__RRXjX>







..\Drivers\CMSIS\Include\cmsis_armcc.h
<03>
&

`<00><><EFBFBD><EFBFBD>armcc+
|

	
<07><07><07><07><07><07><07><07><08><08><08><08><08><08><08><08>`<00><><EFBFBD><EFBFBD>armcc+
|

	
<07><07><07><07><07><07><07><07><08><08><08><08><08><08><08><08>`<00><><EFBFBD><EFBFBD>armcc+
|

	
<07><07><07><07><07><07><07><07><08><08><08><08><08><08><08><08><00>bsp_System\Callback.cppComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM8.






bsp_System\Callback.cpp


__DATE__ "Apr 24 2023"
__TIME__ "02:35:03"
__STDC__ 1
__cplusplus 199711L
_BOOL 1
__ARRAY_OPERATORS 1
__IMPLICIT_INCLUDE 1
__RTTI 1
__EDG_RUNTIME_USES_NAMESPACES 1
__EDG_IA64_ABI 1
__EDG_IA64_ABI_VARIANT_CTORS_AND_DTORS_RETURN_THIS 1
__EDG_IA64_ABI_USE_INT_STATIC_INIT_GUARD 1
__EDG_TYPE_TRAITS_ENABLED 1
__EDG__ 1
__EDG_VERSION__ 407
__EDG_SIZE_TYPE__ unsigned int
__EDG_PTRDIFF_TYPE__ int
__sizeof_int 4
__sizeof_long 4
__sizeof_ptr 4
__ARMCC_VERSION 5060960
__TARGET_CPU_CORTEX_M4_FP_SP 1
__TARGET_FPU_VFPV4_SP_D16 1
__UVISION_VERSION 537
_RTE_ 1
STM32F429xx 1
_RTE_ 1
USE_HAL_DRIVER 1
STM32F429xx 1
__CC_ARM 1
__arm 1
__arm__ 1
__TARGET_ARCH_7E_M 1
__TARGET_ARCH_ARM 0
__TARGET_ARCH_THUMB 4
__TARGET_ARCH_A64 0
__TARGET_ARCH_AARCH32 1
__TARGET_PROFILE_M 1
__TARGET_FEATURE_HALFWORD 1
__TARGET_FEATURE_THUMB 1
__TARGET_FEATURE_MULTIPLY 1
__TARGET_FEATURE_DSPMUL 1
__TARGET_FEATURE_DOUBLEWORD 1
__TARGET_FEATURE_DIVIDE 1
__TARGET_FEATURE_UNALIGNED 1
__TARGET_FEATURE_CLZ 1
__TARGET_FEATURE_DMB 1
__TARGET_FPU_VFPV4 1
__TARGET_FPU_VFP 1
__TARGET_FPU_VFP_SINGLE 1
__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 16
__APCS_INTERWORK 1
__FP_FAST_FMAF 1
__thumb 1
__thumb__ 1
__t32__ 1
__OPTIMISE_SPACE 1
__OPT_SMALL_ASSERT 1
__OPTIMISE_LEVEL 3



%

.




'__DEBUG__ 
+_STM32_HAL_ 
.BPS_CONFIG_VERSION "1.0.0"
3EQ_CheckBox 0
7EQ_NumBox 0
>EQ_BITERABI 0x000
BEQ_BITERABIS 0x00
Itext(format,__VA_ARGS__...) com.print(format, ## __VA_ARGS__)4)






bsp_System\User.h


<01>bsp_System\User.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM


__stdint_h 
__ARMCLIB_VERSION 5060044
__INT64 __int64
__INT64_C_SUFFIX__ ll
__PASTE2(x,y) x ## y
__PASTE(x,y) __PASTE2(x, y)
__INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))
__UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))
__LONGLONG long long
#__STDINT_DECLS %__CLIBNS
)__CLIBNS std::<02>__INT64<02>__LONGLONGXM






D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h


D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]
unsigned charunsigned shortunsigned intunsigned long long
signed charshortintlong long<00>
<01>stdiint8_t<12>
8 iint16_t<12>
9 iint32_t<12>
: iint64_t<12>
; iuint8_t<12>
> iuint16_t<12>
? iuint32_t<12>
@ iuint64_t<12>
A iint_least8_t<12>
G iint_least16_t<12>
H iint_least32_t<12>
I iint_least64_t<12>
J iuint_least8_t<12>
M iuint_least16_t<12>
N iuint_least32_t<12>
O iuint_least64_t<12>
P iint_fast8_t<12>
U iint_fast16_t<12>
V iint_fast32_t<12>
W iint_fast64_t<12>
X iuint_fast8_t<12>
[ iuint_fast16_t<12>
\ iuint_fast32_t<12>
] iuint_fast64_t<12>
^ iintptr_t<12>
e iuintptr_t<12>
f iintmax_t<12>
j!iuintmax_t<12>
k!

#
>P8(x) ((u8*)(&(x)))
?Pn8(x,y) (((u8*)(&(x)))[y])
@P16(x) ((u16*)(&(x)))
APn16(x,y) (((u16*)(&(x)))[y])
BP32(x) ((u32*)(&(x)))
CPn32(x,y) (((u32*)(&(x)))[y])
EDelLb(x) (x & (x - 1))
FqDelLb(x) (x=(x & (x - 1)))
HtoBool(x) (x!=0)
IuBit(x,y) (x&(1<<y))
JtBit(x,y) (toBool(uBit(x,y)))
LsBit(x,y) (x|(1<<y))
MrBit(x,y) (x&(~(1<<y)))
NmBit(x,y,z) ((z)?sBit(x,y):rBit(x,y))
PLoopAdd(var,min,step,max) (var<max?var+step:min)
QqLoopAdd(var,min,step,max) (var=var<max?var+step:min)
RLoopDec(var,min,step,max) (var>min?var-step:max)
SqLoopDec(var,min,step,max) (var=var>min?var-step:max)pe






bsp_System\D:\SOFTWARE\Ke

<01>__get_FPSCRj
z__resultj

r__regfpscrj

PS<>

<01>__set_FPSCR3j
fpscrr__regfpscrj

P
345

__CMSIS_COMPILER_H "<00><00>






../Drivers/CMSIS/Include/D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\cmsis_compiler.h
stdint.hcmsis_armcc.h


<01>../Drivers/CMSIS/Include/cmsis_compiler.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM
789

 ARM_MPU_ARMV7_H 
"ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
#ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
$ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
%ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
&ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
'ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
(ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
)ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
*ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
+ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
,ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
-ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
.ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
/ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
0ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
1ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
2ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
3ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
4ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
5ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
6ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
7ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
8ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
9ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
:ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
;ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
<ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
=ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
?ARM_MPU_AP_NONE 0U
@ARM_MPU_AP_PRIV 1U
AARM_MPU_AP_URO 2U
BARM_MPU_AP_FULL 3U
CARM_MPU_AP_PRO 5U
DARM_MPU_AP_RO 6U
KARM_MPU_RBAR(Region,BaseAddress) (((BaseAddress) & MPU_RBAR_ADDR_Msk) | ((Region) & MPU_RBAR_REGION_Msk) | (MPU_RBAR_VALID_Msk))
XARM_MPU_ACCESS_(TypeExtField,IsShareable,IsCacheable,IsBufferable) ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
gARM_MPU_RASR_EX(DisableExec,AccessPermission,AccessAttributes,SubRegionDisable,Size) ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
xARM_MPU_RASR(DisableExec,AccessPermission,TypeExtField,IsShareable,IsCacheable,IsBufferable,SubRegionDisable,Size) ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
<01>
ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
<01>
ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
<01>
ARM_MPU_ACCESS_NORMAL(OuterCp,InnerCp,IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
<01>
ARM_MPU_CACHEP_NOCACHE 0U
<01>
ARM_MPU_CACHEP_WB_WRA 1U
<01>
ARM_MPU_CACHEP_WT_NWA 2U
<01>
ARM_MPU_CACHEP_WB_NWA 3UH<






../Drivers/CMSIS/Include/mpu_armv7.h


\../Drivers/CMSIS/Include/mpu_armv7.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARMB<>
&RBARj
#&RASRj
#iARM_MPU_Region_t<12>
<01>
S<>
<01>
ARM_MPU_Enable3j
MPU_ControlS<>
<01>
ARM_MPU_DisableS<>
<01>
ARM_MPU_ClrRegion3j
rnrS<>
<01>
ARM_MPU_SetRegion3j
rbar3j
rasrS<>
<01>
ARM_MPU_SetRegionEx3j
rnr3j
rbar3j
rasrS<>
<01>
orderedCpy3
dst3src3j
lenuij
<00>
j
0j
0S<>
<01>ARM_MPU_Load3Ytable3j
cnt<00>
rowWordSize<12>0U
;<=>

 __CORE_CM4_H_GENERIC "?
B__CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
C__CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
D__CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | __CM4_CMSIS_VERSION_SUB )
G__CORTEX_M (4U)
O__FPU_USED 1U<03>

<01>
__CORE_CM4_H_DEPENDANT 
<01>
__I volatile
<01>
__O volatile
<01>
__IO volatile
<01>
__IM volatile const
<01>
__OM volatile
<01>
__IOM volatile
<01>APSR_N_Pos 31U
<01>APSR_N_Msk (1UL << APSR_N_Pos)
<01>APSR_Z_Pos 30U
<01>APSR_Z_Msk (1UL << APSR_Z_Pos)
<01>APSR_C_Pos 29U
<01>APSR_C_Msk (1UL << APSR_C_Pos)
<01>APSR_V_Pos 28U
<01>APSR_V_Msk (1UL << APSR_V_Pos)
<01>APSR_Q_Pos 27U
<01>APSR_Q_Msk (1UL << APSR_Q_Pos)
<01>APSR_GE_Pos 16U
<01>APSR_GE_Msk (0xFUL << APSR_GE_Pos)
<01>IPSR_ISR_Pos 0U
<01>IPSR_ISR_Msk (0x1FFUL )
<01>xPSR_N_Pos 31U
<01>xPSR_N_Msk (1UL << xPSR_N_Pos)
<01>xPSR_Z_Pos 30U
<01>xPSR_Z_Msk (1UL << xPSR_Z_Pos)
<01>xPSR_C_Pos 29U
<01>xPSR_C_Msk (1UL << xPSR_C_Pos)
<01>xPSR_V_Pos 28U
<01>xPSR_V_Msk (1UL << xPSR_V_Pos)
<01>xPSR_Q_Pos 27U
<01>xPSR_Q_Msk (1UL << xPSR_Q_Pos)
<01>xPSR_ICI_IT_2_Pos 25U
<01>xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)
<01>xPSR_T_Pos 24U
<01>xPSR_T_Msk (1UL << xPSR_T_Pos)
<01>xPSR_GE_Pos 16U
<01>xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
<01>xPSR_ICI_IT_1_Pos 10U
<01>xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)
<01>xPSR_ISR_Pos 0U
<01>xPSR_ISR_Msk (0x1FFUL )
<01>CONTROL_FPCA_Pos 2U
<01>CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
<01>CONTROL_SPSEL_Pos 1U
<01>CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
<01>CONTROL_nPRIV_Pos 0U
<01>CONTROL_nPRIV_Msk (1UL )
<01>NVIC_STIR_INTID_Pos 0U
<01>NVIC_STIR_INTID_Msk (0x1FFUL )
<01>SCB_CPUID_IMPLEMENTER_Pos 24U
<01>SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
<01>SCB_CPUID_VARIANT_Pos 20U
<01>SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
<01>SCB_CPUID_ARCHITECTURE_Pos 16U
<01>SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
<01>SCB_CPUID_PARTNO_Pos 4U
<01>SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
<01>SCB_CPUID_REVISION_Pos 0U
<01>SCB_CPUID_REVISION_Msk (0xFUL )
<01>SCB_ICSR_NMIPENDSET_Pos 31U
<01>SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
<01>SCB_ICSR_PENDSVSET_Pos 28U
<01>SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
<01>SCB_ICSR_PENDSVCLR_Pos 27U
<01>SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
<01>SCB_ICSR_PENDSTSET_Pos 26U
<01>SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
<01>SCB_ICSR_PENDSTCLR_Pos 25U
<01>SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
<01>SCB_ICSR_ISRPREEMPT_Pos 23U
<01>SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
<01>SCB_ICSR_ISRPENDING_Pos 22U
<01>SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
<01>SCB_ICSR_VECTPENDING_Pos 12U
<01>SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
<01>SCB_ICSR_RETTOBASE_Pos 11U
<01>SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
<01>SCB_ICSR_VECTACTIVE_Pos 0U
<01>SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
<01>SCB_VTOR_TBLOFF_Pos 7U
<01>SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
<01>SCB_AIRCR_VECTKEY_Pos 16U
<01>SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
<01>SCB_AIRCR_VECTKEYSTAT_Pos 16U
<01>SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
<01>SCB_AIRCR_ENDIANESS_Pos 15U
<01>SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
<01>SCB_AIRCR_PRIGROUP_Pos 8U
<01>SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
<01>SCB_AIRCR_SYSRESETREQ_Pos 2U
<01>SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
<01>SCB_AIRCR_VECTCLRACTIVE_Pos 1U
<01>SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
<01>SCB_AIRCR_VECTRESET_Pos 0U
<01>SCB_AIRCR_VECTRESET_Msk (1UL )
<01>SCB_SCR_SEVONPEND_Pos 4U
<01>SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
<01>SCB_SCR_SLEEPDEEP_Pos 2U
<01>SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
<01>SCB_SCR_SLEEPONEXIT_Pos 1U
<01>SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
<01>SCB_CCR_STKALIGN_Pos 9U
<01>SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
MPU_RASR_AP_Pos 24U
<01>
MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
<01>
MPU_RASR_TEX_Pos 19U
<01>
MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
<01>
MPU_RASR_S_Pos 18U
<01>
MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
<01>
MPU_RASR_C_Pos 17U
<01>
MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
<01>
MPU_RASR_B_Pos 16U
<01>
MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
<01>
MPU_RASR_SRD_Pos 8U
<01>
MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
<01>
MPU_RASR_SIZE_Pos 1U
<01>
MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
<01>
MPU_RASR_ENABLE_Pos 0U
<01>
MPU_RASR_ENABLE_Msk (1UL )
<01>
FPU_FPCCR_ASPEN_Pos 31U
<01>
FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
<01>
FPU_FPCCR_LSPEN_Pos 30U
<01>
FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
<01>
FPU_FPCCR_MONRDY_Pos 8U
<01>
FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
<01>
FPU_FPCCR_BFRDY_Pos 6U
<01>
FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
<01>
FPU_FPCCR_MMRDY_Pos 5U
<01>
FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
<01>
FPU_FPCCR_HFRDY_Pos 4U
<01>
FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
<01>
FPU_FPCCR_THREAD_Pos 3U
<01>
FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
<01>
FPU_FPCCR_USER_Pos 1U
<01>
FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
<01>
FPU_FPCCR_LSPACT_Pos 0U
<01>
FPU_FPCCR_LSPACT_Msk (1UL )
<01>
FPU_FPCAR_ADDRESS_Pos 3U
<01>
FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
<01>
FPU_FPDSCR_AHP_Pos 26U
<01>
FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
<01>
FPU_FPDSCR_DN_Pos 25U
<01>
FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
<01>
FPU_FPDSCR_FZ_Pos 24U
<01>
FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
<01>
FPU_FPDSCR_RMode_Pos 22U
<01>
FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
<01>
FPU_MVFR0_FP_rounding_modes_Pos 28U
<01>
FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
<01>
FPU_MVFR0_Short_vectors_Pos 24U
<01>
FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
<01>
FPU_MVFR0_Square_root_Pos 20U
<01>
FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
<01>
FPU_MVFR0_Divide_Pos 16U
<01>
FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
<01>
FPU_MVFR0_FP_excep_trapping_Pos 12U
<01>
FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
<01>
FPU_MVFR0_Double_precision_Pos 8U
<01>
FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
<01>
FPU_MVFR0_Single_precision_Pos 4U
<01>
FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
<01>
FPU_MVFR0_A_SIMD_registers_Pos 0U
<01>
FPU_MVFR0_A_SIMD_registers_Msk (0xFUL )
<01>
FPU_MVFR1_FP_fused_MAC_Pos 28U
<01>
FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
<01>
FPU_MVFR1_FP_HPFP_Pos 24U
<01>
FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
<01>
FPU_MVFR1_D_NaN_mode_Pos 4U
<01>
FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
<01>FPU_MVFR1_FtZ_mode_Pos 0U
<01>FPU_MVFR1_FtZ_mode_Msk (0xFUL )
<01>CoreDebug_DHCSR_DBGKEY_Pos 16U
<01>CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
<01>CoreDebug_DHCSR_S_RESET_ST_Pos 25U
<01>CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
<01>CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
<01>CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
<01>CoreDebug_DHCSR_S_LOCKUP_Pos 19U
<01>CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
<01>CoreDebug_DHCSR_S_SLEEP_Pos 18U
<01>CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
<01>CoreDebug_DHCSR_S_HALT_Pos 17U
<01>CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
<01>CoreDebug_DHCSR_S_REGRDY_Pos 16U
<01>CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
<01>CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
<01>CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
<01>CoreDebug_DHCSR_C_MASKINTS_Pos 3U
<01>CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
<01>CoreDebug_DHCSR_C_STEP_Pos 2U
<01>CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
<01>CoreDebug_DHCSR_C_HALT_Pos 1U
<01>CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
<01>CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
<01>CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL )
<01>CoreDebug_DCRSR_REGWnR_Pos 16U
<01>CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
<01>CoreDebug_DCRSR_REGSEL_Pos 0U
<01>CoreDebug_DCRSR_REGSEL_Msk (0x1FUL )
<01>CoreDebug_DEMCR_TRCENA_Pos 24U
<01>CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
<01>CoreDebug_DEMCR_MON_REQ_Pos 19U
<01>CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
<01>CoreDebug_DEMCR_MON_STEP_Pos 18U
<01>CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
<01>CoreDebug_DEMCR_MON_PEND_Pos 17U
<01>CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
<01>CoreDebug_DEMCR_MON_EN_Pos 16U
<01>CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
<01>CoreDebug_DEMCR_VC_HARDERR_Pos 10U
<01>CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
<01>CoreDebug_DEMCR_VC_INTERR_Pos 9U
<01>CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
<01>CoreDebug_DEMCR_VC_BUSERR_Pos 8U
<01>CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
<01>CoreDebug_DEMCR_VC_STATERR_Pos 7U
<01>CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
<01>CoreDebug_DEMCR_VC_CHKERR_Pos 6U
<01>CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
<01>CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
<01>CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
<01>CoreDebug_DEMCR_VC_MMERR_Pos 4U
<01>CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
<01>CoreDebug_DEMCR_VC_CORERESET_Pos 0U
<01>CoreDebug_DEMCR_VC_CORERESET_Msk (1UL )
<01>_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
<01>_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
<01>SCS_BASE (0xE000E000UL)
<01>ITM_BASE (0xE0000000UL)
<01>DWT_BASE (0xE0001000UL)
<01>TPI_BASE (0xE0040000UL)
<01>CoreDebug_BASE (0xE000EDF0UL)
<01>SysTick_BASE (SCS_BASE + 0x0010UL)
<01>NVIC_BASE (SCS_BASE + 0x0100UL)
<01>SCB_BASE (SCS_BASE + 0x0D00UL)
<01>SCnSCB ((SCnSCB_Type *) SCS_BASE )
<01>SCB ((SCB_Type *) SCB_BASE )
<01>SysTick ((SysTick_Type *) SysTick_BASE )
<01>NVIC ((NVIC_Type *) NVIC_BASE )
<01>ITM ((ITM_Type *) ITM_BASE )
<01>DWT ((DWT_Type *) DWT_BASE )
<01>TPI ((TPI_Type *) TPI_BASE )
<01>CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
<01>MPU_BASE (SCS_BASE + 0x0D90UL)
<01>MPU ((MPU_Type *) MPU_BASE )
<01>FPU_BASE (SCS_BASE + 0x0F30UL)
<01>FPU ((FPU_Type *) FPU_BASE )
<01>NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
<01>NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
<01>NVIC_EnableIRQ __NVIC_EnableIRQ
<01>NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
<01>NVIC_DisableIRQ __NVIC_DisableIRQ
<01>NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
<01>NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
<01>NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

<12>

&PFRA#@&DFR<12>#H&ADR<12>#L<03>
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&RESERVED3#<23>&IWRj#<23>&IRR<12>#<23>&IMCRj#<23><03>j

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&RESERVED2<12>	#L&COMP3j#P&MASK3j#T&FUNCTION3j#XiDWT_Typet
<01>B<><17>&SSPSR<12>#&CSPSRj#<03>j


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<01>&RESERVED3<12>
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&RESERVED7<12>#<23>&DEVID<12>#<23>&DEVTYPE<12>#<23>iTPI_Type<12>	
<01>B<>,&TYPE<12>#&CTRLj#&RNRj#&RBARj#&RASRj#&RBAR_A1j#&RASR_A1j#&RBAR_A2j#&RASR_A2j# &RBAR_A3j#$&RASR_A3j#(iMPU_Type<12>
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<01>
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<01><03>
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<00>
ITM_RxBufferC


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<01>__NVIC_SetPriorityGrouping3j
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<01>
__NVIC_GetPriorityGroupingj
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<01>
__NVIC_EnableIRQ3IRQnR<>
<01>
__NVIC_GetEnableIRQj
3IRQnz__resultj

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<01>
__NVIC_DisableIRQ3IRQnR<>
<01>
__NVIC_GetPendingIRQj
3IRQnz__resultj

S<>
<01>
__NVIC_SetPendingIRQ3IRQnS<>
<01>
__NVIC_ClearPendingIRQ3IRQnR<>
<01>__NVIC_GetActivej
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<01>NVIC_DecodePriority3j
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__SYSTEM_STM32F4XX_H `W






../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h


4
../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM<00>
SystemCoreClockj


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AHBPrescTable<12>

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APBPrescTable


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<00>SystemCoreClock
AHBPrescTable
APBPrescTable
EFG

"__STM32F429xx_H 
/__CM4_REV 0x0001U
0__MPU_PRESENT 1U
1__NVIC_PRIO_BITS 4U
2__Vendor_SysTickConfig 0U
3__FPU_PRESENT 1U<03>
<03>
<03>

<01>FLASH_BASE 0x08000000UL
<01>CCMDATARAM_BASE 0x10000000UL
<01>SRAM1_BASE 0x20000000UL
<01>SRAM2_BASE 0x2001C000UL
<01>SRAM3_BASE 0x20020000UL
<01>PERIPH_BASE 0x40000000UL
<01>BKPSRAM_BASE 0x40024000UL
<01>FMC_R_BASE 0xA0000000UL
<01>SRAM1_BB_BASE 0x22000000UL
<01>SRAM2_BB_BASE 0x22380000UL
<01>SRAM3_BB_BASE 0x22400000UL
<01>PERIPH_BB_BASE 0x42000000UL
<01>BKPSRAM_BB_BASE 0x42480000UL
<01>FLASH_END 0x081FFFFFUL
<01>FLASH_OTP_BASE 0x1FFF7800UL
<01>FLASH_OTP_END 0x1FFF7A0FUL
<01>CCMDATARAM_END 0x1000FFFFUL
<01>SRAM_BASE SRAM1_BASE
<01>SRAM_BB_BASE SRAM1_BB_BASE
<01>APB1PERIPH_BASE PERIPH_BASE
<01>APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
<01>AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
<01>AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
<01>TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
<01>TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
<01>TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
<01>TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
<01>TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
<01>TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
<01>TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
<01>TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
<01>TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
<01>RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
<01>WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
<01>IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
<01>I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
<01>SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
<01>SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
<01>I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
<01>USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
<01>USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
<01>UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
<01>UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
<01>I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
<01>I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
<01>I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
<01>CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
<01>CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
<01>PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
<01>DAC_BASE (APB1PERIPH_BAS
ETH ((ETH_TypeDef *) ETH_BASE)
<01>
DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
<01>
DCMI ((DCMI_TypeDef *) DCMI_BASE)
<01>
RNG ((RNG_TypeDef *) RNG_BASE)
<01>
FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
<01>
FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
<01>
FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
<01>
FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
<01>
FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
<01>
DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
<01>
USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
<01>
USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
<01>
LSI_STARTUP_TIME 40U
<01>
ADC_MULTIMODE_SUPPORT 
<01>
ADC_SR_AWD_Pos (0U)
<01>
ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
<01>
ADC_SR_AWD ADC_SR_AWD_Msk
<01>
ADC_SR_EOC_Pos (1U)
<01>
ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
<01>
ADC_SR_EOC ADC_SR_EOC_Msk
<01>
ADC_SR_JEOC_Pos (2U)
<01>
ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
<01>
ADC_SR_JEOC ADC_SR_JEOC_Msk
<01>
ADC_SR_JSTRT_Pos (3U)
<01>
ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
<01>
ADC_SR_JSTRT ADC_SR_JSTRT_Msk
<01>
ADC_SR_STRT_Pos (4U)
<01>
ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
<01>
ADC_SR_STRT ADC_SR_STRT_Msk
<01>
ADC_SR_OVR_Pos (5U)
<01>
ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
<01>
ADC_SR_OVR ADC_SR_OVR_Msk
<01>
ADC_CR1_AWDCH_Pos (0U)
<01>
ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
<01>
ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
<01>
ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
<01>
ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
<01>
ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
<01>
ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
<01>
ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
<01>
ADC_CR1_EOCIE_Pos (5U)
<01>
ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
<01>
ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
<01>
ADC_CR1_AWDIE_Pos (6U)
<01>
ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
<01>
ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
<01>
ADC_CR1_JEOCIE_Pos (7U)
<01>
ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
<01>
ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
<01>
ADC_CR1_SCAN_Pos (8U)
<01>
ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
<01>
ADC_CR1_SCAN ADC_CR1_SCAN_Msk
<01>
ADC_CR1_AWDSGL_Pos (9U)
<01>
ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
<01>
ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
<01>
ADC_CR1_JAUTO_Pos (10U)
<01>
ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
<01>
ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
<01>
ADC_CR1_DISCEN_Pos (11U)
<01>
ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
<01>
ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
<01>
ADC_CR1_JDISCEN_Pos (12U)
<01>
ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
<01>
ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
<01>
ADC_CR1_DISCNUM_Pos (13U)
<01>
ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
<01>
ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
<01>
ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
<01>
ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
<01>
ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
<01>
ADC_CR1_JAWDEN_Pos (22U)
<01>
ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
<01>
ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
<01>
ADC_CR1_AWDEN_Pos (23U)
<01>
ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
<01>
ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
<01>
ADC_CR1_RES_Pos (24U)
<01>
ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
<01>
ADC_CR1_RES ADC_CR1_RES_Msk
<01>
ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
<01>
ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
<01>
ADC_CR1_OVRIE_Pos (26U)
<01>
ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
<01>
ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
<01>
ADC_CR2_ADON_Pos (0U)
<01>
ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
<01>
ADC_CR2_ADON ADC_CR2_ADON_Msk
<01>
ADC_CR2_CONT_Pos (1U)
<01>
ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
<01>
ADC_CR2_CONT ADC_CR2_CONT_Msk
<01>ADC_CR2_DMA_Pos (8U)
<01>ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
<01>ADC_CR2_DMA ADC_CR2_DMA_Msk
<01>ADC_CR2_DDS_Pos (9U)
<01>ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
<01>ADC_CR2_DDS ADC_CR2_DDS_Msk
<01>ADC_CR2_EOCS_Pos (10U)
<01>ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
<01>ADC_CR2_EOCS ADC_CR2_EOCS_Msk
<01>ADC_CR2_ALIGN_Pos (11U)
<01>ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
<01>ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
<01>ADC_CR2_JEXTSEL_Pos (16U)
<01>ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
<01>ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
<01>ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
<01>ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
<01>ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
<01>ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
<01>ADC_CR2_JEXTEN_Pos (20U)
<01>ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
<01>ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
<01>ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
<01>ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
<01>ADC_CR2_JSWSTART_Pos (22U)
<01>ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
<01>ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
<01>ADC_CR2_EXTSEL_Pos (24U)
<01>ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
<01>ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
<01>ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
<01>ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
<01>ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
<01>ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
<01>ADC_CR2_EXTEN_Pos (28U)
<01>ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
<01>ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
<01>ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
<01>ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
<01>ADC_CR2_SWSTART_Pos (30U)
<01>ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
<01>ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
<01>ADC_SMPR1_SMP10_Pos (0U)
<01>ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
<01>ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
<01>ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
<01>ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
<01>ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
<01>ADC_SMPR1_SMP11_Pos (3U)
<01>ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
<01>ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
<01>ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
<01>ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
<01>ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
<01>ADC_SMPR1_SMP12_Pos (6U)
<01>ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
<01>ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
<01>ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
<01>ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
<01>ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
<01>ADC_SMPR1_SMP13_Pos (9U)
<01>ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
<01>ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
<01>ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
<01>ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
<01>ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
<01>ADC_SMPR1_SMP14_Pos (12U)
<01>ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
<01>ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
<01>ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
<01>ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
<01>ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
<01>ADC_SMPR1_SMP15_Pos (15U)
<01>ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
<01>ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
<01>ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
<01>ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
<01>ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
<01>ADC_SMPR1_SMP16_Pos (18U)
<01>ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
<01>ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
<01>ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
<01>ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
<01>ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
<01>ADC_SMPR1_SMP17_Pos (21U)
<01>ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
<01>ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
<01>ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
<01>ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
<01>ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
<01>ADC_SMPR1_SMP18_Pos (24U)
<01>ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
<01>ADC_SMPR1_SMP18 A
DMA1_Stream0_IRQnDMA1_Stream1_IRQnDMA1_Stream2_IRQn
DMA1_Stream3_IRQnDMA1_Stream4_IRQnDMA1_Stream5_IRQnDMA1_Stream6_IRQnADC_IRQnCAN1_TX_IRQnCAN1_RX0_IRQnCAN1_RX1_IRQnCAN1_SCE_IRQnEXTI9_5_IRQnTIM1_BRK_TIM9_IRQnTIM1_UP_TIM10_IRQnTIM1_TRG_COM_TIM11_IRQnTIM1_CC_IRQnTIM2_IRQnTIM3_IRQnTIM4_IRQnI2C1_EV_IRQnI2C1_ER_IRQn I2C2_EV_IRQn!I2C2_ER_IRQn"SPI1_IRQn#SPI2_IRQn$USART1_IRQn%USART2_IRQn&USART3_IRQn'EXTI15_10_IRQn(RTC_Alarm_IRQn)OTG_FS_WKUP_IRQn*TIM8_BRK_TIM12_IRQn+TIM8_UP_TIM13_IRQn,TIM8_TRG_COM_TIM14_IRQn-TIM8_CC_IRQn.DMA1_Stream7_IRQn/FMC_IRQn0SDIO_IRQn1TIM5_IRQn2SPI3_IRQn3UART4_IRQn4UART5_IRQn5TIM6_DAC_IRQn6TIM7_IRQn7DMA2_Stream0_IRQn8DMA2_Stream1_IRQn9DMA2_Stream2_IRQn:DMA2_Stream3_IRQn;DMA2_Stream4_IRQn<ETH_IRQn=ETH_WKUP_IRQn>CAN2_TX_IRQn?CAN2_RX0_IRQn<00>CAN2_RX1_IRQn<00>CAN2_SCE_IRQn<00>OTG_FS_IRQn<00>DMA2_Stream5_IRQn<00>DMA2_Stream6_IRQn<00>DMA2_Stream7_IRQn<00>USART6_IRQn<00>I2C3_EV_IRQn<00>I2C3_ER_IRQn<00>OTG_HS_EP1_OUT_IRQn<00>OTG_HS_EP1_IN_IRQn<00>OTG_HS_WKUP_IRQn<00>OTG_HS_IRQn<00>DCMI_IRQn<00>HASH_RNG_IRQn<00>FPU_IRQn<00>UART7_IRQn<00>UART8_IRQn<00>SPI4_IRQn<00>SPI5_IRQn<00>SPI6_IRQn<00>SAI1_IRQn<00>LTDC_IRQn<00>LTDC_ER_IRQn<00>DMA2D_IRQn<00>iIRQn_Type<12>
<01>
B<>P&SR
#&CR1
#&CR2
#&SMPR1
#&SMPR2
#&JOFR1
#&JOFR2
#&JOFR3
#&JOFR4
# &HTR
#$&LTR
#(&SQR1
#,&SQR2
#0&SQR3
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j
iADC_TypeDef
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B<>&CSR
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#iCAN_TxMailBox_TypeDefi
<01>
B<>&RIR
#&RDTR
#&RDLR
#&RDHR
#iCAN_FIFOMailBox_TypeDef<12>
<01>
B<>&FR1
#&FR2
#iCAN_FilterRegister_TypeDef	
<01>
B<><15>&MCR
#&MSR
#&TSR
#&RF0R
#&RF1R
#&IER
#&ESR
#&BTR
#<03>j

W&RESERVED0<12>	# <03><12>
&sTxMailBox<12>	#<23><03><12>

&sFIFOMailBox<12>	#<23><03>j

&RESERVED1
#<23>&FMR
#<23>&FM1R
#<23>&RESERVED2j
#<23>&FS1R
#<23>&RESERVED3j
#<23>&FFA1R
#<23>&RESERVED4j
#<23>&FA1R
#<23><03>j

&RESERVED5<12>
#<23><03>*	
&sFilterRegister<12>
#<23>iCAN_TypeDefM	
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#&IDR9#&RESERVED0K
#&RESERVED1Z
#&CR
#<00>
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<01>B<>8&CR
#&SWTRIGR
#&DHR12R1
#&DHR12L1
#&DHR8R1
#&DHR12R2
#&DHR12L2
#&DHR8R2
#&DHR12RD
# &DHR12LD
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#(&DOR1
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#0&SR
#4iDAC_TypeDefT
<01>B<>&IDCODE
#&CR
#&APB1FZ
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#iDBGMCU_TypeDef,
<01>B<>,&CR
#&SR
#&RISR
#&IER
#&MISR
#&ICR
#&ESCR
#&ESUR
#&CWSTRTR
# &CWSIZER
#$&DR
#(iDCMI_TypeDef|
<01>B<>&CR
#&NDTR
#&PAR
#&M0AR
#&M1AR
#&FCR
#iDMA_Stream_TypeDef

<01>B<>&LISR
#&HISR
#&LIFCR
#&HIFCR
#iDMA_TypeDef|

<01>B<><1E>&CR
#&ISR
#&IFCR
#&FGMAR
#&FGOR
#&BGMAR
#&BGOR
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# &BGPFCCR
#$&BGCOLR
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#<&OOR
#@&NLR
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<01>
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<01>
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<01>
&BGCLUT<12>#<23>iDMA2D_TypeDef<12>

<01>B<>'<27> &MACCR
#&MACFFR
#&MACHTHR
#&MACHTLR
#&MACMIIAR
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#&MACVLANTR
#<03>j


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'&RESERVED2<12>#`&MMCCR
#<23>&MMCRIR
#<23>&MMCTIR
#<23>&MMCRIMR
#<23>&MMCTIMR
#<23><03>"j


&RESERVED3#<23>&MMCTGFSCCR
#<23>&MMCTGFMSCCR
#<23><03>"j

&RESERVED4K#<23>&MMCTGFCR
#<23><03>#j

	&RESERVED5y#<23>&MMCRFCECR
#<23>&MMCRFAECR
#<23><03>#j

	&RESERVED6<12>#<23>&MMCRGUFCR
#<23><03>#j

<01>&RESERVED7<12>#<23>&PTPTSCR
#<23>&PTPSSIR
#<23>&PTPTSHR
#<23>&PTPTSLR
#<23>&PTPTSHUR
#<23>&PTPTSLUR
#<23>&PTPTSAR
#<23>&PTPTTHR
#<23>&PTPTTLR
#<23>&RESERVED8
#<23>&PTPTSSR
#<23><03>%j

<01>&RESERVED9<12>#<23>&DMABMR
#<23> &DMATPDR
#<23> &DMARPDR
#<23> &DMARDLAR
#<23> &DMATDLAR
#<23> &DMASR
#<23> &DMAOMR
#<23> &DMAIER
#<23> &DMAMFBOCR
#<23> &DMARSWTR
#<23> <03>'j

&RESERVED10y#<23> &DMACHTDR
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#<23> &DMACHTBAR
#<23> &DMACHRBAR
#<23> iETH_TypeDef/
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uwTickH


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uwTickPrioj


<01>
uwTickFreq-


7<00>
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uwTick]
uwTickPrioq
uwTickFreq
NOP

&__STM32F4xx_H 
4STM32F4 
n__STM32F4xx_CMSIS_VERSION_MAIN (0x02U)
o__STM32F4xx_CMSIS_VERSION_SUB1 (0x06U)
p__STM32F4xx_CMSIS_VERSION_SUB2 (0x08U)
q__STM32F4xx_CMSIS_VERSION_RC (0x00U)
r__STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24) |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16) |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 ) |(__STM32F4xx_CMSIS_VERSION_RC))<03>

<01>
IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
<01>
SET_BIT(REG,BIT) ((REG) |= (BIT))
<01>
CLEAR_BIT(REG,BIT) ((REG) &= ~(BIT))
<01>
READ_BIT(REG,BIT) ((REG) & (BIT))
<01>
CLEAR_REG(REG) ((REG) = (0x0))
<01>
WRITE_REG(REG,VAL) ((REG) = (VAL))
<01>
READ_REG(REG) ((REG))
<01>
MODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
<01>
POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
<01>
ATOMIC_SET_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_CLEAR_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)
<01>
ATOMIC_MODIFY_REG(REG,CLEARMSK,SETMASK) do { uint32_t val; do { val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)
<01>ATOMIC_SETH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)
<01>ATOMIC_CLEARH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)
<01>ATOMIC_MODIFYH_REG(REG,CLEARMSK,SETMASK) do { uint16_t val; do { val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)<03><00><00>






../Drivers/CMSIS/Device/ST/STM32F4xx/Include/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx.h
stm32f429xx.h
stm32f4xx_hal.h

h
../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM<19>

RESETSET
iFlagStatus<12>
<01>
iITStatus<12>
<01>
<19>
DISABLEENABLE
iFunctionalState


<01>
<19>
SUCCESSERROR
iErrorStatus<

<01>

RST

STM32_HAL_LEGACY 
#AES_FLAG_RDERR CRYP_FLAG_RDERR
$AES_FLAG_WRERR CRYP_FLAG_WRERR
%AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
&AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
'AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
9ADC_RESOLUTION12b ADC_RESOLUTION_12B
:ADC_RESOLUTION10b ADC_RESOLUTION_10B
;ADC_RESOLUTION8b ADC_RESOLUTION_8B
<ADC_RESOLUTION6b ADC_RESOLUTION_6B
=OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
>OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
?EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
@EOC_SEQ_CONV ADC_EOC_SEQ_CONV
AEOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
BREGULAR_GROUP ADC_REGULAR_GROUP
CINJECTED_GROUP ADC_INJECTED_GROUP
DREGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
EAWD_EVENT ADC_AWD_EVENT
FAWD1_EVENT ADC_AWD1_EVENT
GAWD2_EVENT ADC_AWD2_EVENT
HAWD3_EVENT ADC_AWD3_EVENT
IOVR_EVENT ADC_OVR_EVENT
JJQOVF_EVENT ADC_JQOVF_EVENT
KALL_CHANNELS ADC_ALL_CHANNELS
LREGULAR_CHANNELS ADC_REGULAR_CHANNELS
MINJECTED_CHANNELS ADC_INJECTED_CHANNELS
NSYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
OSYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
PADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
QADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
RADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
SADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
TADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
UADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
VADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
WADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
XADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
YADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
ZADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
[ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
\ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
]ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
^ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
_ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
`ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
bHAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
cHAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
dHAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
eHAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
fHAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
gHAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
hHAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
|__HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
<01>
COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
<01>
COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
<01>
COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
<01>
COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
<01>
COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
<01>
COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
<01>
COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
<01>
COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
<01>
COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
<01>
COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
<01>
__HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
<01>
HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
<01>
HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
<01>
CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
<01>
CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
<01>DAC1_CHANNEL_1 DAC_CHANNEL_1
<01>DAC1_CHANNEL_2 DAC_CHANNEL_2
<01>DAC2_CHANNEL_1 DAC_CHANNEL_1
<01>DAC_WAVE_NONE 0x00000000U
<01>DAC_WAVE_NOISE DAC_CR_WAVE1_0
<01>DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
<01>DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
<01>DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
<01>DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
<01>HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
<01>HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
<01>HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
<01>HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
<01>HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
<01>HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
<01>HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
<01>HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
<01>HAL_REMAPDMA_
TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
<01>
TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
<01>
UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
<01>
UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
<01>
UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
<01>
UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
<01>
__HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
<01>
__HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
<01>
__DIV_SAMPLING16 UART_DIV_SAMPLING16
<01>
__DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
<01>
__DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
<01>
__UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
<01>
__DIV_SAMPLING8 UART_DIV_SAMPLING8
<01>
__DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
<01>
__DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
<01>
__UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
<01>
__DIV_LPUART UART_DIV_LPUART
<01>
UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
<01>
UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
<01>
USART_CLOCK_DISABLED USART_CLOCK_DISABLE
<01>
USART_CLOCK_ENABLED USART_CLOCK_ENABLE
<01>
USARTNACK_ENABLED USART_NACK_ENABLE
<01>
USARTNACK_DISABLED USART_NACK_DISABLE
<01>
CFR_BASE WWDG_CFR_BASE
<01>
CAN_FilterFIFO0 CAN_FILTER_FIFO0
<01>
CAN_FilterFIFO1 CAN_FILTER_FIFO1
<01>
CAN_IT_RQCP0 CAN_IT_TME
<01>
CAN_IT_RQCP1 CAN_IT_TME
<01>
CAN_IT_RQCP2 CAN_IT_TME
<01>
INAK_TIMEOUT CAN_TIMEOUT_VALUE
<01>
SLAK_TIMEOUT CAN_TIMEOUT_VALUE
<01>
CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
<01>
CAN_TXSTATUS_OK ((uint8_t)0x01U)
<01>
CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
<01>
VLAN_TAG ETH_VLAN_TAG
<01>
MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
<01>
MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
<01>
JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
<01>
MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
<01>
MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
<01>
MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
<01>
DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
<01>
ETH_MMCCR 0x00000100U
<01>
ETH_MMCRIR 0x00000104U
<01>
ETH_MMCTIR 0x00000108U
<01>
ETH_MMCRIMR 0x0000010CU
<01>
ETH_MMCTIMR 0x00000110U
<01>
ETH_MMCTGFSCCR 0x0000014CU
<01>
ETH_MMCTGFMSCCR 0x00000150U
<01>
ETH_MMCTGFCR 0x00000168U
<01>
ETH_MMCRFCECR 0x00000194U
<01>
ETH_MMCRFAECR 0x00000198U
<01>
ETH_MMCRGUFCR 0x000001C4U
<01>
ETH_MAC_TXFIFO_FULL 0x02000000U
<01>
ETH_MAC_TXFIFONOT_EMPTY 0x01000000U
<01>
ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U
<01>
ETH_MAC_TXFIFO_IDLE 0x00000000U
<01>
ETH_MAC_TXFIFO_READ 0x00100000U
<01>
ETH_MAC_TXFIFO_WAITING 0x00200000U
<01>
ETH_MAC_TXFIFO_WRITING 0x00300000U
<01>
ETH_MAC_TRANSMISSION_PAUSE 0x00080000U
<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U
<01>ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U
<01>ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U
<01>ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U
<01>ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U
<01>ETH_MAC_RXFIFO_EMPTY 0x00000000U
<01>ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U
<01>ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U
<01>ETH_MAC_RXFIFO_FULL 0x00000300U
<01>ETH_MAC_READCONTROLLER_IDLE 0x00000000U
<01>ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U
<01>ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U
<01>ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U
<01>ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U
<01>ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U
<01>ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U
<01>ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U
<01>ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U
<01>ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U
<01>HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
<01>DCMI_IT_OVF DCMI_IT_OVR
<01>DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
<01>DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
<01>HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
<01>HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
<01>HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
<01>DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
<01>DMA2D_RGB888 DMA2D_OUTPUT_RGB888
<01>DMA2D_RGB565 DMA2D_OUTPUT_RGB565
<01>DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
<01>DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
<01>CM_ARGB8888 DMA2D_INPUT_ARGB8888
<01>CM_RGB888 DMA2D_INPUT_RGB888
<01>CM_RGB565 DMA2D_INPUT_RGB565
<01>CM_ARGB1555 DMA2D_INPUT_ARGB1555
<01>CM_ARGB4444 DMA2D_INPUT_ARGB4444
<01>CM_L8 DMA2D_INPUT_L8
<01>CM_AL44 DMA2D_INPUT_AL44
<01>CM_AL88 DMA2D_INPUT_AL88
<01>CM_L4 DMA2D_INPUT_L4
<01>CM_A8 DMA2D_INPUT_A8
<01>CM_A4 DMA2D_INPUT_A4
<01>HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort
<01>HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
<01>HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler
<01>HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
<01>HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
<01>HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
<01>HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
<01>HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
<01>HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
<01>HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
<01>HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
<01>HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
<01>HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
<01>HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
<01>HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
<01>HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
<01>HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
<01>HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
<01>HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
<01>HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
<01>HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
<01>HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
<01>HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
<01>HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
<01>HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
<01>HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
<01>HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
<01>HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
<01>HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
<01>HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
<01>HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
<01>HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
<01>HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
<01>HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
<01>HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
<01>HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
<01>HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
<01>HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
<01>HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
<01>HAL_DBG_LowPowerConfig(Periph,cmd) (((cmd )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
<01>HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
<01>HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_En
__HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
<01>
__HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
<01>
__HAL_RCC_TIM6_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_TIM7_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_TIM12_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_TIM13_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_TIM14_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_TIM14_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_USART3_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_UART4_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_UART5_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_CAN1_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_CAN2_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_DAC_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_UART7_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN); UNUSED(tmpreg); } while(0U)
<01>
__HAL_RCC_UART8_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_TIM2_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_TIM3_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_TIM4_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_SPI3_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_I2C3_CLK_ENABLE() do { __IO uint32_t tmpreg = 0x00U; SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN); tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN); UNUSED(tmpreg); } while(0U)
<01>__HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
<01>__HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
<01>__HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
<01>__HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
<01>__HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
<01>__HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
<01>__HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
<01>__HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
<01>__HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
<01>__HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
<01>__HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
<01>__HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
<01>__HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
<01>__HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
<01>__HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
<01>__HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
<01>__HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
<01>__HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
<01>__HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
<01>__HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
<01>__HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
<01>__HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
<01>__HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
<01>__HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
<01>__HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
<01>__HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
<01>__HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
<01>__HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
<01>__HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
<01>__HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
<01>__HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
<01>__HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
<01>__HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
<01>__HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
<01>__HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
<01>__HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
<01>__HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
<01>__HAL_RCC_TIM3_IS_CLK_DISAB
RCC_OFFSET (RCC_BASE - PERIPH_BASE)
<01>
RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
<01>
RCC_HSION_BIT_NUMBER 0x00U
<01>
RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
<01>
RCC_CSSON_BIT_NUMBER 0x13U
<01>
RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
<01>
RCC_PLLON_BIT_NUMBER 0x18U
<01>
RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
<01>
RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
<01>
RCC_RTCEN_BIT_NUMBER 0x0FU
<01>
RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
<01>
RCC_BDRST_BIT_NUMBER 0x10U
<01>
RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
<01>
RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
<01>
RCC_LSION_BIT_NUMBER 0x00U
<01>
RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
<01>
RCC_CR_BYTE2_ADDRESS 0x40023802U
<01>
RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
<01>
RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
<01>
RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
<01>
RCC_DBP_TIMEOUT_VALUE 2U
<01>
RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
<01>
HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
<01>
HSI_TIMEOUT_VALUE 2U
<01>
LSI_TIMEOUT_VALUE 2U
<01>
CLOCKSWITCH_TIMEOUT_VALUE 5000U
<01>
IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
<01>
IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || ((HSE) == RCC_HSE_BYPASS))
<01>
IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || ((LSE) == RCC_LSE_BYPASS))
<01>
IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
<01>
IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
<01>
IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
<01>
IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || ((SOURCE) == RCC_PLLSOURCE_HSE))
<01>
IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
<01>
IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
<01>IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
<01>IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
<01>IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
<01>IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || ((HCLK) == RCC_SYSCLK_DIV512))
<01>IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
<01>IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || ((PCLK) == RCC_HCLK_DIV16))
<01>IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
<01>IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
<01>IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_5))
<01>IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)<00><00>






../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h
stm32f4xx_hal_def.h
stm32f4xx_hal_rcc_ex.h


../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARMB<>0&OscillatorTypej
#&HSEStatej
#&LSEStatej
#&HSIStatej
#&HSICalibrationValuej
#&LSIStatej
#&PLL5
#iRCC_OscInitTypeDef<12>
FB<>&ClockTypej
#&SYSCLKSourcej
#&AHBCLKDividerj
#&APB1CLKDividerj
#&APB2CLKDividerj
#iRCC_ClkInitTypeDefy

\
fgh

__STM32F4xx_HAL_GPIO_EX_H 
5GPIO_AF0_RTC_50Hz ((uint8_t)0x00)
6GPIO_AF0_MCO ((uint8_t)0x00)
7GPIO_AF0_TAMPER ((uint8_t)0x00)
8GPIO_AF0_SWJ ((uint8_t)0x00)
9GPIO_AF0_TRACE ((uint8_t)0x00)
>GPIO_AF1_TIM1 ((uint8_t)0x01)
?GPIO_AF1_TIM2 ((uint8_t)0x01)
DGPIO_AF2_TIM3 ((uint8_t)0x02)
EGPIO_AF2_TIM4 ((uint8_t)0x02)
FGPIO_AF2_TIM5 ((uint8_t)0x02)
KGPIO_AF3_TIM8 ((uint8_t)0x03)
LGPIO_AF3_TIM9 ((uint8_t)0x03)
MGPIO_AF3_TIM10 ((uint8_t)0x03)
NGPIO_AF3_TIM11 ((uint8_t)0x03)
SGPIO_AF4_I2C1 ((uint8_t)0x04)
TGPIO_AF4_I2C2 ((uint8_t)0x04)
UGPIO_AF4_I2C3 ((uint8_t)0x04)
ZGPIO_AF5_SPI1 ((uint8_t)0x05)
[GPIO_AF5_SPI2 ((uint8_t)0x05)
\GPIO_AF5_
IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || ((AF) == GPIO_AF14_LTDC))tj






../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h
stm32f4xx_hal_def.h


<01>../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T439\MDK-ARM
jkl

__STM32F4xx_HAL_GPIO_H 
UGPIO_PIN_0 ((uint16_t)0x0001)
VGPIO_PIN_1 ((uint16_t)0x0002)
WGPIO_PIN_2 ((uint16_t)0x0004)
XGPIO_PIN_3 ((uint16_t)0x0008)
YGPIO_PIN_4 ((uint16_t)0x0010)
ZGPIO_PIN_5 ((uint16_t)0x0020)
[GPIO_PIN_6 ((uint16_t)0x0040)
\GPIO_PIN_7 ((uint16_t)0x0080)
]GPIO_PIN_8 ((uint16_t)0x0100)
^GPIO_PIN_9 ((uint16_t)0x0200)
_GPIO_PIN_10 ((uint16_t)0x0400)
`GPIO_PIN_11 ((uint16_t)0x0800)
aGPIO_PIN_12 ((uint16_t)0x1000)
bGPIO_PIN_13 ((uint16_t)0x2000)
cGPIO_PIN_14 ((uint16_t)0x4000)
dGPIO_PIN_15 ((uint16_t)0x8000)
eGPIO_PIN_All ((uint16_t)0xFFFF)
gGPIO_PIN_MASK 0x0000FFFFU
uGPIO_MODE_INPUT MODE_INPUT
vGPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP)
wGPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD)
xGPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP)
yGPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD)
{GPIO_MODE_ANALOG MODE_ANALOG
}GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING)
~GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)
GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)
<01>
GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)
<01>
GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)
<01>
GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)
<01>
GPIO_SPEED_FREQ_LOW 0x00000000U
<01>
GPIO_SPEED_FREQ_MEDIUM 0x00000001U
<01>
GPIO_SPEED_FREQ_HIGH 0x00000002U
<01>
GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U
<01>
GPIO_NOPULL 0x00000000U
<01>
GPIO_PULLUP 0x00000001U
<01>
GPIO_PULLDOWN 0x00000002U
<01>
__HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
<01>
__HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
<01>
__HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
<01>
__HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
<01>
__HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))<03>

<01>
GPIO_MODE_Pos 0U
<01>
GPIO_MODE (0x3UL << GPIO_MODE_Pos)
<01>MODE_INPUT (0x0UL << GPIO_MODE_Pos)
<01>MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)
<01>MODE_AF (0x2UL << GPIO_MODE_Pos)
<01>MODE_ANALOG (0x3UL << GPIO_MODE_Pos)
<01>OUTPUT_TYPE_Pos 4U
<01>OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)
<01>OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)
<01>OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)
<01>EXTI_MODE_Pos 16U
<01>EXTI_MODE (0x3UL << EXTI_MODE_Pos)
<01>EXTI_IT (0x1UL << EXTI_MODE_Pos)
<01>EXTI_EVT (0x2UL << EXTI_MODE_Pos)
<01>TRIGGER_MODE_Pos 20U
<01>TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)
<01>TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)
<01>TRIGGER_FALLING (0x2UL <
5<12>0<12>&XferErrorCallback#Lh<4C>
5<12>0 &XferAbortCallback(#P&ErrorCode<12>#T&StreamBaseAddressj
#X&StreamIndexj
#\0a
<00>
<12>
z{|

__STM32F4xx_HAL_CORTEX_H 
XNVIC_PRIORITYGROUP_0 0x00000007U
ZNVIC_PRIORITYGROUP_1 0x00000006U
\NVIC_PRIORITYGROUP_2 0x00000005U
^NVIC_PRIORITYGROUP_3 0x00000004U
`NVIC_PRIORITYGROUP_4 0x00000003U
iSYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
jSYSTICK_CLKSOURCE_HCLK 0x00000004U
tMPU_HFNMI_PRIVDEF_NONE 0x00000000U
uMPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
vMPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
wMPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
<01>
MPU_REGION_ENABLE ((uint8_t)0x01)
<01>
MPU_REGION_DISABLE ((uint8_t)0x00)
<01>
MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
<01>
MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
<01>
MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
<01>
MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
<01>
MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
<01>
MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
<01>
MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
<01>
MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
<01>
MPU_TEX_LEVEL0 ((uint8_t)0x00)
<01>
MPU_TEX_LEVEL1 ((uint8_t)0x01)
<01>
MPU_TEX_LEVEL2 ((uint8_t)0x02)
<01>
MPU_REGION_SIZE_32B ((uint8_t)0x04)
<01>
MPU_REGION_SIZE_64B ((uint8_t)0x05)
<01>
MPU_REGION_SIZE_128B ((uint8_t)0x06)
<01>
MPU_REGION_SIZE_256B ((uint8_t)0x07)
<01>
MPU_REGION_SIZE_512B ((uint8_t)0x08)
<01>
MPU_REGION_SIZE_1KB ((uint8_t)0x09)
<01>
MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
<01>
MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
<01>
MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
<01>
MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
<01>
MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
<01>
MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
<01>
MPU_REGION_SIZE_128KB ((uint8_t)0x10)
<01>
MPU_REGION_SIZE_256KB ((uint8_t)0x11)
<01>
MPU_REGION_SIZE_512KB ((uint8_t)0x12)
<01>
MPU_REGION_SIZE_1MB ((uint8_t)0x13)
<01>
MPU_REGION_SIZE_2MB ((uint8_t)0x14)
<01>
MPU_REGION_SIZE_4MB ((uint8_t)0x15)
<01>
MPU_REGION_SIZE_8MB ((uint8_t)0x16)
<01>
MPU_REGION_SIZE_16MB ((uint8_t)0x17)
<01>
MPU_REGION_SIZE_32MB ((uint8_t)0x18)
<01>
MPU_REGION_SIZE_64MB ((uint8_t)0x19)
<01>
MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
<01>
MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
<01>
MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
<01>
MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
<01>
MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
<01>
MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
<01>
MPU_REGION_NO_ACCESS ((uint8_t)0x00)
<01>
MPU_REGION_PRIV_RW ((uint8_t)0x01)
<01>
MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
<01>
MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
<01>
MPU_REGION_PRIV_RO ((uint8_t)0x05)
<01>
MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
<01>
MPU_REGION_NUMBER0 ((uint8_t)0x00)
<01>
MPU_REGION_NUMBER1 ((uint8_t)0x01)
<01>
MPU_REGION_NUMBER2 ((uint8_t)0x02)
<01>
MPU_REGION_NUMBER3 ((uint8_t)0x03)
<01>
MPU_REGION_NUMBER4 ((uint8_t)0x04)
<01>
MPU_REGION_NUMBER5 ((uint8_t)0x05)
<01>
MPU_REGION_NUMBER6 ((uint8_t)0x06)
<01>
MPU_REGION_NUMBER7 ((uint8_t)0x07)
<01>IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || ((GROUP) == NVIC_PRIORITYGROUP_4))
<01>IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
<01>IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
<01>IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
<01>IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
<01>IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE))
<01>IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
<01>IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
<01>IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
<01>IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
<01>IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || ((TYPE) == MPU_TEX_LEVEL1) || ((TYPE) == MPU_TEX_LEVEL2))
<01>IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_PRI
&AccessPermissionK
#&DisableExecK
#&IsShareableK
#
&IsCacheableK
#&IsBufferableK
#iMPU_Region_InitTypeDef<12>
E
~<00>

__STM32F4xx_HAL_FLASH_EX_H 
<01>
FLASH_TYPEERASE_SECTORS 0x00000000U
<01>
FLASH_TYPEERASE_MASSERASE 0x00000001U
<01>
FLASH_VOLTAGE_RANGE_1 0x00000000U
<01>
FLASH_VOLTAGE_RANGE_2 0x00000001U
<01>
FLASH_VOLTAGE_RANGE_3 0x00000002U
<01>
FLASH_VOLTAGE_RANGE_4 0x00000003U
<01>
OB_WRPSTATE_DISABLE 0x00000000U
<01>
OB_WRPSTATE_ENABLE 0x00000001U
<01>
OPTIONBYTE_WRP 0x00000001U
<01>
OPTIONBYTE_RDP 0x00000002U
<01>
OPTIONBYTE_USER 0x00000004U
<01>
OPTIONBYTE_BOR 0x00000008U
<01>
OB_RDP_LEVEL_0 ((uint8_t)0xAA)
<01>
OB_RDP_LEVEL_1 ((uint8_t)0x55)
<01>
OB_RDP_LEVEL_2 ((uint8_t)0xCC)
<01>
OB_IWDG_SW ((uint8_t)0x20)
<01>
OB_IWDG_HW ((uint8_t)0x00)
<01>
OB_STOP_NO_RST ((uint8_t)0x40)
<01>
OB_STOP_RST ((uint8_t)0x00)
<01>
OB_STDBY_NO_RST ((uint8_t)0x80)
<01>
OB_STDBY_RST ((uint8_t)0x00)
<01>
OB_BOR_LEVEL3 ((uint8_t)0x00)
<01>
OB_BOR_LEVEL2 ((uint8_t)0x04)
<01>
OB_BOR_LEVEL1 ((uint8_t)0x08)
<01>
OB_BOR_OFF ((uint8_t)0x0C)
<01>
OB_PCROP_STATE_DISABLE 0x00000000U
<01>
OB_PCROP_STATE_ENABLE 0x00000001U
<01>
OPTIONBYTE_PCROP 0x00000001U
<01>
OPTIONBYTE_BOOTCONFIG 0x00000002U
<01>FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
<01>FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
<01>FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
<01>FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
<01>FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
<01>FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
<01>FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
<01>FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
<01>FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
<01>FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS
<01>FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS
<01>FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS
<01>FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS
<01>FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS
<01>FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS
<01>FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS
<01>FLASH_BANK_1 1U
<01>FLASH_BANK_2 2U
<01>FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2)
<01>FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2)
<01>FLASH_SECTOR_0 0U
<01>FLASH_SECTOR_1 1U
<01>FLASH_SECTOR_2 2U
<01>FLASH_SECTOR_3 3U
<01>FLASH_SECTOR_4 4U
<01>FLASH_SECTOR_5 5U
<01>FLASH_SECTOR_6 6U
<01>FLASH_SECTOR_7 7U
<01>FLASH_SECTOR_8 8U
<01>FLASH_SECTOR_9 9U
<01>FLASH_SECTOR_10 10U
<01>FLASH_SECTOR_11 11U
<01>FLASH_SECTOR_12 12U
<01>FLASH_SECTOR_13 13U
<01>FLASH_SECTOR_14 14U
<01>FLASH_SECTOR_15 15U
<01>FLASH_SECTOR_16 16U
<01>FLASH_SECTOR_17 17U
<01>FLASH_SECTOR_18 18U
<01>FLASH_SECTOR_19 19U
<01>FLASH_SECTOR_20 20U
<01>FLASH_SECTOR_21 21U
<01>FLASH_SECTOR_22 22U
<01>FLASH_SECTOR_23 23U
<01>OB_WRP_SECTOR_0 0x00000001U
<01>OB_WRP_SECTOR_1 0x00000002U
<01>OB_WRP_SECTOR_2 0x00000004U
<01>OB_WRP_SECTOR_3 0x00000008U
<01>OB_WRP_SECTOR_4 0x00000010U
<01>OB_WRP_SECTOR_5 0x00000020U
<01>OB_WRP_SECTOR_6 0x00000040U
<01>OB_WRP_SECTOR_7 0x00000080U
<01>OB_WRP_SECTOR_8 0x00000100U
<01>OB_WRP_SECTOR_9 0x00000200U
<01>OB_WRP_SECTOR_10 0x00000400U
<01>OB_WRP_SECTOR_11 0x00000800U
<01>OB_WRP_SECTOR_12 0x00000001U << 12U
<01>OB_WRP_SECTOR_13 0x00000002U << 12U
<01>OB_WRP_SECTOR_14 0x00000004U << 12U
<01>OB_WRP_SECTOR_15 0x00000008U << 12U
<01>OB_WRP_SECTOR_16 0x00000010U << 12U
<01>OB_WRP_SECTOR_17 0x00000020U << 12U
<01>OB_WRP_SECTOR_18 0x00000040U << 12U
<01>OB_WRP_SECTOR_19 0x00000080U << 12U
<01>OB_WRP_SECTOR_20 0x00000100U << 12U
<01>OB_WRP_SECTOR_21 0x00000200U << 12U
<01>OB_WRP_SECTOR_22 0x00000400U << 12U
<01>OB_WRP_SECTOR_23 0x00000800U << 12U
<01>OB_WRP_SECTOR_All 0x00000FFFU << 12U
<01>OB_PCROP_SECTOR_0 0x00000001U
<01>OB_PCROP_SECTOR_1 0x00000002U
<01>OB_PCROP_SECTOR_2 0x00000004U
<01>OB_PCROP_SECTOR_3 0x00000008U
<01>OB_PCROP_SECTOR_4 0x00000010U
<01>OB_PCROP_SECTOR_5 0x00000020U
<01>OB_PCROP_SECTOR_6 0x00000040U
<01>OB_PCROP_SECTOR_7 0x00000080U
<01>OB_PCROP_SECTOR_8 0x00000100U
<01>OB_PCROP_SECTOR_9 0x00000200U
<01>OB_PCROP_SECTOR_10 0x00000400U
<01>OB_PCROP_SECTOR_11 0x00000800U
<01>OB_PCROP_SECTOR_12 0x00000001U
<01>OB_PCROP_SECTOR_13 0x00000002U
<01>OB_PCROP_SECTOR_14 0x00000004U
<01>OB_PCROP_SECTOR_15 0x00000008U
<01>OB_PCROP_SECTOR_16 0x00000010U
<01>OB_PCROP_SECTOR_17 0x00000020U
<01>OB_PCROP_SECTOR_18 0x00000040U
<01>OB_PCROP_SECTOR_19 0x00000080U
<01>OB_PCROP_S

%


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Input Comments:p562c-3Component: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M4.fp.sp --fpu=VFPv4_SP_D16 --apcs=/interwork/interwork --divide callback.oComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]ArmCC --cpp --split_sections --debug -c -otemplate\callback.o --depend=template\callback.d --cpu=Cortex-M4.fp.sp --apcs=interwork -O3 --diag_suppress=9931 -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I..\MDK-ARM -I.\bsp_System -I.\bsp_Device -I.\RTE\_template -ID:\SOFTWARE\Keil_v5\ARM\PACK\ARM\CMSIS\5.9.0\CMSIS\Core\Include -ID:\SOFTWARE\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.15.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include -D__UVISION_VERSION=537 -D_RTE_ -DSTM32F429xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F429xx --omf_browse=template\callback.crf bsp_System\Callback.cpp<00>,
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F)FjF<00><02><00>r.ARM.attributes.strtab.shstrtab.rel.debug_pubnames.rel.debug_frame.rel.debug_line.rel.debug_info.symtab.comment.arm_vfe_header__ARM_grp..debug_abbrev.group.2_8M0000_tpM4SoO0Naf_000000__ARM_grp.Callback.cpp.2_U01000_smMvIz3jZS3_300000__ARM_grp.bsp_PrintArt.h.2_0vs200_5rFdgS7HL7b_120000__ARM_grp.usart.h.2_F1U400_3R30cgfeGPe_v30000__ARM_grp.stdlib.h.2_Yq1000_ga5O7Uo6Yj1_300000__ARM_grp.string.h.2_BX1000_R9yEUUIdVod_700000__ARM_grp.stdarg.h.2_A$0000_GVPHKELl1X9_300000__ARM_grp.gpio.h.2_MR0000_N$QI1PYcQU0_300000__ARM_grp.main.h.2_8T0000_j24Ik2fO8pa_300000__ARM_grp.stm32f4xx_hal_conf.h.2_kx2000_HzGb7RoU$B3_300000__ARM_grp.stm32f4xx_hal_uart.h.2_MTt200_fYWef2Cy5x5_H10000__ARM_grp.stm32f4xx_hal_pwr.h.2_o53000_evsJip8F6i8_800000__ARM_grp.stm32f4xx_hal_pwr_ex.h.2_g12000_JcvX9360759_300000__ARM_grp.stm32f4xx_hal_flash.h.2_YS2000_hfqv7gxtq71_c00000__ARM_grp.stm32f4xx_hal_flash_ramfunc.h.2_YT0000_kT9KM2txqLb_300000__ARM_grp.stm32f4xx_hal_flash_ex.h.2_o05000_Si0Z$SQHN72_o00000__ARM_grp.stm32f4xx_hal_cortex.h.2_4Y3000_Cr558PD0Lmf_h00000__ARM_grp.stm32f4xx_hal_dma.h.2_IJs200_zBSC41H0RNd_n10000__ARM_grp.stm32f4xx_hal_dma_ex.h.2_oV0000_oEH377R7845_300000__ARM_grp.stm32f4xx_hal_exti.h.2_0E2000_cFat$UdxCB1_b00000__ARM_grp.stm32f4xx_hal_gpio.h.2_UW2000_lFa$o9RLBs7_b00000__ARM_grp.stm32f4xx_hal_gpio_ex.h.2_Eu2000_PVCeEz69pT8_300000__ARM_grp.stm32f4xx_hal_rcc.h.2_Y8q000_Vf6gKDicCQ6_D00000__ARM_grp.stm32f4xx_hal_rcc_ex.h.2_o9m000_WJJAQjDUaIf_o00000__ARM_grp.stm32f4xx_hal_def.h.2_sk1000_s6gD3wi$Z11_300000__ARM_grp.stddef.h.2_UY0000_VXMehDdzAme_300000__ARM_grp.stm32_hal_legacy.h.2_MUR000_RrzWXqprA$a_300000__ARM_grp.stm32f4xx.h.2_IS1000_PwNcanTrP51_300000__ARM_grp.stm32f4xx_hal.h.2_fL5000_$y8uOhgSd40_h00000__ARM_grp.stm32f429xx.h.2_UAE400_5yqJ9GEubK3_010000__ARM_grp.system_stm32f4xx.h.2_mo2000_dznNAt9$BS5_h00000__ARM_grp.core_cm4.h.2_j51500_sTeLVz$KFB4_L50000__ARM_grp.mpu_armv7.h.2_UC2000_jmJF__mVnX7_k00000__ARM_grp.cmsis_compiler.h.2_cV0000_ha9I6CVRnHe_300000__ARM_grp.cmsis_armcc.h.2_8f3000_Vrj4SGijR05_Q00000__ARM_grp.cmsis_version.h.2_4X0000_9ZXwYG9dAAb_300000__ARM_grp.CallBack.h.2_wR0000_WtEWymNTiq9_300000__ARM_grp.vartable.h.2_MW0000_9DpezjVIfYb_300000__ARM_grp.stdio.h.2_Ml1000_U_UtJvXZoKb_700000__





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