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e0a8e010334f4ee0b864a65fce8abad3d49c74bb
MicrochipFor32/MX_FastSet/T103RC/MDK-ARM/template/stm32f1xx_hal_pwr.o

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更新modbus,更新rtthread
2023-12-15 01:08:04 +08:00
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L h@<40> `) <09>@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> h <20> `<10>0<EFBFBD><30><EFBFBD>p@<10><00>pG<10>L h<><04><><EFBFBD><EFBFBD><EFBFBD>O<EFBFBD><4F>0 `<10>@ <20><00>pG ..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]D:\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM__asm___19_stm32f1xx_hal_pwr_c_f2cfe8be____REV16X> ..\Drivers\CMSIS\Include\cmsis_armcc.h<03> ..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]D:\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM__asm___19_stm32f1xx_hal_pwr_c_f2cfe8be____REVSHX> ..\Drivers\CMSIS\Include\cmsis_armcc.h<03>..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]D:\<5C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM__asm___19_stm32f1xx_hal_pwr_c_f2cfe8be____RRXX> ..\Drivers\CMSIS\Include\cmsis_armcc.h<03>&0<00><><EFBFBD><EFBFBD>armcc+|  
   0<00><><EFBFBD><EFBFBD>armcc+|  
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   0<00><><EFBFBD><EFBFBD>armcc+|  
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   0<00><><EFBFBD><EFBFBD>armcc+|  
   0<00><><EFBFBD><EFBFBD>armcc+|  
  tA}<7D><03><02>0<00><><EFBFBD><EFBFBD>armcc+|  
   0<00><><EFBFBD><EFBFBD>armcc+|  
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  <B~<7E><02>0<00><><EFBFBD><EFBFBD>armcc+|  
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../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<00>../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM?<3F>u PWR_OverloadWfe<00>../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM?<3F><01>HAL_PWR_DeInit../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM?<3F><01>HAL_PWR_EnableBkUpAccess../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM?<3F><01>HAL_PWR_DisableBkUpAccess../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARMt?<3F><01>HAL_PWR_ConfigPVDtisConfigPVD<10>!<00>../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM?<3F><01>HAL_PWR_EnablePVD<00>../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM?<3F><01>HAL_PWR_DisablePVD../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM?<3F><01>HAL_PWR_EnableWakeUpPiniWakeUpPinxb../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM?<3F><01>HAL_PWR_DisableWakeUpPiniWakeUpPinxb(../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM?<3F><01>HAL_PWR_EnterSLEEPMode$bRegulatoriSLEEPEntryC(../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<?<3F><01>HAL_PWR_EnterSTOPMode<iRegulatorb5iSTOPEntryC"../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM?<3F><01>HAL_PWR_EnterSTANDBYMode../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM ?<3F><01>HAL_PWR_EnableSleepOnExit ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM ?<3F><01>HAL_PWR_DisableSleepOnExit ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 96
../Drivers/CMSIS/Include/cmsis_version.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<00><00><00>__CMSIS_ARMCC_H (__ARM_ARCH_7M__ 15__ASM __asm8__INLINE __inline;__STATIC_INLINE static __inline>__STATIC_FORCEINLINE static __forceinlineA__NO_RETURN __declspec(noreturn)D__USED __attribute__((used))G__WEAK __attribute__((weak))J__PACKED __attribute__((packed))M__PACKED_STRUCT __packed structP__PACKED_UNION __packed unionS__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))V__UNALIGNED_UINT16_WRITE(addr,val) ((*((__packed uint16_t *)(addr))) = (val))Y__UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))\__UNALIGNED_UINT32_WRITE(addr,val) ((*((__packed uint32_t *)(addr))) = (val))___UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))b__ALIGNED(x) __attribute__((aligned(x)))e__RESTRICT __restrict<01>__enable_fault_irq __enable_fiq<01>__disable_fault_irq __disable_fiq<01>__NOP __nop<01>__WFI __wfi<01>__WFE __wfe<01>__SEV __sev<01>__ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U)<01>__DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U)<01>__DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0U)<01>__REV __rev<01>__ROR __ror<01>__BKPT(value) __breakpoint(value)<01>__RBIT __rbit<01>__CLZ __clz<01>__LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")<01>__LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")<01>__LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")<01>__STREXB(value,ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")<01>__STREXH(value,ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")<01>__STREXW(value,ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")<01>__CLREX __clrex<01>__SSAT __ssat<01>__USAT __usat<01>__LDRBT(ptr) ((uint8_t ) __ldrt(ptr))<01>__LDRHT(ptr) ((uint16_t) __ldrt(ptr))<01>__LDRT(ptr) ((uint32_t ) __ldrt(ptr))<01>__STRBT(value,ptr) __strt(value, ptr)<01>__STRHT(value,ptr) __strt(value, ptr)<01>__STRT(value,ptr) __strt(value, ptr)H> ../Drivers/CMSIS/Include/cmsis_armcc.h
../Drivers/CMSIS/Include/cmsis_armcc.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM;<3B><01>__get_CONTROLba__resultbY__regControlbP<<3C><01>__set_CONTROL$bcontrolY__regControlbP;<3B><01>__get_IPSRba__resultbY__regIPSRbP;<3B><01>__get_APSRba__resultbY__regAPSRbP;<3B><01>__get_xPSRba__resultbY__regXPSRbP;<3B><01>__get_PSPba__resultbY__regProcessStackPointerbP<<3C><01>__set_PSP$btopOfProcStackY__regProcessStackPointerbP;<3B><01>__get_MSPba__resultbY__regMainStackPointerbP<<3C><01>__set_MSP$btopOfMainStackY__regMainStackPointerbP;<3B><01>__get_PRIMASKba__resultbY__regPriMaskbP<<3C><01>__set_PRIMASK$bpriMaskY__regPriMaskbP;<3B><01>__get_BASEPRIba__resultbY__regBasePribP<<3C><01>__set_BASEPRI$bbasePriY__regBasePribP<<3C><01>__set_BASEPRI_MAX$bbasePriY__regBasePriMaxbP;<3B> <01>__get_FAULTMASKba__resultbY__regFaultMaskbP<<3C> <01>__set_FAULTMASK$bfaultMaskY__regFaultMaskbP;<3B> <01>__get_FPSCRba__resultb<<3C>
<01>__set_FPSCR$bfpscr<00><00><00>__CMSIS_COMPILER_H "<00><00> ../Drivers/CMSIS/Include/D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\cmsis_compiler.hstdint.hcmsis_armcc.h<01>
../Drivers/CMSIS/Include/cmsis_compiler.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<00><00><00><00> __CORE_CM3_H_GENERIC "?B__CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)C__CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)D__CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | __CM3_CMSIS_VERSION_SUB )G__CORTEX_M (3U)L__FPU_USED 0Us__CORE_CM3_H_DEPENDANT <01>__I volatile const<01>__O volatile<01>__IO volatile<01>__IM volatile const<01>__OM volatile<01>__IOM volatile<01>APSR_N_Pos 31U<01>APSR_N_Msk (1UL << APSR_N_Pos)<01>APSR_Z_Pos 30U<01>APSR_Z_Msk (1UL << APSR_Z_Pos)<01>APSR_C_Pos 29U<01>APSR_C_Msk (1UL << APSR_C_Pos)<01>APSR_V_Pos 28U<01>APSR_V_Msk (1UL << APSR_V_Pos)<01>APSR_Q_Pos 27U<01>APSR_Q_Msk (1UL << APSR_Q_Pos)<01>IPSR_ISR_Pos 0U<01>IPSR_ISR_Msk (0x1FFUL )<01>xPSR_N_Pos 31U<01>xPSR_N_Msk (1UL << xPSR_N_Pos)<01>xPSR_Z_Pos 30U<01>xPSR_Z_Msk (1UL << xPSR_Z_Pos)<01>xPSR_C_Pos 29U<01>xPSR_C_Msk (1UL << xPSR_C_Pos)<01>xPSR_V_Pos 28U<01>xPSR_V_Msk (1UL << xPSR_V_Pos)<01>xPSR_Q_Pos 27U<01>xPSR_Q_Msk (1UL << xPSR_Q_Pos)<01>xPSR_ICI_IT_2_Pos 25U<01>xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)<01>xPSR_T_Pos 24U<01>xPSR_T_Msk (1UL << xPSR_T_Pos)<01>xPSR_ICI_IT_1_Pos 10U<01>xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)<01>xPSR_ISR_Pos 0U<01>xPSR_ISR_Msk (0x1FFUL )<01>CONTROL_SPSEL_Pos 1U<01>CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)<01>CONTROL_nPRIV_Pos 0U<01>CONTROL_nPRIV_Msk (1UL )<01>NVIC_STIR_INTID_Pos 0U<01>NVIC_STIR_INTID_Msk (0x1FFUL )<01>SCB_CPUID_IMPLEMENTER_Pos 24U<01>SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)<01>SCB_CPUID_VARIANT_Pos 20U<01>SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)<01>SCB_CPUID_ARCHITECTURE_Pos 16U<01>SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)<01>SCB_CPUID_PARTNO_Pos 4U<01>SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)<01>SCB_CPUID_REVISION_Pos 0U<01>SCB_CPUID_REVISION_Msk (0xFUL )<01>SCB_ICSR_NMIPENDSET_Pos 31U<01>SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)<01>SCB_ICSR_PENDSVSET_Pos 28U<01>SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)<01>SCB_ICSR_PENDSVCLR_Pos 27U<01>SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)<01>SCB_ICSR_PENDSTSET_Pos 26U<01>SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)<01>SCB_ICSR_PENDSTCLR_Pos 25U<01>SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)<01>SCB_ICSR_ISRPREEMPT_Pos 23U<01>SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)<01>SCB_ICSR_ISRPENDING_Pos 22U<01>SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)<01>SCB_ICSR_VECTPENDING_Pos 12U<01>SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)<01>SCB_ICSR_RETTOBASE_Pos 11U<01>SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)<01>SCB_ICSR_VECTACTIVE_Pos 0U<01>SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )<01>SCB_VTOR_TBLBASE_Pos 29U<01>SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)<01>SCB_VTOR_TBLOFF_Pos 7U<01>SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)<01>SCB_AIRCR_VECTKEY_Pos 16U<01>SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)<01>SCB_AIRCR_VECTKEYSTAT_Pos 16U<01>SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)<01>SCB_AIRCR_ENDIANESS_Pos 15U<01>SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)<01>SCB_AIRCR_PRIGROUP_Pos 8U<01>SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)<01>SCB_AIRCR_SYSRESETREQ_Pos 2U<01>SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)<01>SCB_AIRCR_VECTCLRACTIVE_Pos 1U<01>SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)<01>SCB_AIRCR_VECTRESET_Pos 0U<01>SCB_AIRCR_VECTRESET_Msk (1UL )<01>SCB_SCR_SEVONPEND_Pos 4U<01>SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)<01>SCB_SCR_SLEEPDEEP_Pos 2U<01>SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)<01>SCB_SCR_SLEEPONEXIT_Pos 1U<01>SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)<01>SCB_CCR_STKALIGN_Pos 9U<01>SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)<01>SCB_CCR_BFHFNMIGN_Pos 8U<01>SCB
CoreDebug_DHCSR_S_REGRDY_Pos 16U<01>
CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)<01>
CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U<01>
CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)<01>
CoreDebug_DHCSR_C_MASKINTS_Pos 3U<01>
CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)<01>
CoreDebug_DHCSR_C_STEP_Pos 2U<01>
CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)<01>
CoreDebug_DHCSR_C_HALT_Pos 1U<01>
CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)<01>
CoreDebug_DHCSR_C_DEBUGEN_Pos 0U<01>
CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL )<01>
CoreDebug_DCRSR_REGWnR_Pos 16U<01>
CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)<01>
CoreDebug_DCRSR_REGSEL_Pos 0U<01>
CoreDebug_DCRSR_REGSEL_Msk (0x1FUL )<01>
CoreDebug_DEMCR_TRCENA_Pos 24U<01>
CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)<01>
CoreDebug_DEMCR_MON_REQ_Pos 19U<01>
CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)<01>
CoreDebug_DEMCR_MON_STEP_Pos 18U<01>
CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)<01>
CoreDebug_DEMCR_MON_PEND_Pos 17U<01>
CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)<01>
CoreDebug_DEMCR_MON_EN_Pos 16U<01>
CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)<01>
CoreDebug_DEMCR_VC_HARDERR_Pos 10U<01>
CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)<01>
CoreDebug_DEMCR_VC_INTERR_Pos 9U<01>
CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)<01>
CoreDebug_DEMCR_VC_BUSERR_Pos 8U<01>
CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)<01>
CoreDebug_DEMCR_VC_STATERR_Pos 7U<01>
CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)<01>
CoreDebug_DEMCR_VC_CHKERR_Pos 6U<01>
CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)<01>
CoreDebug_DEMCR_VC_NOCPERR_Pos 5U<01>
CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)<01>
CoreDebug_DEMCR_VC_MMERR_Pos 4U<01>
CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)<01>
CoreDebug_DEMCR_VC_CORERESET_Pos 0U<01>
CoreDebug_DEMCR_VC_CORERESET_Msk (1UL )<01>
_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)<01>
_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)<01>
SCS_BASE (0xE000E000UL)<01>
ITM_BASE (0xE0000000UL)<01>
DWT_BASE (0xE0001000UL)<01>
TPI_BASE (0xE0040000UL)<01>
CoreDebug_BASE (0xE000EDF0UL)<01>
SysTick_BASE (SCS_BASE + 0x0010UL)<01>
NVIC_BASE (SCS_BASE + 0x0100UL)<01>
SCB_BASE (SCS_BASE + 0x0D00UL)<01>
SCnSCB ((SCnSCB_Type *) SCS_BASE )<01>
SCB ((SCB_Type *) SCB_BASE )<01>
SysTick ((SysTick_Type *) SysTick_BASE )<01>
NVIC ((NVIC_Type *) NVIC_BASE )<01>
ITM ((ITM_Type *) ITM_BASE )<01>
DWT ((DWT_Type *) DWT_BASE )<01>
TPI ((TPI_Type *) TPI_BASE )<01>
CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)<01> NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping<01> NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping<01> NVIC_EnableIRQ __NVIC_EnableIRQ<01> NVIC_GetEnableIRQ __NVIC_GetEnableIRQ<01> NVIC_DisableIRQ __NVIC_DisableIRQ<01> NVIC_GetPendingIRQ __NVIC_GetPendingIRQ<01> NVIC_SetPendingIRQ __NVIC_SetPendingIRQ<01> NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ<01> NVIC_GetActive __NVIC_GetActive<01> NVIC_SetPriority __NVIC_SetPriority<01> NVIC_GetPriority __NVIC_GetPriority<01> NVIC_SystemReset __NVIC_SystemReset<01> NVIC_SetVector __NVIC_SetVector<01> NVIC_GetVector __NVIC_GetVector<01> NVIC_USER_IRQ_OFFSET 16<01> EXC_RETURN_HANDLER (0xFFFFFFF1UL)<01> EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL)<01> EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL)<01>ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)<00><00> ../Drivers/CMSIS/Include/D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\core_cm3.hstdint.hcmsis_version.hcmsis_compiler.h\
../Drivers/CMSIS/Include/core_cm3.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM*<2A>!_reserved0b#!Qb#!Vb#!Cb#!Zb#!Nb#S<>b<12>wbPAPSR_Type <01>*<2A>!ISRb# !_reserved0b#S<>bEwbPIPSR_Typeq<01>*<2A>!ISRb# !_reserved0b#!ICI_IT_1b#!_reserved1b#!Tb#!ICI_IT_2b#!Qb#!Vb#!Cb#!Zb#!Nb#S<>b<12>wbPxPSR_TypeW<01>*<2A>!nPRIVb#!SPSELb#!_reserved1b#S<>b|wbPCONTROL_Type<12><01>*<2A><08><03>&ISER<12>#<03>bRESERVED0<12># <03>&ICER#<23><03>bRSERVED10#<23><03>&ISPRL#<23><03>bRESERVED2b#<23><03>&ICPR#<23><03>bRESERVED3<12>#<23><03>&IABR<12>#<23><03>b7RESERVED4<12>#<23><03>,<01>IP<12>#<23><03>b<01>RESERVED5<12>#<23>STIR&#<23>tbtCPNVIC_Type<12><01>*<2A>
<EFBFBD>CPUID<12>#ICSR&#VTOR&#AIRCR&# SCR&#CCR&#<03> , SHP<12>#SHCSR&#$CFSR&#(HFSR&#,DFSR&#0MMFAR&#4BFAR&#8AFSR&#<<03>
<12>PFR<12>#@DFR<12>#HADR<12>#L<03>
<12>MMFR%#P<03>
<12>ISAR:#`<03>
bRESERVED0O#tCPACR&#<23>btzPSCB_TypeD<01>*<2A> <03> bRESERVED0<12>#ICTR<12>#ACTLR&#PSCnSCB_Type<12><01>*<2A> CTRL&#LOAD&#VAL&#CALIB<12># PSysTick_Type<12><01>S<> u8,u16Iu32&tR*<2A><10> <03> PORTT#<03> b<01>RESERVED0i#<23>TER&#<23><03> bRESERVED1<12>#<23>TPR&#<23><03> bRESERVED2<12>#<23>TCR&#<23><03> bRESERVED3<12>#<23>IWR&#<23>IRR<12>#<23>IMCR&#<23><03>b*RESERVED4'#<23>LAR&#<23>LSR<12>#<23><03>bRESERVED5\#<23>PID4<12>#<23>PID5<12>#<23>PID6<12>#<23>PID7<12>#<23>PID0<12>#<23>PID1<12>#<23>PID2<12>#<23>PID3<12>#<23>CID0<12>#<23>CID1<12>#<23>CID2<12>#<23>CID3<12>#<23>t-PITM_TypeO<01>*<2A>\CTRL&#CYCCNT&#CPICNT&#EXCCNT&# SLEEPCNT&#LSUCNT&#FOLDCNT&#PCSR<12>#COMP0&# MASK0&#$FUNCTION0&#(<03>bRESERVED0<12>#,COMP1&#0MASK1&#4FUNCTION1&#8<03>bRESERVED1 #<COMP2&#@MASK2&#DFUNCTION2&#H<03>bRESERVED2W #LCOMP3&#PMASK3&#TFUNCTION3&#XPDWT_Type+<01>*<2A><16>SSPSR<12>#CSPSR&#<03>bRESERVED0<12> #ACPR&#<03>b6RESERVED1<12> #SPPR&#<23><03>b<01>RESERVED2
#<23>FFSR<12>#<23>FFCR&#<23>FSCR<12>#<23><03>b<01>RESERVED3e
#<23>TRIGGER<12>#<23>FIFO0<12>#<23>ITATBCTR2<12>#<23><03>bRESERVED4<12>
#<23>ITATBCTR0<12>#<23>FIFO1<12>#<23>ITCTRL&#<23><03>b&RESERVED5<12>
#<23>CLAIMSET&#<23>CLAIMCLR&#<23><03>bRESERVED7> #<23>DEVID<12>#<23>DEVTYPE<12>#<23>PTPI_Type<12> <01>*<2A>DHCSR&#DCRSR&#DCRDR&#DEMCR&# PCoreDebug_Type<12> <01> t%qITM_RxBuffer<12> <<3C><01> __NVIC_SetPriorityGrouping$bPriorityGroup\reg_valueb\PriorityGroupTmpb;<3B><01> __NVIC_GetPriorityGroupingba__resultb<<3C><01> __NVIC_EnableIRQ$IRQn;<3B><01> __NVIC_GetEnableIRQb$IRQna__resultb<<3C><01> __NVIC_DisableIRQ$IRQn;<3B><01> __NVIC_GetPendingIRQb$IRQna__resultb<<3C><01> __NVIC_SetPendingIRQ$IRQn<<3C><01> __NVIC_ClearPendingIRQ$IRQn;<3B><01> __NVIC_GetActiveb$IRQna__resultb<<3C><01> __NVIC_SetPriority$IRQn$bpriority;<3B><01> __NVIC_GetPriorityb$IRQna__resultb;<3B><01> NVIC_EncodePriorityb$bPriorityGroup$bPreemptPriority$bSubPrioritya__resultb\PriorityGroupTmpb\PreemptPriorityBitsb\SubPriorityBitsb<<3C><01> NVIC_DecodePriority$bPriority$bPriorityGroup$<12>pPreemptPriority$<12>pSubPriority\PriorityGroupTmpb\PreemptPriorityBitsb\SubPriorityBitsb"b<12><<3C><01> __NVIC_SetVector$IRQn$bvector\vectors<12>;<3B> <01> __NVIC_GetVectorb$IRQna__resultb\vectors<12><<3C> <01> "__NVIC_SystemReset;<3B>!<01>SCB_GetFPUTypeba__resultb;<3B>!<01>SysTick_Configb$bticksa__resultb;<3B>!<01>ITM_SendCharb$bcha__resultb;<3B>"<01>ITM_ReceiveChar%a__result%\ch%;<3B>"<01>ITM_CheckChar%a__result%`<00> ITM_RxBuffer<00><00><00><00> __SYSTEM_STM32F10X_H `W ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h0
../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARMqSystemCoreClockbC<03><12>qAHBPrescTable<12><03><12>qAPBPrescTableF4<00>SystemCoreClockAHBPrescTableAPBPrescTable<00><00><00>&__STM32F103xE_H 2__CM3_REV 0x0200U3__MPU_PRESENT 0U4__NVIC_PRIO_BITS 4U5__Vendor_SysTickConfig 0U<03><03><03><01>FLASH_BASE 0x08000000UL<01>FLASH_BANK1_END 0x0807FFFFUL<01>SRAM_BASE 0x20000000UL<01>PERIPH_BASE 0x40000000UL<01>SRAM_BB_BASE 0x22000000UL<01>PERIPH_BB_BASE 0x42000000UL<01>FSMC_BASE 0x60000000UL<01>FSMC_R_BASE 0xA0000000UL<01>APB1PERIPH_BASE PERIPH_BASE<01>APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)<01>AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)<01>TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)<01>TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)<01>TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)<01>TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL)<01>TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL)<01>TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL)<01>RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)<01>WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)<01>IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)<01>SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)<01>SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL)<01>USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)<01>USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)<01>UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL)<01>UART5_BASE (APB1PERIPH_BASE + 0x00005000UL)<01>I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)<01>I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)<01>CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL)<01>BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL)<01>PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)<01>DAC_BASE (APB1PERIPH_BASE + 0x00007400UL)<01>AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL)<01>EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)<01>GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL)<01>GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL)<01>GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL)<01>GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL)<01>GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL)<01>GPIOF_BASE (APB2PERIPH_BASE + 0x00001C00UL)<01>GPIOG_BASE (APB2PERIPH_BASE + 0x00002000UL)<01>ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL)<01>ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL)<01>TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)<01>SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)<01>TIM8_BASE (APB2PERIPH_BASE + 0x00003400UL)<01>USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)<01>ADC3_BASE (APB2PERIPH_BASE + 0x00003C00UL)<01>SDIO_BASE (PERIPH_BASE + 0x00018000UL)<01>DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)<01>DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL)<01>DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL)<01>DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL)<01>DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL)<01>DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL)<01>DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL)<01>DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL)<01>DMA2_BASE (AHBPERIPH_BASE + 0x00000400UL)<01>DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408UL)<01>DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CUL)<01>DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430UL)<01>DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444UL)<01>DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458UL)<01>RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)<01>CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)<01>FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL)<01>FLASHSIZE_BASE 0x1FFFF7E0UL<01>UID_BASE 0x1FFFF7E8UL<01>OB_BASE 0x1FFFF800UL<01>FSMC_BANK1 (FSMC_BASE)<01>FSMC_BANK1_1 (FSMC_BANK1)<01>FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000UL)<01>FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000UL)<01>FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000UL)<01>FSMC_BANK2 (FSMC_BASE + 0x10000000UL)<01>FSMC_BANK3 (FSMC_BASE + 0x20000000UL)<01>FSMC_BANK4 (FSMC_BASE + 0x30000000UL)<01>FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x00000000UL)<01>FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x00000104UL)<01>FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x00000060UL)<01>FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x000000A0UL)<01>DBG
RCC_CR_HSION RCC_CR_HSION_Msk<01>
RCC_CR_HSIRDY_Pos (1U)<01>
RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)<01>
RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk<01>
RCC_CR_HSITRIM_Pos (3U)<01>
RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)<01>
RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk<01>
RCC_CR_HSICAL_Pos (8U)<01>
RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)<01>
RCC_CR_HSICAL RCC_CR_HSICAL_Msk<01>
RCC_CR_HSEON_Pos (16U)<01>
RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)<01>
RCC_CR_HSEON RCC_CR_HSEON_Msk<01>
RCC_CR_HSERDY_Pos (17U)<01>
RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)<01>
RCC_CR_HSERDY RCC_CR_HSERDY_Msk<01>
RCC_CR_HSEBYP_Pos (18U)<01>
RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)<01>
RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk<01>
RCC_CR_CSSON_Pos (19U)<01>
RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)<01>
RCC_CR_CSSON RCC_CR_CSSON_Msk<01>
RCC_CR_PLLON_Pos (24U)<01>
RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)<01>
RCC_CR_PLLON RCC_CR_PLLON_Msk<01>
RCC_CR_PLLRDY_Pos (25U)<01>
RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)<01>
RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk<01>
RCC_CFGR_SW_Pos (0U)<01>
RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)<01>
RCC_CFGR_SW RCC_CFGR_SW_Msk<01>
RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)<01>
RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)<01>
RCC_CFGR_SW_HSI 0x00000000U<01>
RCC_CFGR_SW_HSE 0x00000001U<01>
RCC_CFGR_SW_PLL 0x00000002U<01>
RCC_CFGR_SWS_Pos (2U)<01>
RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)<01>
RCC_CFGR_SWS RCC_CFGR_SWS_Msk<01>
RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)<01>
RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)<01>
RCC_CFGR_SWS_HSI 0x00000000U<01>
RCC_CFGR_SWS_HSE 0x00000004U<01>
RCC_CFGR_SWS_PLL 0x00000008U<01>
RCC_CFGR_HPRE_Pos (4U)<01>
RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)<01>
RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk<01>
RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)<01>
RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)<01>
RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)<01>
RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)<01>
RCC_CFGR_HPRE_DIV1 0x00000000U<01>
RCC_CFGR_HPRE_DIV2 0x00000080U<01>
RCC_CFGR_HPRE_DIV4 0x00000090U<01>
RCC_CFGR_HPRE_DIV8 0x000000A0U<01>
RCC_CFGR_HPRE_DIV16 0x000000B0U<01>
RCC_CFGR_HPRE_DIV64 0x000000C0U<01>
RCC_CFGR_HPRE_DIV128 0x000000D0U<01>
RCC_CFGR_HPRE_DIV256 0x000000E0U<01>
RCC_CFGR_HPRE_DIV512 0x000000F0U<01>
RCC_CFGR_PPRE1_Pos (8U)<01>
RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)<01>
RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk<01>
RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)<01>
RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)<01>
RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)<01>
RCC_CFGR_PPRE1_DIV1 0x00000000U<01>
RCC_CFGR_PPRE1_DIV2 0x00000400U<01>
RCC_CFGR_PPRE1_DIV4 0x00000500U<01>
RCC_CFGR_PPRE1_DIV8 0x00000600U<01>
RCC_CFGR_PPRE1_DIV16 0x00000700U<01>
RCC_CFGR_PPRE2_Pos (11U)<01>
RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)<01>
RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk<01>
RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)<01>
RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)<01>
RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)<01>
RCC_CFGR_PPRE2_DIV1 0x00000000U<01>
RCC_CFGR_PPRE2_DIV2 0x00002000U<01>
RCC_CFGR_PPRE2_DIV4 0x00002800U<01>
RCC_CFGR_PPRE2_DIV8 0x00003000U<01>
RCC_CFGR_PPRE2_DIV16 0x00003800U<01>
RCC_CFGR_ADCPRE_Pos (14U)<01>
RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos)<01>
RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk<01>
RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos)<01>
RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos)<01>
RCC_CFGR_ADCPRE_DIV2 0x00000000U<01>
RCC_CFGR_ADCPRE_DIV4 0x00004000U<01>
RCC_CFGR_ADCPRE_DIV6 0x00008000U<01>
RCC_CFGR_ADCPRE_DIV8 0x0000C000U<01>
RCC_CFGR_PLLSRC_Pos (16U)<01>
RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos)<01>
RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk<01>
RCC_CFGR_PLLXTPRE_Pos (17U)<01>
RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos)<01>
RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk<01>
RCC_CFGR_PLLMULL_Pos (18U)<01>
RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos)<01>
RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk<01>
RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos)<01>
RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos)<01>
RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos)<01>
RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos)<01> RCC_CFGR_PLLXTPRE_HSE 0x00000000U<01> RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U<01> RCC_CFGR_PLLMULL2 0x00000000U<01> RCC_CFGR_PLLMULL3_Pos (18U)<01> RCC_CFGR_PLLMULL3_Msk (0x1UL << RCC_CFGR_PLLMULL3_Pos)<01> RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk<01> RCC_CFGR_PLLMULL4_Pos (19U)<01> RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos)<01> RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk<01> RCC_CFGR_PLLMULL5_Pos (18U)<01> RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos)<01> RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk<01> RCC_CFGR_PLLMULL6_Pos (20U)<01> RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos)<01> RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk<01> RCC_CFGR_PLLMULL7_Pos (18U)<01> RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos)<01> RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk<01> RCC_CFGR_PLLMULL8_Pos (19U)<01> RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos)<01> RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk<01> RCC_CFGR_PLLMULL9_Pos (18U)<01> RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos)<01> RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk<01> RCC_CFGR_PLLMULL10_Pos (21U)<01> RCC_CFGR_PLLMULL10_Msk (0x1UL << RCC_CFGR_PLLMULL10_Pos)<01> RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk<01> RCC_CFGR_PLLMULL11_Pos (18U)<01> RCC_CFGR_PLLMULL11_Msk (0x9UL << RCC_CFGR_PLLMULL11_Pos)<01> RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk<01> RCC_CFGR_PLLMULL12_Pos (19U)<01> RCC_CFGR_PLLMULL12_Msk (0x5UL << RCC_CFGR_PLLMULL12_Pos)<01> RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk<01> RCC_CFGR_PLLMULL13_Pos (18U)<01> RCC_CFGR_PLLMULL13_Msk (0xBUL << RCC_CFGR_PLLMULL13_Pos)<01> RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk<01> RCC_CFGR_PLLMULL14_Pos (20U)<01> RCC_CFGR_PLLMULL14_Msk (0x3UL << RCC_CFGR_PLLMULL14_Pos)<01> RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk<01> RCC_CFGR_PLLMULL15_Pos (18U)<01> RCC_CFGR_PLLMULL15_Msk (0xDUL << RCC_CFGR_PLLMULL15_Pos)<01> RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk<01> RCC_CFGR_PLLMULL16_Pos (19U)<01> RCC_CFGR_PLLMULL16_Msk (0x7UL << RCC_CFGR_PLLMULL16_Pos)<01> RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk<01> RCC_CFGR_USBPRE_Pos (22U)<01> RCC_CFGR_USBPRE_Msk (0x1UL << RCC_CFGR_USBPRE_Pos)<01> RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk<01> RCC_CFGR_MCO_Pos (24U)<01> RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos)<01> RCC_CFGR_MCO RCC_CFGR_MCO_Msk<01> RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos)<01> RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos)<01> RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos)<01> RCC_CFGR_MCO_NOCLOCK 0x00000000U<01> RCC_CFGR_MCO_SYSCLK 0x04000000U<01> RCC_CFGR_MCO_HSI 0x05000000U<01> RCC_CFGR_MCO_HSE 0x06000000U<01> RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U<01> RCC_CFGR_MCOSEL RCC_CFGR_MCO<01> RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0<01> RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1<01> RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2<01> RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK<01> RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK<01> RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI<01> RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE<01> RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2<01> RCC_CIR_LSIRDYF_Pos (0U)<01> RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)<01> RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk<01> RCC_CIR_LSERDYF_Pos (1U)<01> RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)<01> RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk<01> RCC_CIR_HSIRDYF_Pos (2U)<01> RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)<01> RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk<01> RCC_CIR_HSERDYF_Pos (3U)<01> RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)<01> RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk<01> RCC_CIR_PLLRDYF_Pos (4U)<01> RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)<01> RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk<01> RCC_CIR_CSSF_Pos (7U)<01> RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)<01> RCC_CIR_CSSF RCC_CIR_CSSF_Msk<01> RCC_CIR_LSIRDYIE_Pos (8U)<01> RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)<01> RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk<01> RCC_CIR_LSERDYIE_Pos (9U)<01> RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)<01> RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk<01> RCC_CIR_HSIRDYIE_Pos (10U)<01> RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)<01> RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk<01> RCC_CIR_HSERDYIE_Pos (11U)<01> RCC_CIR_HSERDYIE_
../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<13>
NonMaskableInt_IRQnrHardFault_IRQnsMemoryManagement_IRQntBusFault_IRQnuUsageFault_IRQnvSVCall_IRQn{DebugMonitor_IRQn|PendSV_IRQn~SysTick_IRQnWWDG_IRQnPVD_IRQnTAMPER_IRQnRTC_IRQnFLASH_IRQnRCC_IRQnEXTI0_IRQnEXTI1_IRQnEXTI2_IRQnEXTI3_IRQn EXTI4_IRQn
DMA1_Channel1_IRQn DMA1_Channel2_IRQn DMA1_Channel3_IRQn DMA1_Channel4_IRQnDMA1_Channel5_IRQnDMA1_Channel6_IRQnDMA1_Channel7_IRQnADC1_2_IRQnUSB_HP_CAN1_TX_IRQnUSB_LP_CAN1_RX0_IRQnCAN1_RX1_IRQnCAN1_SCE_IRQnEXTI9_5_IRQnTIM1_BRK_IRQnTIM1_UP_IRQnTIM1_TRG_COM_IRQnTIM1_CC_IRQnTIM2_IRQnTIM3_IRQnTIM4_IRQnI2C1_EV_IRQnI2C1_ER_IRQn I2C2_EV_IRQn!I2C2_ER_IRQn"SPI1_IRQn#SPI2_IRQn$USART1_IRQn%USART2_IRQn&USART3_IRQn'EXTI15_10_IRQn(RTC_Alarm_IRQn)USBWakeUp_IRQn*TIM8_BRK_IRQn+TIM8_UP_IRQn,TIM8_TRG_COM_IRQn-TIM8_CC_IRQn.ADC3_IRQn/FSMC_IRQn0SDIO_IRQn1TIM5_IRQn2SPI3_IRQn3UART4_IRQn4UART5_IRQn5TIM6_IRQn6TIM7_IRQn7DMA2_Channel1_IRQn8DMA2_Channel2_IRQn9DMA2_Channel3_IRQn:DMA2_Channel4_5_IRQn;PIRQn_Type<12><01>*<2A> PSR"#CR1"#CR2"#SMPR1"# SMPR2"#JOFR1"#JOFR2"#JOFR3"#JOFR4"# HTR"#$LTR"#(SQR1"#,SQR2"#0SQR3"#4JSQR"#8JDR1"#<JDR2"#@JDR3"#DJDR4"#HDR"#LtbPADC_TypeDef/<01>*<2A> PSR"#CR1"#CR2"#<03> bRESERVED`# DR"#LPADC_Common_TypeDef<<01>*<2A><11>RESERVED0b#DR1"#DR2"#DR3"# DR4"#DR5"#DR6"#DR7"#DR8"# DR9"#$DR10"#(RTCCR"#,CR"#0CSR"#4<03>bRESERVED13J#8DR11"#@DR12"#DDR13"#HDR14"#LDR15"#PDR16"#TDR17"#XDR18"#\DR19"#`DR20"#dDR21"#hDR22"#lDR23"#pDR24"#tDR25"#xDR26"#|DR27"#<23>DR28"#<23>DR29"#<23>DR30"#<23>DR31"#<23>DR32"#<23>DR33"#<23>DR34"#<23>DR35"#<23>DR36"#<23>DR37"#<23>DR38"#<23>DR39"#<23>DR40"#<23>DR41"#<23>DR42"#<23>PBKP_TypeDef<12><01>*<2A>TIR"#TDTR"#TDLR"#TDHR"# PCAN_TxMailBox_TypeDef <01>*<2A>RIR"#RDTR"#RDLR"#RDHR"# PCAN_FIFOMailBox_TypeDef^ <01>*<2A>FR1"#FR2"#PCAN_FilterRegister_TypeDef<12> <01>*<2A><16>MCR"#MSR"#TSR"#RF0R"# RF1R"#IER"#ESR"#BTR"#<03>bWRESERVED0O
# <03>@ sTxMailBoxk
#<23><03><12> sFIFOMailBox<12>
#<23><03>b RESERVED1<12>
#<23>FMR"#<23>FM1R"#<23>RESERVED2b#<23>FS1R"#<23>RESERVED3b#<23>FFA1R"#<23>RESERVED4b#<23>FA1R"#<23><03>bRESERVED5? #<23><03><12>  sFilterRegister\ #<23>PCAN_TypeDef<12> <01>*<2A> DR"#IDR<12> #RESERVED0C#RESERVED1R#CR"#tCPCRC_TypeDef<12> <01>*<2A>4CR"#SWTRIGR"#DHR12R1"#DHR12L1"# DHR8R1"#DHR12R2"#DHR12L2"#DHR8R2"#DHR12RD"# DHR12LD"#$DHR8RD"#(DOR1"#,DOR2"#0PDAC_TypeDef<12> <01>*<2A>IDCODE"#CR"#PDBGMCU_TypeDef<12> <01>*<2A>CCR"#CNDTR"#CPAR"#CMAR"# PDMA_Channel_TypeDef<12> <01>*<2A>ISR"#IFCR"#PDMA_TypeDefI <01>*<2A>IMR"#EMR"#RTSR"#FTSR"# SWIER"#PR"#PEXTI_TypeDefy <01>*<2A>$ACR"#KEYR"#OPTKEYR"#SR"# CR"#AR"#RESERVED"#OBR"#WRPR"# PFLASH_TypeDef<12> <01>*<2A>RDP<12>#USER<12>#Data0<12>#Data1<12>#WRP0<12>#WRP1<12>#
WRP2<12># WRP3<12>#tRPOB_TypeDef^<01>*<2A> <03>"BTCR<12>#PFSMC_Bank1_TypeDef<12><01>*<2A><03>"BWTR#PFSMC_Bank1E_TypeDef<01>*<2A> 8PCR2"#SR2"#PMEM2"#PATT2"# RESERVED0b#ECCR2"#RESERVED1b#RESERVED2b#PCR3"# SR3"#$PMEM3"#(PATT3"#,RESERVED3b#0ECCR3"#4PFSMC_Bank2_3_TypeDefH<01>*<2A> PCR4"#SR4"#PMEM4"#PATT4"# PIO4"#PFSMC_Bank4_TypeDef2<01>*<2A>!CRL"#CRH"#IDR"#ODR"# BSRR"#BRR"#LCKR"#PGPIO_TypeDef<12><01>*<2A>" EVCR"#MAPR"#<03>""EXTICR#RESERVED0b#MAPR2"#PAFIO_TypeDef<12><01>*<2A>#$CR1"#CR2"#OAR1"#OAR2"# DR"#SR1"#SR2"#CCR"#TRISE"# PI2C_TypeDefa<01>*<2A>$KR"#PR"#RLR"#SR"# PIWDG_TypeDef<12><01>*<2A>$CR"#CSR"#PPWR_TypeDef#<01>*<2A>%(CR"#CFGR"#CIR"#APB2RSTR"# APB1RSTR"#AHBENR"#APB2ENR"#APB1ENR"#BDCR"# CSR"#$PRCC_TypeDefQ<01>*<2A>&(CRH"#CRL"#PRLH"#PRLL"# DIVH"#DIVL"#CNTH"#CNTL"#ALRH"# ALRL"#$PRTC_TypeDef<12><01>*<2A>)<29>POWER"#CLKCR"#ARG"#CMD"# RESPCMD<12>#RESP1<12>#RESP2<12>#RESP3<12>#RESP4<12># DTIMER"#$DLEN"#(DCTRL"#,DCOUNT<12>#0STA<12>#4ICR"#8MASK"#<<03>(bRESERVED0L#@FIFOCNT<12>#H<03>)b RESERVED1w#LFIFO"#<23>bt<12>PSDIO_TypeDef}<01>*<2A>*$CR1"#CR2"#SR"#DR"# CRCPR"#RXCRCR"#TXCRCR"#I2SCFGR"#I2SPR"# PSPI_TypeDef<12><01>*<2A>,TCR1"#CR2"#SMCR"#DIER"# SR"#EGR"#CCMR1"#CCMR2"#CCER"# CNT"#$PSC"#(ARR"#,RCR"#0CCR1"#4CCR2"#8CCR3"#<CCR4"#@BDTR"#DDCR"#HDMAR"#LOR"#PPTIM_TypeDefH<01>*<2A>-SR"#DR"#BRR"#CR1"# CR2"#CR3"#GTPR"#PUSART_TypeDefS<01>*<2A>0TEP0R<12>#RESERVED0<12>#EP1R<12>#RESERVED1<12>#EP2R<12>#RESERVED2<12>#
EP3R<12># RESERVED3<12>#EP4R<12>#RESERVED4<12>#EP5R<12>#RESERVED5<12>#EP6R<12>#RESERVED6<12>#EP7R<12>#<03>/<12>RESERVED7<12>#CNTR<12>#@RESERVED8<12>#BISTR<12>#DRESERVED9<12>#FFNR<12>#HRESERVEDA<12>#JDADDR<12>#LRESERVEDB<12>#NBTABLE<12>#PRESERVEDC<12>#RPUSB_TypeDef<12><01>*<2A>0 CR"#CFR"#SR"#PWWDG_TypeDefW<01><00><00><00><00>__STM32F1xx_HAL_H X__HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)Y__HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)^__HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)___HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)e__HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)f__HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)m__HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)n__HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)u__HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)v__HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)}__HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)~__HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)<01>__HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)<01>__HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)<01>__HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)<01>__HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)<01>__HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)<01>__HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)<01>__HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)<01>__HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)<01>__HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)<01>__HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)<01>__HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)<01>__HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)<01>__HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)<01>__HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)<01>IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || ((FREQ) == HAL_TICK_FREQ_1KHZ))|p ../Drivers/STM32F1xx_HAL_Driver/Inc/../Core/Inc/stm32f1xx_hal.hstm32f1xx_hal_conf.h<01>
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<13>HAL_TICK_FREQ_10HZ dHAL_TICK_FREQ_100HZ
HAL_TICK_FREQ_1KHZ HAL_TICK_FREQ_DEFAULT PHAL_TickFreqTypeDef<12>7tbquwTickJquwTickPriobquwTickFreq/7<00>PuwTick]uwTickPriopuwTickFreq<00><00><00>'__STM32F1XX_H 5STM32F1 ___STM32F1_CMSIS_VERSION_MAIN (0x04)`__STM32F1_CMSIS_VERSION_SUB1 (0x03)a__STM32F1_CMSIS_VERSION_SUB2 (0x03)b__STM32F1_CMSIS_VERSION_RC (0x00)c__STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24) |(__STM32F1_CMSIS_VERSION_SUB1 << 16) |(__STM32F1_CMSIS_VERSION_SUB2 << 8 ) |(__STM32F1_CMSIS_VERSION_RC))<03><01>IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))<01>SET_BIT(REG,BIT) ((REG) |= (BIT))<01>CLEAR_BIT(REG,BIT) ((REG) &= ~(BIT))<01>READ_BIT(REG,BIT) ((REG) & (BIT))<01>CLEAR_REG(REG) ((REG) = (0x0))<01>WRITE_REG(REG,VAL) ((REG) = (VAL))<01>READ_REG(REG) ((REG))<01>MODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))<01>POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))<01>ATOMIC_SET_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)<01>ATOMIC_CLEAR_BIT(REG,BIT) do { uint32_t val; do { val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)<01>ATOMIC_MODIFY_REG(REG,CLEARMSK,SETMASK) do { uint32_t val; do { val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); } while(0)<01>ATOMIC_SETH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)<01>ATOMIC_CLEARH_BIT(REG,BIT) do { uint16_t val; do { val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)<01>ATOMIC_MODIFYH_REG(REG,CLEARMSK,SETMASK) do { uint16_t val; do { val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); } while(0)<03><00><00> ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx.hstm32f103xe.hstm32f1xx_hal.hl
../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<13>RESET SET PFlagStatus<12><01>PITStatus<12><01><13>DISABLE ENABLE PFunctionalState <01><13>SUCCESS ERROR PErrorStatus><01><00><00><00>STM32_HAL_LEGACY $AES_FLAG_RDERR CRYP_FLAG_RDERR%AES_FLAG_WRERR CRYP_FLAG_WRERR&AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF'AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR(AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR0ADC_RESOLUTION12b ADC_RESOLUTION_12B1ADC_RESOLUTION10b ADC_RESOLUTION_10B2ADC_RESOLUTION8b ADC_RESOLUTION_8B3ADC_RESOLUTION6b ADC_RESOLUTION_6B4OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN5OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED6EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV7EOC_SEQ_CONV ADC_EOC_SEQ_CONV8EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV9REGULAR_GROUP ADC_REGULAR_GROUP:INJECTED_GROUP ADC_INJECTED_GROUP;REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP<AWD_EVENT ADC_AWD_EVENT=AWD1_EVENT ADC_AWD1_EVENT>AWD2_EVENT ADC_AWD2_EVENT?AWD3_EVENT ADC_AWD3_EVENT@OVR_EVENT ADC_OVR_EVENTAJQOVF_EVENT ADC_JQOVF_EVENTBALL_CHANNELS ADC_ALL_CHANNELSCREGULAR_CHANNELS ADC_REGULAR_CHANNELSDINJECTED_CHANNELS ADC_INJECTED_CHANNELSESYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSORFSYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINTGADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1HADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2IADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4JADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6KADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8LADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGOMADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2NADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGOOADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4PADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGOQADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11RADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1SADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONETADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISINGUADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLINGVADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLINGWADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5YHAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSYZHAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY[HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC\HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC]HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL^HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL_HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1l__HAL_CEC_GET_IT __HAL_CEC_GET_FLAGuCOMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLEvCOMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLEwCOMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1xCOMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2yCOMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3zCOMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4{COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5|COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6}COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7<01>COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR<01>__HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig<01>CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE<01>CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE<01>DAC1_CHANNEL_1 DAC_CHANNEL_1<01>DAC1_CHANNEL_2 DAC_CHANNEL_2<01>DAC2_CHANNEL_1 DAC_CHANNEL_1<01>DAC_WAVE_NONE 0x00000000U<01>DAC_WAVE_NOISE DAC_CR_WAVE1_0<01>DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1<01>DAC_WAVEGENERATION_NONE DAC_WAVE_NONE<01>DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE<01>DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE<01>HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2<01>HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4<01>HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5<01>HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4<01>HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
USART_CLOCK_DISABLED USART_CLOCK_DISABLE<01>
USART_CLOCK_ENABLED USART_CLOCK_ENABLE<01>
USARTNACK_ENABLED USART_NACK_ENABLE<01>
USARTNACK_DISABLED USART_NACK_DISABLE<01>
CFR_BASE WWDG_CFR_BASE<01>
CAN_FilterFIFO0 CAN_FILTER_FIFO0<01>
CAN_FilterFIFO1 CAN_FILTER_FIFO1<01>
CAN_IT_RQCP0 CAN_IT_TME<01>
CAN_IT_RQCP1 CAN_IT_TME<01>
CAN_IT_RQCP2 CAN_IT_TME<01>
INAK_TIMEOUT CAN_TIMEOUT_VALUE<01>
SLAK_TIMEOUT CAN_TIMEOUT_VALUE<01>
CAN_TXSTATUS_FAILED ((uint8_t)0x00U)<01>
CAN_TXSTATUS_OK ((uint8_t)0x01U)<01>
CAN_TXSTATUS_PENDING ((uint8_t)0x02U)<01>
VLAN_TAG ETH_VLAN_TAG<01>
MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD<01>
MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD<01>
JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD<01>
MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK<01>
MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK<01>
MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK<01>
DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK<01>
ETH_MMCCR 0x00000100U<01>
ETH_MMCRIR 0x00000104U<01>
ETH_MMCTIR 0x00000108U<01>
ETH_MMCRIMR 0x0000010CU<01>
ETH_MMCTIMR 0x00000110U<01>
ETH_MMCTGFSCCR 0x0000014CU<01>
ETH_MMCTGFMSCCR 0x00000150U<01>
ETH_MMCTGFCR 0x00000168U<01>
ETH_MMCRFCECR 0x00000194U<01>
ETH_MMCRFAECR 0x00000198U<01>
ETH_MMCRGUFCR 0x000001C4U<01>
ETH_MAC_TXFIFO_FULL 0x02000000U<01>
ETH_MAC_TXFIFONOT_EMPTY 0x01000000U<01>
ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U<01>
ETH_MAC_TXFIFO_IDLE 0x00000000U<01>
ETH_MAC_TXFIFO_READ 0x00100000U<01>
ETH_MAC_TXFIFO_WAITING 0x00200000U<01>
ETH_MAC_TXFIFO_WRITING 0x00300000U<01>
ETH_MAC_TRANSMISSION_PAUSE 0x00080000U<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U<01>
ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U<01>
ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U<01>
ETH_MAC_RXFIFO_EMPTY 0x00000000U<01>
ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U<01>
ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U<01>
ETH_MAC_RXFIFO_FULL 0x00000300U<01>
ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U<01>
ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U<01>
ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U<01>
ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U<01>
ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U<01>
ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U<01>
ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U<01>
HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR<01>
DCMI_IT_OVF DCMI_IT_OVR<01>
DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI<01>
DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI<01>
HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop<01>
HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop<01>
HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop<01> HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback<01> HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef<01> HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef<01> HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish<01> HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish<01> HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish<01> HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish<01> HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1<01> HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224<01> HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256<01> HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5<01> HASH_AlgoMode_HASH HASH_ALGOMODE_HASH<01> HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC<01> HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY<01> HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY<01> HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode<01> HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode<01> HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode<01> HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode<01> HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode<01> HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode<01> HAL_DBG_LowPowerConfig(Periph,cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))<01> HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect<01> HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())<01> HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())<01> HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())<01> HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())<01> FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram<01> FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown<01> FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown<01> HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock<01> HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock<01> HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase<01> HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program<01> HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter<01> HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter<01> HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter<01> HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter<01> HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus,cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))<01> HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT<01> HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT<01> HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT<01> HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT<01> HAL_PWR_PVDConfig HAL_PWR_ConfigPVD<01> HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg<01> HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown<01> HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor<01> HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg<01> HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown<01> HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor<01> HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler<01> HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD<01> HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler<01> HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback<01> HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive<01> HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive<01> HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC<01> HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC<01> HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM<01> PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL<01> PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING<01> PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING<01> PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING<01> PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING<01> PWR_MODE_EVENT_FALLING
../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<00><00><00>__stddef_h __ARMCLIB_VERSION 5060044__STDDEF_DECLS __CLIBNS __CLIBNS SNULLTNULL 0[offsetof(t,memb) ((__CLIBNS size_t)__INTADDR__(&(((t *)0)->memb)))XM D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.h D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] intunsigned intunsigned shortlong doublePptrdiff_t<12>&Psize_t<12>.Pwchar_t<12>@Pmax_align_t<12>_<00><00><00>__STM32F1xx_HAL_DEF  9HAL_MAX_DELAY 0xFFFFFFFFU;HAL_IS_BIT_SET(REG,BIT) (((REG) & (BIT)) != 0U)<HAL_IS_BIT_CLR(REG,BIT) (((REG) & (BIT)) == 0U)>__HAL_LINKDMA(__HANDLE__,__PPP_DMA_FIELD__,__DMA_HANDLE__) do{ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); (__DMA_HANDLE__).Parent = (__HANDLE__); } while(0U)DUNUSED(X) (void)XU__HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)[__HAL_LOCK(__HANDLE__) do{ if((__HANDLE__)->Lock == HAL_LOCKED) { return HAL_BUSY; } else { (__HANDLE__)->Lock = HAL_LOCKED; } }while (0U)g__HAL_UNLOCK(__HANDLE__) do{ (__HANDLE__)->Lock = HAL_UNLOCKED; }while (0U)<01>__ALIGN_END <01>__ALIGN_BEGIN __align(4)<01>__RAM_FUNC <01>__NOINLINE __attribute__ ( (noinline) )<00><00> ../Drivers/STM32F1xx_HAL_Driver/Inc/../Drivers/CMSIS/Device/ST/STM32F1xx/Include/D:\SOFTWARE\Keil_v5\ARM\ARMCC\Bin\..\include\stm32f1xx_hal_def.hstm32f1xx.hLegacy/stm32_hal_legacy.hstddef.h\
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<13>HAL_OK HAL_ERROR HAL_BUSY HAL_TIMEOUT PHAL_StatusTypeDef<12>-<13>HAL_UNLOCKED HAL_LOCKED PHAL_LockTypeDef"6<00><00><00>__STM32F1xx_HAL_RCC_EX_H :CR_REG_INDEX ((uint8_t)1)UIS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2))eIS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || ((__MUL__) == RCC_PLL_MUL16))nIS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))tIS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))<01>IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)<01>IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)<01>IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))<01>IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))<01>RCC_PERIPHCLK_RTC 0x00000001U<01>RCC_PERIPHCLK_ADC 0x00000002U<01>RCC_PERIPHCLK_I2S2 0x00000004U<01>RCC_PERIPHCLK_I2S3 0x00000008U<01>RCC_PERIPHCLK_USB 0x00000010U<01>RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2<01>RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4<01>RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6<01>RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8<01>RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U<01>RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U<01>RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE<01>RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U<01>RCC_HSE_PREDIV_DIV1 0x00000000U<01>RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE<01>RCC_PLL_MUL2 RCC_CFGR_PLLMULL2<01>RCC_PLL_MUL3 RCC_CFGR_PLLMULL3<01>RCC_PLL_MUL4 RCC_CFGR_PLLMULL4<01>RCC_PLL_MUL5 RCC_CFGR_PLLMULL5<01>RCC_PLL_MUL6 RCC_CFGR_PLLMULL6<01>RCC_PLL_MUL7 RCC_CFGR_PLLMULL7<01>RCC_PLL_MUL8 RCC_CFGR_PLLMULL8<01>RCC_PLL_MUL9 RCC_CFGR_PLLMULL9<01>RCC_PLL_MUL10 RCC_CFGR_PLLMULL10<01>RCC_PLL_MUL11 RCC_CFGR_PLLMULL11<01>RCC_PLL_MUL12 RCC_CFGR_PLLMULL12<01>RCC_PLL_MUL13 RCC_CFGR_PLLMULL13<01>RCC_PLL_MUL14 RCC_CFGR_PLLMULL14<01>RCC_PLL_MUL15 RCC_CFGR_PLLMULL15<01>RCC_PLL_MUL16 RCC_CFGR_PLLMULL16<01>RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)<01>RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)<01>RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)<01>RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)<01>RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)<01>__HAL_RCC_DMA2_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); UNUSED(tmpreg); } while(0U)<01>__HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))<01>__HAL_RCC_FSMC_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); UNUSED(tmpreg); } while(0U)<01>__HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))<01>__HAL_RCC_SDIO_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN); tmpreg = READ_BIT(RCC->AHBE
__HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)<01>
__HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)<01>
__HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)<01>
__HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)<01>
__HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)<01>
__HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)<01>
__HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)<01>
__HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)<01>
__HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)<01>
__HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)<01>
__HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)<01>
__HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)<01> __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))<01> __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))<01> __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))<01> __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))<01> __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))<01> __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))<01> __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))<01> __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))<01> __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))<01> __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))<01> __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))<01> __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))<01> __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))<01> __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))<01> __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))<01> __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))<01> __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))<01> __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))<01> __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))<01> __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))<01> __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))<01> __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))<01> __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))<01> __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))<01> __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))<01> __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))<01> __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))<01> __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))<01> __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))<01> __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))<01> __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))<01> __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))<01> __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))<01> __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))<01> __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))<01> __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST))<01> __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))<01> __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))<01> __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))<01> __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)<01> __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))<01> __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))<01> __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))<01> __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))ti ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.hstm32f1xx_hal_def.hd
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM*<2A>(OscillatorTypeb#HSEStateb#HSEPredivValueb#LSEStateb# HSIStateb#HSICalibrationValueb#LSIStateb#PLL #PRCC_OscInitTypeDef<12><01>*<2A>PeriphClockSelectionb#RTCClockSelectionb#AdcClockSelectionb#I2s2ClockSelectionb# I2s3ClockSelectionb#UsbClockSelectionb#PRCC_PeriphCLKInitTypeDef<12><01><00><00><00>__STM32F1xx_HAL_RCC_H _RCC_PLLSOURCE_HSI_DIV2 0x00000000U`RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRCiRCC_OSCILLATORTYPE_NONE 0x00000000UjRCC_OSCILLATORTYPE_HSE 0x00000001UkRCC_OSCILLATORTYPE_HSI 0x00000002UlRCC_OSCILLATORTYPE_LSE 0x00000004UmRCC_OSCILLATORTYPE_LSI 0x00000008UuRCC_HSE_OFF 0x00000000UvRCC_HSE_ON RCC_CR_HSEONwRCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))RCC_LSE_OFF 0x00000000U<01>RCC_LSE_ON RCC_BDCR_LSEON<01>RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))<01>RCC_HSI_OFF 0x00000000U<01>RCC_HSI_ON RCC_CR_HSION<01>RCC_HSICALIBRATION_DEFAULT 0x10U<01>RCC_LSI_OFF 0x00000000U<01>RCC_LSI_ON RCC_CSR_LSION<01>RCC_PLL_NONE 0x00000000U<01>RCC_PLL_OFF 0x00000001U<01>RCC_PLL_ON 0x00000002U<01>RCC_CLOCKTYPE_SYSCLK 0x00000001U<01>RCC_CLOCKTYPE_HCLK 0x00000002U<01>RCC_CLOCKTYPE_PCLK1 0x00000004U<01>RCC_CLOCKTYPE_PCLK2 0x00000008U<01>RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI<01>RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE<01>RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL<01>RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI<01>RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE<01>RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL<01>RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1<01>RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2<01>RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4<01>RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8<01>RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16<01>RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64<01>RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128<01>RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256<01>RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512<01>RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1<01>RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2<01>RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4<01>RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8<01>RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16<01>RCC_RTCCLKSOURCE_NO_CLK 0x00000000U<01>RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE<01>RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI<01>RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE<01>RCC_MCO1 0x00000000U<01>RCC_MCO RCC_MCO1<01>RCC_MCODIV_1 0x00000000U<01>RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF)<01>RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF)<01>RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF)<01>RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF)<01>RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF)<01>RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF)<01>RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos))<01>RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos))<01>RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos))<01>RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos))<01>RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos))<01>RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos))<01>RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos))<01>RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos))<01>RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos))<01>RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos))<01>RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos))<01>__HAL_RCC_DMA1_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); UNUSED(tmpreg); } while(0U)<01>__HAL_RCC_SRAM_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN); tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN); UNUSED(tmpreg); } while(0U)<01>__HAL_RCC_FLITF_CLK_ENABLE() do { __IO uint32_t tmpreg; SET_BIT(RCC->AH
RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))<01>
RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))<01>
RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))<01>
CR_REG_INDEX ((uint8_t)1)<01>
BDCR_REG_INDEX ((uint8_t)2)<01>
CSR_REG_INDEX ((uint8_t)3)<01>
RCC_FLAG_MASK ((uint8_t)0x1F)<01>
__HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE<01>
__HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE<01>
__HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET<01>
__HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET<01>
IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || ((__SOURCE__) == RCC_PLLSOURCE_HSE))<01>
IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))<01>
IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || ((__HSE__) == RCC_HSE_BYPASS))<01>
IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS))<01>
IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))<01>
IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)<01>
IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))<01>
IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON))<01>
IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))<01>
IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))<01>
IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))<01>
IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512))<01>
IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || ((__PCLK__) == RCC_HCLK_DIV16))<01>
IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)<01>
IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))<01>
IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))<00><00> ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.hstm32f1xx_hal_def.hstm32f1xx_hal_rcc_ex.h<01>
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM*<2A> PLLStateb#PLLSourceb#PLLMULb#PRCC_PLLInitTypeDef<12>;*<2A>ClockTypeb#SYSCLKSourceb#AHBCLKDividerb#APB1CLKDividerb# APB2CLKDividerb#PRCC_ClkInitTypeDef&P<00><00><00>STM32F1xx_HAL_GPIO_EX_H 6AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX07AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX18AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX29AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3:AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4;AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5<AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6=AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7>AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8?AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9@AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10AAFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11BAFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12CAFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13DAFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14EAFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15GIS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || ((__PIN__) == AFIO_EVENTOUT_PIN_1) || ((__PIN__) == AFIO_EVENTOUT_PIN_2) || ((__PIN__) == AFIO_EVENTOUT_PIN_3) || ((__PIN__) == AFIO_EVENTOUT_PIN_4) || ((__PIN__) == AFIO_EVENTOUT_PIN_5) || ((__PIN__) == AFIO_EVENTOUT_PIN_6) || ((__PIN__) == AFIO_EVENTOUT_PIN_7) || ((__PIN__) == AFIO_EVENTOUT_PIN_8) || ((__PIN__) == AFIO_EVENTOUT_PIN_9) || ((__PIN__) == AFIO_EVENTOUT_PIN_10) || ((__PIN__) == AFIO_EVENTOUT_PIN_11) || ((__PIN__) == AFIO_EVENTOUT_PIN_12) || ((__PIN__) == AFIO_EVENTOUT_PIN_13) || ((__PIN__) == AFIO_EVENTOUT_PIN_14) || ((__PIN__) == AFIO_EVENTOUT_PIN_15))_AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA`AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PBaAFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PCbAFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PDcAFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PEeIS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || ((__PORT__) == AFIO_EVENTOUT_PORT_B) || ((__PORT__) == AFIO_EVENTOUT_PORT_C) || ((__PORT__) == AFIO_EVENTOUT_PORT_D) || ((__PORT__) == AFIO_EVENTOUT_PORT_E))|__HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP)<01>__HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP)<01>__HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP)<01>__HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP)<01>__HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP)<01>__HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP)<01>__HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP)<01>__HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP)<01>__HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)<01>__HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)<01>__HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)<01>__HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)<01>__HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)<01>__HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)<01>__HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)<01>__HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP)<01>__HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP)<01>__HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)<01>__HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MA
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<00><00><00>STM32F1xx_HAL_GPIO_H SGPIO_PIN_0 ((uint16_t)0x0001)TGPIO_PIN_1 ((uint16_t)0x0002)UGPIO_PIN_2 ((uint16_t)0x0004)VGPIO_PIN_3 ((uint16_t)0x0008)WGPIO_PIN_4 ((uint16_t)0x0010)XGPIO_PIN_5 ((uint16_t)0x0020)YGPIO_PIN_6 ((uint16_t)0x0040)ZGPIO_PIN_7 ((uint16_t)0x0080)[GPIO_PIN_8 ((uint16_t)0x0100)\GPIO_PIN_9 ((uint16_t)0x0200)]GPIO_PIN_10 ((uint16_t)0x0400)^GPIO_PIN_11 ((uint16_t)0x0800)_GPIO_PIN_12 ((uint16_t)0x1000)`GPIO_PIN_13 ((uint16_t)0x2000)aGPIO_PIN_14 ((uint16_t)0x4000)bGPIO_PIN_15 ((uint16_t)0x8000)cGPIO_PIN_All ((uint16_t)0xFFFF)eGPIO_PIN_MASK 0x0000FFFFutGPIO_MODE_INPUT 0x00000000uuGPIO_MODE_OUTPUT_PP 0x00000001uvGPIO_MODE_OUTPUT_OD 0x00000011uwGPIO_MODE_AF_PP 0x00000002uxGPIO_MODE_AF_OD 0x00000012uyGPIO_MODE_AF_INPUT GPIO_MODE_INPUT{GPIO_MODE_ANALOG 0x00000003u}GPIO_MODE_IT_RISING 0x10110000u~GPIO_MODE_IT_FALLING 0x10210000uGPIO_MODE_IT_RISING_FALLING 0x10310000u<01>GPIO_MODE_EVT_RISING 0x10120000u<01>GPIO_MODE_EVT_FALLING 0x10220000u<01>GPIO_MODE_EVT_RISING_FALLING 0x10320000u<01>GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1)<01>GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0)<01>GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0)<01>GPIO_NOPULL 0x00000000u<01>GPIO_PULLUP 0x00000001u<01>GPIO_PULLDOWN 0x00000002u<01>__HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))<01>__HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))<01>__HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))<01>__HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))<01>__HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))<03><01>IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))<01>IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00u) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00u))<01>IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) || ((MODE) == GPIO_MODE_OUTPUT_PP) || ((MODE) == GPIO_MODE_OUTPUT_OD) || ((MODE) == GPIO_MODE_AF_PP) || ((MODE) == GPIO_MODE_AF_OD) || ((MODE) == GPIO_MODE_IT_RISING) || ((MODE) == GPIO_MODE_IT_FALLING) || ((MODE) == GPIO_MODE_IT_RISING_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING) || ((MODE) == GPIO_MODE_EVT_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING_FALLING) || ((MODE) == GPIO_MODE_ANALOG))<01>IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))<01>IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || ((PULL) == GPIO_PULLDOWN))<00><00> ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.hstm32f1xx_hal_def.hstm32f1xx_hal_gpio_ex.hd
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM*<2A>Pinb#Modeb#Pullb#Speedb# PGPIO_InitTypeDef<12><<13>GPIO_PIN_RESET GPIO_PIN_SET PGPIO_PinState(E<00><00><00>STM32F1xx_HAL_EXTI_H [EXTI_LINE_0 (EXTI_GPIO | 0x00u)\EXTI_LINE_1 (EXTI_GPIO | 0x01u)]EXTI_LINE_2 (EXTI_GPIO | 0x02u)^EXTI_LINE_3 (EXTI_GPIO | 0x03u)_EXTI_LINE_4 (EXTI_GPIO | 0x04u)`EXTI_LINE_5 (EXTI_GPIO | 0x05u)aEXTI_LINE_6 (EXTI_GPIO | 0x06u)bEXTI_LINE_7 (EXTI_GPIO | 0x07u)cEXTI_LINE_8 (EXTI_GPIO | 0x08u)dEXTI_LINE_9 (EXTI_GPIO | 0x09u)eEXTI_LINE_10 (EXTI_GPIO | 0x0Au)fEXTI_LINE_11 (EXTI_GPIO | 0x0Bu)gEXTI_LINE_12 (EXTI_GPIO | 0x0Cu)hEXTI_LINE_13 (EXTI_GPIO | 0x0Du)iEXTI_LINE_14 (EXTI_GPIO | 0x0Eu)jEXTI_LINE_15 (EXTI_GPIO | 0x0Fu)kEXTI_LINE_16 (EXTI_CONFIG | 0x10u)lEXTI_LINE_17 (EXTI_CONFIG | 0x11u)nEXTI_LINE_18 (EXTI_CONFIG | 0x12u){EXTI_MODE_NONE 0x00000000u|EXTI_MODE_INTERRUPT 0x00000001u}EXTI_MODE_EVENT 0x00000002u<01>EXTI_TRIGGER_NONE 0x00000000u<01>EXTI_TRIGGER_RISING 0x00000001u<01>EXTI_TRIGGER_FALLING 0x00000002u<01>EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)<01>EXTI_GPIOA 0x00000000u<01>EXTI_GPIOB 0x00000001u<01>EXTI_GPIOC 0x00000002u<01>EXTI_GPIOD 0x00000003u<01>EXTI_GPIOE 0x00000004u<01>EXTI_GPIOF 0x00000005u<01>EXTI_GPIOG 0x00000006u<01>EXTI_PROPERTY_SHIFT 24u<01>EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)<01>EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)<01>EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)<01>EXTI_PIN_MASK 0x0000001Fu<01>EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)<01>EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)<01>EXTI_LINE_NB 19UL<01>IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))<01>IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))<01>IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)<01>IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)<01>IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)<01>IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) || ((__PORT__) == EXTI_GPIOD) || ((__PORT__) == EXTI_GPIOE) || ((__PORT__) == EXTI_GPIOF) || ((__PORT__) == EXTI_GPIOG))<01>IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)pg ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.hstm32f1xx_hal_def.h<01>
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<13>HAL_EXTI_COMMON_CB_ID PEXTI_CallbackIDTypeDef<12>4*<2A>Lineb#O<>"!PendingCallback%#PEXTI_HandleTypeDef=*<2A>Lineb#Modeb#Triggerb#GPIOSelb# PEXTI_ConfigTypeDef[M<00><00><00>__STM32F1xx_HAL_DMA_EX_H 9__HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 : DMA_FLAG_TC5)L__HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 : DMA_FLAG_HT5)___HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 : DMA_FLAG_TE5)r__HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 : ((uint32_t)((__HANDLE__)->Instance)
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<00><00><00>__STM32F1xx_HAL_DMA_H <01>HAL_DMA_ERROR_NONE 0x00000000U<01>HAL_DMA_ERROR_TE 0x00000001U<01>HAL_DMA_ERROR_NO_XFER 0x00000004U<01>HAL_DMA_ERROR_TIMEOUT 0x00000020U<01>HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U<01>DMA_PERIPH_TO_MEMORY 0x00000000U<01>DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR)<01>DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM)<01>DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC)<01>DMA_PINC_DISABLE 0x00000000U<01>DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC)<01>DMA_MINC_DISABLE 0x00000000U<01>DMA_PDATAALIGN_BYTE 0x00000000U<01>DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0)<01>DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1)<01>DMA_MDATAALIGN_BYTE 0x00000000U<01>DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0)<01>DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1)<01>DMA_NORMAL 0x00000000U<01>DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC)<01>DMA_PRIORITY_LOW 0x00000000U<01>DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0)<01>DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1)<01>DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL)<01>DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)<01>DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)<01>DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)<01>DMA_FLAG_GL1 0x00000001U<01>DMA_FLAG_TC1 0x00000002U<01>DMA_FLAG_HT1 0x00000004U<01>DMA_FLAG_TE1 0x00000008U<01>DMA_FLAG_GL2 0x00000010U<01>DMA_FLAG_TC2 0x00000020U<01>DMA_FLAG_HT2 0x00000040U<01>DMA_FLAG_TE2 0x00000080U<01>DMA_FLAG_GL3 0x00000100U<01>DMA_FLAG_TC3 0x00000200U<01>DMA_FLAG_HT3 0x00000400U<01>DMA_FLAG_TE3 0x00000800U<01>DMA_FLAG_GL4 0x00001000U<01>DMA_FLAG_TC4 0x00002000U<01>DMA_FLAG_HT4 0x00004000U<01>DMA_FLAG_TE4 0x00008000U<01>DMA_FLAG_GL5 0x00010000U<01>DMA_FLAG_TC5 0x00020000U<01>DMA_FLAG_HT5 0x00040000U<01>DMA_FLAG_TE5 0x00080000U<01>DMA_FLAG_GL6 0x00100000U<01>DMA_FLAG_TC6 0x00200000U<01>DMA_FLAG_HT6 0x00400000U<01>DMA_FLAG_TE6 0x00800000U<01>DMA_FLAG_GL7 0x01000000U<01>DMA_FLAG_TC7 0x02000000U<01>DMA_FLAG_HT7 0x04000000U<01>DMA_FLAG_TE7 0x08000000U<01>__HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)<01>__HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))<01>__HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))<01>__HAL_DMA_ENABLE_IT(__HANDLE__,__INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))<01>__HAL_DMA_DISABLE_IT(__HANDLE__,__INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))<01>__HAL_DMA_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)<01>__HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)<03><01>IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || ((DIRECTION) == DMA_MEMORY_TO_MEMORY))<01>IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))<01>IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || ((STATE) == DMA_PINC_DISABLE))<01>IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || ((STATE) == DMA_MINC_DISABLE))<01>IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || ((SIZE) == DMA_PDATAALIGN_HALFWORD) || ((SIZE) == DMA_PDATAALIGN_WORD))<01>IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || ((SIZE) == DMA_MDATAALIGN_HALFWORD) || ((SIZE) == DMA_MDATAALIGN_WORD ))<01>IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || ((MODE) == DMA_CIRCULAR))<01>IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_HIGH) || ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))<00><00> ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.hstm32f1xx_hal_def.hstm32f1xx_hal_dma_ex.hp
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARMuvoid"<12>":tb"e PDMA_InitTypeDef~IPHAL_DMA_StateTypeDefTPHAL_DMA_LevelCompleteTypeDefr]PHAL_DMA_CallbackIDTypeDef<12>jPDMA_HandleTypeDef:<01>*<2A>Directionb#PeriphIncb#MemIncb#PeriphDataAlignmentb# MemDataAlignmentb#Modeb#Priorityb#<13>HAL_DMA_STATE_RESET HAL_DMA_STATE_READY HAL_DMA_STATE_BUSY HAL_DMA_STATE_TIMEOUT <13>HAL_DMA_FULL_TRANSFER HAL_DMA_HALF_TRANSFER <13>HAL_DMA_XFER_CPLT_CB_ID HAL_DMA_XFER_HALFCPLT_CB_ID HAL_DMA_XFER_ERROR_CB_ID HAL_DMA_XFER_ABORT_CB_ID HAL_DMA_XFER_ALL_CB_ID )<29>__DMA_HandleTypeDefDInstancek#Init<12>#LockE# State#!Parent<12>#$O<>%<12>"<12>XferCpltCallback<12>#(O<>%<12>"<12>XferHalfCpltCallback<12>#,O<>%<12>"<12>XferErrorCallback<12>#0O<30>%<12>"XferAbortCallback#4ErrorCode<12>#8DmaBaseAddress<12>#<ChannelIndexb#@"- <00><00><00>__STM32F1xx_HAL_CORTEX_H ZNVIC_PRIORITYGROUP_0 0x00000007U\NVIC_PRIORITYGROUP_1 0x00000006U^NVIC_PRIORITYGROUP_2 0x00000005U`NVIC_PRIORITYGROUP_3 0x00000004UbNVIC_PRIORITYGROUP_4 0x00000003UkSYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000UlSYSTICK_CLKSOURCE_HCLK 0x00000004U<01>IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || ((GROUP) == NVIC_PRIORITYGROUP_4))<01>IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)<01>IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)<01>IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)<01>IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))ti ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.hstm32f1xx_hal_def.h<01>
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<00><00><00>__STM32F1xx_HAL_FLASH_EX_H +FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U,OBR_REG_INDEX 1U-SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))7IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))9IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)));IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))=IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))?IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))AIS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))CIS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))EIS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))[IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU)))mIS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))tIS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))<01>IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU))))<01>FLASH_PAGE_SIZE 0x800U<01>FLASH_TYPEERASE_PAGES 0x00U<01>FLASH_TYPEERASE_MASSERASE 0x02U<01>FLASH_BANK_1 1U<01>OPTIONBYTE_WRP 0x01U<01>OPTIONBYTE_RDP 0x02U<01>OPTIONBYTE_USER 0x04U<01>OPTIONBYTE_DATA 0x08U<01>OB_WRPSTATE_DISABLE 0x00U<01>OB_WRPSTATE_ENABLE 0x01U<01>OB_WRP_PAGES0TO1 0x00000001U<01>OB_WRP_PAGES2TO3 0x00000002U<01>OB_WRP_PAGES4TO5 0x00000004U<01>OB_WRP_PAGES6TO7 0x00000008U<01>OB_WRP_PAGES8TO9 0x00000010U<01>OB_WRP_PAGES10TO11 0x00000020U<01>OB_WRP_PAGES12TO13 0x00000040U<01>OB_WRP_PAGES14TO15 0x00000080U<01>OB_WRP_PAGES16TO17 0x00000100U<01>OB_WRP_PAGES18TO19 0x00000200U<01>OB_WRP_PAGES20TO21 0x00000400U<01>OB_WRP_PAGES22TO23 0x00000800U<01>OB_WRP_PAGES24TO25 0x00001000U<01>OB_WRP_PAGES26TO27 0x00002000U<01>OB_WRP_PAGES28TO29 0x00004000U<01>OB_WRP_PAGES30TO31 0x00008000U<01>OB_WRP_PAGES32TO33 0x00010000U<01>OB_WRP_PAGES34TO35 0x00020000U<01>OB_WRP_PAGES36TO37 0x00040000U<01>OB_WRP_PAGES38TO39 0x00080000U<01>OB_WRP_PAGES40TO41 0x00100000U<01>OB_WRP_PAGES42TO43 0x00200000U<01>OB_WRP_PAGES44TO45 0x00400000U<01>OB_WRP_PAGES46TO47 0x00800000U<01>OB_WRP_PAGES48TO49 0x01000000U<01>OB_WRP_PAGES50TO51 0x02000000U<01>OB_WRP_PAGES52TO53 0x04000000U<01>OB_WRP_PAGES54TO55 0x08000000U<01>OB_WRP_PAGES56TO57 0x10000000U<01>OB_WRP_PAGES58TO59 0x20000000U<01>OB_WRP_PAGES60TO61 0x40000000U<01>OB_WRP_PAGES62TO127 0x80000000U<01>OB_WRP_PAGES62TO255 0x80000000U<01>OB_WRP_PAGES62TO511 0x80000000U<01>OB_WRP_ALLPAGES 0xFFFFFFFFU<01>OB_WRP_PAGES0TO15MASK 0x000000FFU<01>OB_WRP_PAGES16TO31MASK 0x0000FF00U<01>OB_WRP_PAGES32TO47MASK 0x00FF0000U<01>OB_WRP_PAGES48TO255MASK 0xFF000000U<01>OB_RDP_LEVEL_0 ((uint8_t)0xA5)<01>OB_RDP_LEVEL_1 ((uint8_t)0x00)<01>OB_IWDG_SW ((uint16_t)0x0001)<01>OB_IWDG_HW ((uint16_t)0x0000)<01>OB_STOP_NO_RST ((uint16_t)0x0002)<01>OB_STOP_RST ((uint16_t)0x0000)<01>OB_STDBY_NO_RST ((uint16_t)0x0004)<01>OB_STDBY_RST ((uint16_t)0x0000)<01>OB_DATA_ADDRESS_DATA0 0x1FFFF804U<01>OB_DATA_ADDRESS_DATA1 0x1FFFF806U<01>FLASH_FLAG_BSY FLASH_SR_BSY<01>FLASH_FLAG_PGERR FLASH_SR_PGERR<01>FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR<01>FLASH_FLAG_EOP FLASH_SR_EOP<01>FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR))<01>FLASH_IT_EOP FLASH_CR_EOPIE<01>FLASH_IT_ERR FLASH_CR_ERRIE<01>__HAL_FLASH_EN
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM*<2A>TypeEraseb#Banksb#PageAddressb#NbPagesb# PFLASH_EraseInitTypeDef<12><01>*<2A>OptionTypeb#WRPStateb#WRPPageb#Banksb# RDPLevelC#USERConfigC#DATAAddressb#DATADataC#PFLASH_OBProgramInitTypeDefC<01><00><00><00>__STM32F1xx_HAL_FLASH_H *FLASH_TIMEOUT_VALUE 50000U3IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || ((VALUE) == FLASH_TYPEPROGRAM_WORD) || ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))8IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || ((__LATENCY__) == FLASH_LATENCY_1) || ((__LATENCY__) == FLASH_LATENCY_2))uHAL_FLASH_ERROR_NONE 0x00UvHAL_FLASH_ERROR_PROG 0x01UwHAL_FLASH_ERROR_WRP 0x02UxHAL_FLASH_ERROR_OPTV 0x04U<01>FLASH_TYPEPROGRAM_HALFWORD 0x01U<01>FLASH_TYPEPROGRAM_WORD 0x02U<01>FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U<01>FLASH_LATENCY_0 0x00000000U<01>FLASH_LATENCY_1 FLASH_ACR_LATENCY_0<01>FLASH_LATENCY_2 FLASH_ACR_LATENCY_1<01>__HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)<01>__HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))<01>__HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))<01>__HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))<01>__HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)<01>__HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))<03><00><00> ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.hstm32f1xx_hal_def.hstm32f1xx_hal_flash_ex.h(
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<13>FLASH_PROC_NONE FLASH_PROC_PAGEERASE FLASH_PROC_MASSERASE FLASH_PROC_PROGRAMHALFWORD FLASH_PROC_PROGRAMWORD FLASH_PROC_PROGRAMDOUBLEWORD PFLASH_ProcedureTypeDef<12>S*<2A> ProcedureOnGoing<12>#DataRemaining#Address#Data#LockE#ErrorCode#tttbtrPFLASH_ProcessTypeDef<12>f<00><00><00>__STM32F1xx_HAL_PWR_H EPWR_EXTI_LINE_PVD ((uint32_t)0x00010000)UPWR_PVDLEVEL_0 PWR_CR_PLS_2V2VPWR_PVDLEVEL_1 PWR_CR_PLS_2V3WPWR_PVDLEVEL_2 PWR_CR_PLS_2V4XPWR_PVDLEVEL_3 PWR_CR_PLS_2V5YPWR_PVDLEVEL_4 PWR_CR_PLS_2V6ZPWR_PVDLEVEL_5 PWR_CR_PLS_2V7[PWR_PVDLEVEL_6 PWR_CR_PLS_2V8\PWR_PVDLEVEL_7 PWR_CR_PLS_2V9ePWR_PVD_MODE_NORMAL 0x00000000UfPWR_PVD_MODE_IT_RISING 0x00010001UgPWR_PVD_MODE_IT_FALLING 0x00010002UhPWR_PVD_MODE_IT_RISING_FALLING 0x00010003UiPWR_PVD_MODE_EVENT_RISING 0x00020001UjPWR_PVD_MODE_EVENT_FALLING 0x00020002UkPWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003UvPWR_WAKEUP_PIN1 PWR_CSR_EWUPPWR_MAINREGULATOR_ON 0x00000000U<01>PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS<01>PWR_SLEEPENTRY_WFI ((uint8_t)0x01)<01>PWR_SLEEPENTRY_WFE ((uint8_t)0x02)<01>PWR_STOPENTRY_WFI ((uint8_t)0x01)<01>PWR_STOPENTRY_WFE ((uint8_t)0x02)<01>PWR_FLAG_WU PWR_CSR_WUF<01>PWR_FLAG_SB PWR_CSR_SBF<01>PWR_FLAG_PVDO PWR_CSR_PVDO<01>__HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))<01>__HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))<01>__HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)<01>__HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)<01>__HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)<01>__HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)<01>__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)<01>__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)<01>__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)<01>__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)<01>__HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();<01>__HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();<01>__HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))<01>__HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))<01>__HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)<01>IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))<01>IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL))<01>IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))<01>IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))<01>IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))<01>IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))pf ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.hstm32f1xx_hal_def.h 
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM*<2A>PVDLevelb#Modeb#PPWR_PVDTypeDef<12>7<00><00><00>STM32F1xx_HAL_TIM_EX_H ti ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.hstm32f1xx_hal_def.hT
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM*<2A>IC1Polarityb#IC1Prescalerb#IC1Filterb#Commutation_Delayb# PTIM_HallSensor_InitTypeDef<12>=<00><00><00>STM32F1xx_HAL_TIM_H <01>TIM_CLEARINPUTSOURCE_NONE 0x00000000U<01>TIM_CLEARINPUTSOURCE_ETR 0x00000001U<01>TIM_DMABASE_CR1 0x00000000U<01>TIM_DMABASE_CR2 0x00000001U<01>TIM_DMABASE_SMCR 0x00000002U<01>TIM_DMABASE_DIER 0x00000003U<01>TIM_DMABASE_SR 0x00000004U<01>TIM_DMABASE_EGR 0x00000005U<01>TIM_DMABASE_CCMR1 0x00000006U<01>TIM_DMABASE_CCMR2 0x00000007U<01>TIM_DMABASE_CCER 0x00000008U<01>TIM_DMABASE_CNT 0x00000009U<01>TIM_DMABASE_PSC 0x0000000AU<01>TIM_DMABASE_ARR 0x0000000BU<01>TIM_DMABASE_RCR 0x0000000CU<01>TIM_DMABASE_CCR1 0x0000000DU<01>TIM_DMABASE_CCR2 0x0000000EU<01>TIM_DMABASE_CCR3 0x0000000FU<01>TIM_DMABASE_CCR4 0x00000010U<01>TIM_DMABASE_BDTR 0x00000011U<01>TIM_DMABASE_DCR 0x00000012U<01>TIM_DMABASE_DMAR 0x00000013U<01>TIM_EVENTSOURCE_UPDATE TIM_EGR_UG<01>TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G<01>TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G<01>TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G<01>TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G<01>TIM_EVENTSOURCE_COM TIM_EGR_COMG<01>TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG<01>TIM_EVENTSOURCE_BREAK TIM_EGR_BG<01>TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U<01>TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P<01>TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)<01>TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP<01>TIM_ETRPOLARITY_NONINVERTED 0x00000000U<01>TIM_ETRPRESCALER_DIV1 0x00000000U<01>TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0<01>TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1<01>TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS<01>TIM_COUNTERMODE_UP 0x00000000U<01>TIM_COUNTERMODE_DOWN TIM_CR1_DIR<01>TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0<01>TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1<01>TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS<01>TIM_CLOCKDIVISION_DIV1 0x00000000U<01>TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0<01>TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1<01>TIM_OUTPUTSTATE_DISABLE 0x00000000U<01>TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E<01>TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U<01>TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE<01>TIM_OCFAST_DISABLE 0x00000000U<01>TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE<01>TIM_OUTPUTNSTATE_DISABLE 0x00000000U<01>TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE<01>TIM_OCPOLARITY_HIGH 0x00000000U<01>TIM_OCPOLARITY_LOW TIM_CCER_CC1P<01>TIM_OCNPOLARITY_HIGH 0x00000000U<01>TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP<01>TIM_OCIDLESTATE_SET TIM_CR2_OIS1<01>TIM_OCIDLESTATE_RESET 0x00000000U<01>TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N<01>TIM_OCNIDLESTATE_RESET 0x00000000U<01>TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING<01>TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING<01>TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE<01>TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING<01>TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING<01>TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0<01>TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1<01>TIM_ICSELECTION_TRC TIM_CCMR1_CC1S<01>TIM_ICPSC_DIV1 0x00000000U<01>TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0<01>TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1<01>TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC<01>TIM_OPMODE_SINGLE TIM_CR1_OPM<01>TIM_OPMODE_REPETITIVE 0x00000000U<01>TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0<01>TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1<01>TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)<01>TIM_IT_UPDATE TIM_DIER_UIE<01>TIM_IT_CC1 TIM_DIER_CC1IE<01>TIM_IT_CC2 TIM_DIER_CC2IE<01>TIM_IT_CC3 TIM_DIER_CC3IE<01>TIM_IT_CC4 TIM_DIER_CC4IE<01>TIM_IT_COM TIM_DIER_COMIE<01>TIM_IT_TRIGGER TIM_DIER_TIE<01>TIM_IT_BREAK TIM_DIER_BIE<01>TIM_COMMUTATION_TRGI TIM_CR2_CCUS<01>TIM_COMMUTATION_SOFTWARE 0x00000000U<01>TIM_DMA_UPDATE TIM_DIER_UDE<01>TIM_DMA_CC1 TIM_DIER_CC1DE<01>TIM_DMA_CC2 TIM_DIER_CC2DE<01>TIM_DMA_CC3 TIM_DIER_CC3DE<01>TIM_DMA_CC4 TIM_DIER_CC4DE<01>TIM_DMA_COM TIM_DIER_COMDE<01>TIM_DMA_TRIGGER TIM_DIER_TDE<01>TIM_FLAG_UPDATE TIM_SR_UIF<01>TIM_FLAG_CC1
__HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)<01>
__HAL_TIM_SET_AUTORELOAD(__HANDLE__,__AUTORELOAD__) do{ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); (__HANDLE__)->Init.Period = (__AUTORELOAD__); } while(0)<01>
__HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)<01>
__HAL_TIM_SET_CLOCKDIVISION(__HANDLE__,__CKD__) do{ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); (__HANDLE__)->Instance->CR1 |= (__CKD__); (__HANDLE__)->Init.ClockDivision = (__CKD__); } while(0)<01>
__HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)<01>
__HAL_TIM_SET_ICPRESCALER(__HANDLE__,__CHANNEL__,__ICPSC__) do{ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); } while(0)<01>
__HAL_TIM_GET_ICPRESCALER(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) : ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) : (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)<01>
__HAL_TIM_SET_COMPARE(__HANDLE__,__CHANNEL__,__COMPARE__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) : ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))<01>
__HAL_TIM_GET_COMPARE(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) : ((__HANDLE__)->Instance->CCR4))<01> __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))<01> __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))<01> __HAL_TIM_ENABLE_OCxFAST(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))<01> __HAL_TIM_DISABLE_OCxFAST(__HANDLE__,__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))<01> __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)<01> __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)<01> __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__,__CHANNEL__,__POLARITY__) do{ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); }while(0)<01> TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))<01> TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))<01> IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))<01> IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || ((__BASE__) == TIM_DMABASE_CR2) || ((__BASE__) == TIM_DMABASE_SMCR) || ((__BASE__) == TIM_DMABASE_DIER) || ((__BASE__) == TIM_DMABASE_SR) || ((__BASE__) == TIM_DMABASE_EGR) || ((__BASE__) == TIM_DMABASE_CCMR1) || ((__BASE__) == TIM_DMABASE_CCMR2) || ((__BASE__) == TIM_DMABASE_CCER) || ((__BASE__) == TIM_DMABASE_CNT) || ((__BASE__) == TIM_DMABASE_PSC) || ((__BASE__) == TIM_DMABASE_ARR) || ((__BASE__) == TIM_DMABASE_RCR) || ((__BASE__) == TIM_DMABASE_CCR1) || ((__BASE__) == TIM_DMABASE_CCR2) || ((__BASE__) == TIM_DMABASE_CCR3) || ((__BASE__) == TIM_DMABASE_CCR4) || ((__BASE__) == TIM_DMABASE_BDTR))<01> IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))<01> IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || ((__MODE__) == TIM_COUNTERMODE_DOWN) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))<01> IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || ((__DIV__) == TIM_CLOCKDIVISION_DIV4))<01> IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))<01> IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || ((__STATE__) == TIM_OCFAST_ENABLE))<01> IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || ((__POLARITY__) == TIM_OCPOLARITY_LOW))<01> IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_

../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM*<2A>Prescalerb#CounterModeb#Periodb#ClockDivisionb# RepetitionCounterb#AutoReloadPreloadb#PTIM_Base_InitTypeDef<12>K*<2A>OCModeb#Pulseb#OCPolarityb#OCNPolarityb# OCFastModeb#OCIdleStateb#OCNIdleStateb#PTIM_OC_InitTypeDefxk*<2A>$OCModeb#Pulseb#OCPolarityb#OCNPolarityb# OCIdleStateb#OCNIdleStateb#ICPolarityb#ICSelectionb#ICFilterb# PTIM_OnePulse_InitTypeDef<01>*<2A>ICPolarityb#ICSelectionb#ICPrescalerb#ICFilterb# PTIM_IC_InitTypeDef<12><01>*<2A>$EncoderModeb#IC1Polarityb#IC1Selectionb#IC1Prescalerb# IC1Filterb#IC2Polarityb#IC2Selectionb#IC2Prescalerb#IC2Filterb# PTIM_Encoder_InitTypeDefb<01>*<2A> ClockSourceb#ClockPolarityb#ClockPrescalerb#ClockFilterb# PTIM_ClockConfigTypeDefD<01>*<2A>
ClearInputStateb#ClearInputSourceb#ClearInputPolarityb#ClearInputPrescalerb# ClearInputFilterb#PTIM_ClearInputConfigTypeDef<12><01>*<2A> MasterOutputTriggerb#MasterSlaveModeb#PTIM_MasterConfigTypeDefp<01>*<2A> SlaveModeb#InputTriggerb#TriggerPolarityb#TriggerPrescalerb# TriggerFilterb#PTIM_SlaveConfigTypeDef<12><01>*<2A> OffStateRunModeb#OffStateIDLEModeb#LockLevelb#DeadTimeb# BreakStateb#BreakPolarityb#BreakFilterb#AutomaticOutputb#PTIM_BreakDeadTimeConfigTypeDefb<01><13>HAL_TIM_STATE_RESET HAL_TIM_STATE_READY HAL_TIM_STATE_BUSY HAL_TIM_STATE_TIMEOUT HAL_TIM_STATE_ERROR PHAL_TIM_StateTypeDef?<01><13>HAL_TIM_CHANNEL_STATE_RESET HAL_TIM_CHANNEL_STATE_READY HAL_TIM_CHANNEL_STATE_BUSY PHAL_TIM_ChannelStateTypeDef<12><01><13>HAL_DMA_BURST_STATE_RESET HAL_DMA_BURST_STATE_READY HAL_DMA_BURST_STATE_BUSY PHAL_TIM_DMABurstStateTypeDefZ<01><13>HAL_TIM_ACTIVE_CHANNEL_1 HAL_TIM_ACTIVE_CHANNEL_2 HAL_TIM_ACTIVE_CHANNEL_3 HAL_TIM_ACTIVE_CHANNEL_4 HAL_TIM_ACTIVE_CHANNEL_CLEARED PHAL_TIM_ActiveChannel<12><01>*<2A>HInstance?
#Init\#Channelq #<03>E
hdma<12> # LockE#<StateK
#=<03>O
ChannelState<12> #><03>O
ChannelNState
#BDMABurstStateS
#F"?"dt<12>t6t<12>PTIM_HandleTypeDef<12> <01><00><00><00>__STM32F1xx_HAL_UART_H <01>HAL_UART_ERROR_NONE 0x00000000U<01>HAL_UART_ERROR_PE 0x00000001U<01>HAL_UART_ERROR_NE 0x00000002U<01>HAL_UART_ERROR_FE 0x00000004U<01>HAL_UART_ERROR_ORE 0x00000008U<01>HAL_UART_ERROR_DMA 0x00000010U<01>UART_WORDLENGTH_8B 0x00000000U<01>UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)<01>UART_STOPBITS_1 0x00000000U<01>UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)<01>UART_PARITY_NONE 0x00000000U<01>UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)<01>UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))<01>UART_HWCONTROL_NONE 0x00000000U<01>UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)<01>UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)<01>UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))<01>UART_MODE_RX ((uint32_t)USART_CR1_RE)<01>UART_MODE_TX ((uint32_t)USART_CR1_TE)<01>UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE))<01>UART_STATE_DISABLE 0x00000000U<01>UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)<01>UART_OVERSAMPLING_16 0x00000000U<01>UART_LINBREAKDETECTLENGTH_10B 0x00000000U<01>UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)<01>UART_WAKEUPMETHOD_IDLELINE 0x00000000U<01>UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)<01>UART_FLAG_CTS ((uint32_t)USART_SR_CTS)<01>UART_FLAG_LBD ((uint32_t)USART_SR_LBD)<01>UART_FLAG_TXE ((uint32_t)USART_SR_TXE)<01>UART_FLAG_TC ((uint32_t)USART_SR_TC)<01>UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)<01>UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)<01>UART_FLAG_ORE ((uint32_t)USART_SR_ORE)<01>UART_FLAG_NE ((uint32_t)USART_SR_NE)<01>UART_FLAG_FE ((uint32_t)USART_SR_FE)<01>UART_FLAG_PE ((uint32_t)USART_SR_PE)<01>UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))<01>UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))<01>UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))<01>UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))<01>UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))<01>UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))<01>UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))<01>UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))<01>HAL_UART_RECEPTION_STANDARD (0x00000000U)<01>HAL_UART_RECEPTION_TOIDLE (0x00000001U)<01>__HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ (__HANDLE__)->gState = HAL_UART_STATE_RESET; (__HANDLE__)->RxState = HAL_UART_STATE_RESET; } while(0U)<01>__HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)<01>__HAL_UART_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))<01>__HAL_UART_CLEAR_FLAG(__HANDLE__,__FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))<01>__HAL_UART_CLEAR_PEFLAG(__HANDLE__) do{ __IO uint32_t tmpreg = 0x00U; tmpreg = (__HANDLE__)->Instance->SR; tmpreg = (__HANDLE__)->Instance->DR; UNUSED(tmpreg); } while(0U)<01>__HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)<01>__HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)<01>__HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)<01>__HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)<01>__HAL_UART_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))<01>__HAL_UART_DISABLE_IT(__HANDLE__,__INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))<01>__HAL_UART_GET_IT_SOURCE(__HANDLE__,__IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint
../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM*<2A>BaudRateb#WordLengthb#StopBitsb#Parityb# Modeb#HwFlowCtlb#OverSamplingb#PUART_InitTypeDef<12>L<13>HAL_UART_STATE_RESET HAL_UART_STATE_READY HAL_UART_STATE_BUSY $HAL_UART_STATE_BUSY_TX !HAL_UART_STATE_BUSY_RX "HAL_UART_STATE_BUSY_TX_RX #HAL_UART_STATE_TIMEOUT <0B>HAL_UART_STATE_ERROR <0B>PHAL_UART_StateTypeDefo<01>PHAL_UART_RxTypeTypeDefb<01>)<29>__UART_HandleTypeDefDInstance<12>#InitW#pTxBuffPtr<12># TxXferSizeR#$TxXferCount<12>#&pRxBuffPtr<12>#(RxXferSizeR#,RxXferCount<12>#.ReceptionType<12>#0hdmatx<12>#4hdmarx<12>#8LockE#<gState<12>#=RxState<12>#>ErrorCode<12>#@"<10>"CtRt\"dt>tbPUART_HandleTypeDef}<01><00><00><00>__STM32F1xx_HAL_CONF_H $HAL_MODULE_ENABLED -HAL_DMA_MODULE_ENABLED 0HAL_GPIO_MODULE_ENABLED CHAL_TIM_MODULE_ENABLED DHAL_UART_MODULE_ENABLED HHAL_CORTEX_MODULE_ENABLED IHAL_DMA_MODULE_ENABLED JHAL_FLASH_MODULE_ENABLED KHAL_EXTI_MODULE_ENABLED LHAL_GPIO_MODULE_ENABLED MHAL_PWR_MODULE_ENABLED NHAL_RCC_MODULE_ENABLED WHSE_VALUE 8000000U[HSE_STARTUP_TIMEOUT 100UdHSI_VALUE 8000000UkLSI_VALUE 40000UuLSE_VALUE 32768UyLSE_STARTUP_TIMEOUT 5000U<01>VDD_VALUE 3300U<01>TICK_INT_PRIORITY 0U<01>USE_RTOS 0U<01>PREFETCH_ENABLE 1U<01>USE_HAL_ADC_REGISTER_CALLBACKS 0U<01>USE_HAL_CAN_REGISTER_CALLBACKS 0U<01>USE_HAL_CEC_REGISTER_CALLBACKS 0U<01>USE_HAL_DAC_REGISTER_CALLBACKS 0U<01>USE_HAL_ETH_REGISTER_CALLBACKS 0U<01>USE_HAL_HCD_REGISTER_CALLBACKS 0U<01>USE_HAL_I2C_REGISTER_CALLBACKS 0U<01>USE_HAL_I2S_REGISTER_CALLBACKS 0U<01>USE_HAL_MMC_REGISTER_CALLBACKS 0U<01>USE_HAL_NAND_REGISTER_CALLBACKS 0U<01>USE_HAL_NOR_REGISTER_CALLBACKS 0U<01>USE_HAL_PCCARD_REGISTER_CALLBACKS 0U<01>USE_HAL_PCD_REGISTER_CALLBACKS 0U<01>USE_HAL_RTC_REGISTER_CALLBACKS 0U<01>USE_HAL_SD_REGISTER_CALLBACKS 0U<01>USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U<01>USE_HAL_IRDA_REGISTER_CALLBACKS 0U<01>USE_HAL_SRAM_REGISTER_CALLBACKS 0U<01>USE_HAL_SPI_REGISTER_CALLBACKS 0U<01>USE_HAL_TIM_REGISTER_CALLBACKS 0U<01>USE_HAL_UART_REGISTER_CALLBACKS 0U<01>USE_HAL_USART_REGISTER_CALLBACKS 0U<01>USE_HAL_WWDG_REGISTER_CALLBACKS 0U<01>MAC_ADDR0 2U<01>MAC_ADDR1 0U<01>MAC_ADDR2 0U<01>MAC_ADDR3 0U<01>MAC_ADDR4 0U<01>MAC_ADDR5 0U<01>ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE<01>ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE<01>ETH_RXBUFNB 8U<01>ETH_TXBUFNB 4U<01>DP83848_PHY_ADDRESS 0x01U<01>PHY_RESET_DELAY 0x000000FFU<01>PHY_CONFIG_DELAY 0x00000FFFU<01>PHY_READ_TO 0x0000FFFFU<01>PHY_WRITE_TO 0x0000FFFFU<01>PHY_BCR ((uint16_t)0x00)<01>PHY_BSR ((uint16_t)0x01)<01>PHY_RESET ((uint16_t)0x8000)<01>PHY_LOOPBACK ((uint16_t)0x4000)<01>PHY_FULLDUPLEX_100M ((uint16_t)0x2100)<01>PHY_HALFDUPLEX_100M ((uint16_t)0x2000)<01>PHY_FULLDUPLEX_10M ((uint16_t)0x0100)<01>PHY_HALFDUPLEX_10M ((uint16_t)0x0000)<01>PHY_AUTONEGOTIATION ((uint16_t)0x1000)<01>PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200)<01>PHY_POWERDOWN ((uint16_t)0x0800)<01>PHY_ISOLATE ((uint16_t)0x0400)<01>PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020)<01>PHY_LINKED_STATUS ((uint16_t)0x0004)<01>PHY_JABBER_DETECTION ((uint16_t)0x0002)<01>PHY_SR ((uint16_t)0x10U)<01>PHY_SPEED_STATUS ((uint16_t)0x0002U)<01>PHY_DUPLEX_STATUS ((uint16_t)0x0004U)<01>USE_SPI_CRC 0U<03><03><03><03><03><03><03><03> <03>
<01>assert_param(expr) ((void)0U)@4 ../Core/Inc/../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_conf.hstm32f1xx_hal_rcc.hstm32f1xx_hal_gpio.hstm32f1xx_hal_exti.hstm32f1xx_hal_dma.hstm32f1xx_hal_cortex.hstm32f1xx_hal_flash.hstm32f1xx_hal_pwr.hstm32f1xx_hal_tim.hstm32f1xx_hal_uart.h<01>
../Core/Inc/stm32f1xx_hal_conf.hComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM<00><00><00>2PVD_MODE_IT 0x00010000U3PVD_MODE_EVT 0x00020000U4PVD_RISING_EDGE 0x00000001U5PVD_FALLING_EDGE 0x00000002U?PWR_OFFSET (PWR_BASE - PERIPH_BASE)@PWR_CR_OFFSET 0x00UAPWR_CSR_OFFSET 0x04UBPWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)CPWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)MLPSDSR_BIT_NUMBER PWR_CR_LPDS_PosNCR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U)))QDBP_BIT_NUMBER PWR_CR_DBP_PosRCR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)))UPVDE_BIT_NUMBER PWR_CR_PVDE_PosVCR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)))bCSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U)))<00><00> ../Drivers/STM32F1xx_HAL_Driver/Inc/../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cstm32f1xx_hal.h<01>
../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.cComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] D:\工作库\GitHub\MicrochipFor32\MX_FastSet\T103RC\MDK-ARM"<10><00>!/!I$ > %%%% %C
%C % % %%%C%C&I  ((      1 1 1 1 I8  I I8 4 ! I8 "I#7I$I%I&I 'I(I) * +,-./4  04 14 24 34 44 5.:;9? I6.:;9? 7.:;9G8.:;9? I 9.:;9? :.:;9G ;.:;9? I<.:;9? =.:;9G>.:;9? I@?.:;9? @@.:;9G@A.:;9? I@
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D1E1F1XYWG1XYWH.1I.1@J.1@
K.1L.< 4 I? M.< 4 ? NIOPI:;9QI4 R S TUVW1X4I ,Y4I Z4I[4I,\4I]4I 4 ^4I ,4 _4I4 `4I,4 a4I4 b41 ,c41d41,e41f1g1hI iIjIkI 4 lI ,4 mI4 n1 o1p4I ? q4I? < r4I,s4It5Iu;v=w%x<%Component: ARM Compiler 5.06 update 7 (build 960) Tool: armlink [4d3601]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=template\stm32f1xx_hal_pwr.o --vfemode=force
Input Comments:p5d48-3Component: ARM Compiler 5.06 update 7 (build 960) Tool: armasm [4d35fa]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide stm32f1xx_hal_pwr.oComponent: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]ArmCC --c99 --split_sections --debug -c -otemplate\stm32f1xx_hal_pwr.o --depend=template\stm32f1xx_hal_pwr.d --cpu=Cortex-M3 --apcs=interwork -O3 --diag_suppress=9931 -I../Core/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I.\bsp_Device -I.\bsp_System -I.\RTE\_template -ID:\SOFTWARE\Keil_v5\ARM\PACK\ARM\CMSIS\5.9.0\CMSIS\Core\Include -ID:\SOFTWARE\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\1.0.5\Device\Include -D__UVISION_VERSION=537 -D_RTE_ -DSTM32F10X_HD -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F103xE --omf_browse=template\stm32f1xx_hal_pwr.crf ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c<00>+<00>+<00>+<00>+<00>+t<00>+<00>+<00>+<00>+<00>+<00>+<00>+<00>+ <00>+ <00>+ <00>+
<00>+
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