637 lines
45 KiB
ArmAsm
637 lines
45 KiB
ArmAsm
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
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;* File Name : startup_stm32h743xx.s
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;* @author MCD Application Team
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;* version : V1.2.0
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;* Date : 29-December-2017
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;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == Reset_Handler
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;* - Set the vector table entries with the exceptions ISR address
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;* - Branches to __main in the C library (which eventually
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;* calls main()).
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;* After Reset the Cortex-M processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;* <<< Use Configuration Wizard in Context Menu >>>
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;*******************************************************************************
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;
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; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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; You may not use this file except in compliance with the License.
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; You may obtain a copy of the License at:
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;
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; http://www.st.com/software_license_agreement_liberty_v2
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;
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; Unless required by applicable law or agreed to in writing, software
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; distributed under the License is distributed on an "AS IS" BASIS,
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; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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; See the License for the specific language governing permissions and
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; limitations under the License.
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;
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;*******************************************************************************
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; Amount of memory (in bytes) allocated for Stack
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; Tailor this value to your application needs
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x800
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
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DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
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DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
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DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
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DCD FLASH_IRQHandler ; FLASH
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DCD RCC_IRQHandler ; RCC
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DCD EXTI0_IRQHandler ; EXTI Line0
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DCD EXTI1_IRQHandler ; EXTI Line1
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DCD EXTI2_IRQHandler ; EXTI Line2
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DCD EXTI3_IRQHandler ; EXTI Line3
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DCD EXTI4_IRQHandler ; EXTI Line4
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DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
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DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
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DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
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DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
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DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
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DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
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DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
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DCD ADC_IRQHandler ; ADC1, ADC2
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DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
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DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
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DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
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DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
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DCD EXTI9_5_IRQHandler ; External Line[9:5]s
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DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
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DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
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DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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DCD TIM2_IRQHandler ; TIM2
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DCD TIM3_IRQHandler ; TIM3
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DCD TIM4_IRQHandler ; TIM4
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DCD I2C1_EV_IRQHandler ; I2C1 Event
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DCD I2C1_ER_IRQHandler ; I2C1 Error
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DCD I2C2_EV_IRQHandler ; I2C2 Event
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DCD I2C2_ER_IRQHandler ; I2C2 Error
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DCD SPI1_IRQHandler ; SPI1
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DCD SPI2_IRQHandler ; SPI2
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DCD USART1_IRQHandler ; USART1
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DCD USART2_IRQHandler ; USART2
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DCD USART3_IRQHandler ; USART3
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DCD EXTI15_10_IRQHandler ; External Line[15:10]
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DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
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DCD 0 ; Reserved
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DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
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DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
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DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
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DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
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DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
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DCD FMC_IRQHandler ; FMC
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DCD SDMMC1_IRQHandler ; SDMMC1
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DCD TIM5_IRQHandler ; TIM5
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DCD SPI3_IRQHandler ; SPI3
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DCD UART4_IRQHandler ; UART4
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DCD UART5_IRQHandler ; UART5
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DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
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DCD TIM7_IRQHandler ; TIM7
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DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
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DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
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DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
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DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
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DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
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DCD ETH_IRQHandler ; Ethernet
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DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
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DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
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DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
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DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
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DCD USART6_IRQHandler ; USART6
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DCD I2C3_EV_IRQHandler ; I2C3 event
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DCD I2C3_ER_IRQHandler ; I2C3 error
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DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
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DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
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DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
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DCD OTG_HS_IRQHandler ; USB OTG HS
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DCD DCMI_IRQHandler ; DCMI
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DCD 0 ; Reserved
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DCD RNG_IRQHandler ; Rng
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DCD FPU_IRQHandler ; FPU
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DCD UART7_IRQHandler ; UART7
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DCD UART8_IRQHandler ; UART8
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DCD SPI4_IRQHandler ; SPI4
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DCD SPI5_IRQHandler ; SPI5
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DCD SPI6_IRQHandler ; SPI6
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DCD SAI1_IRQHandler ; SAI1
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DCD LTDC_IRQHandler ; LTDC
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DCD LTDC_ER_IRQHandler ; LTDC error
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DCD DMA2D_IRQHandler ; DMA2D
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DCD SAI2_IRQHandler ; SAI2
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DCD QUADSPI_IRQHandler ; QUADSPI
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DCD LPTIM1_IRQHandler ; LPTIM1
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DCD CEC_IRQHandler ; HDMI_CEC
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DCD I2C4_EV_IRQHandler ; I2C4 Event
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DCD I2C4_ER_IRQHandler ; I2C4 Error
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DCD SPDIF_RX_IRQHandler ; SPDIF_RX
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DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
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DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
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DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
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DCD OTG_FS_IRQHandler ; USB OTG FS
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DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
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DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
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DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
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DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
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DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
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DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
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DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
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DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
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DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
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DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
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DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
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DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
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DCD SAI3_IRQHandler ; SAI3 global Interrupt
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DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
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DCD TIM15_IRQHandler ; TIM15 global Interrupt
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DCD TIM16_IRQHandler ; TIM16 global Interrupt
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DCD TIM17_IRQHandler ; TIM17 global Interrupt
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DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
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DCD MDIOS_IRQHandler ; MDIOS global Interrupt
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DCD JPEG_IRQHandler ; JPEG global Interrupt
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DCD MDMA_IRQHandler ; MDMA global Interrupt
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DCD 0 ; Reserved
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DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
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DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
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DCD 0 ; Reserved
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DCD ADC3_IRQHandler ; ADC3 global Interrupt
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DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
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DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
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DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
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DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
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DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
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DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
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DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
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DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
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DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
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DCD COMP1_IRQHandler ; COMP1 global Interrupt
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DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
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DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
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DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
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DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
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DCD LPUART1_IRQHandler ; LP UART1 interrupt
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DCD 0 ; Reserved
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DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
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DCD 0 ; Reserved
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DCD SAI4_IRQHandler ; SAI4 global interrupt
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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;IMPORT SystemInit
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;<3B>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SystemInit<69><74><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD>ε<EFBFBD>,<2C>⺯<EFBFBD><E2BAAF><EFBFBD>汾<EFBFBD><E6B1BE><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD>ⲿʵ<E2B2BF><CAB5>SystemInit<69><74><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD>ᱨ<EFBFBD><E1B1A8>.
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IMPORT __main
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IF {FPU} != "SoftVFP" ;ͨ<><CDA8>Targetѡ<74><EFBFBD><EEBFA8>Floating Point Hardwareѡ<65><D1A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
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;<3B><><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>:Not Used,<2C><EFBFBD><F2B2BBB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>´<EFBFBD><C2B4><EFBFBD>(<28><>ENDIF<49><46><EFBFBD><EFBFBD>)
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;<3B><><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>:Use Single/Double Precision,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>´<EFBFBD><C2B4><EFBFBD>
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;Enable Floating Point Support at reset for FPU
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LDR.W R0, =0xE000ED88 ; Load address of CPACR register
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LDR R1, [R0] ; Read value at CPACR
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ORR R1, R1, #(0xF <<20) ; Set bits 20-23 to enable CP10 and CP11 coprocessors
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; Write back the modified CPACR value
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STR R1, [R0] ; Wait for store to complete
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DSB
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;<3B><><EFBFBD><EFBFBD>OSӦ<53><D3A6>,FPU<50>Ĵ<EFBFBD><C4B4><EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD>OSѹջ<D1B9><D5BB><EFBFBD><EFBFBD>,<2C>ر<EFBFBD>Ӳ<EFBFBD><D3B2>ѹջ
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; Disable automatic FP register content
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; Disable lazy context switch
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LDR.W R0, =0xE000EF34 ; Load address to FPCCR register
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LDR R1, [R0]
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AND R1, R1, #(0x3FFFFFFF) ; Clear the LSPEN and ASPEN bits
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STR R1, [R0]
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ISB ; Reset pipeline now the FPU is enabled
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ENDIF
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;LDR R0, =SystemInit ;<3B>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,δ<>õ<EFBFBD>,<2C><><EFBFBD><EFBFBD>
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;BLX R0 ;<3B>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,δ<>õ<EFBFBD>,<2C><><EFBFBD><EFBFBD>
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT WWDG_IRQHandler [WEAK]
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EXPORT PVD_AVD_IRQHandler [WEAK]
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EXPORT TAMP_STAMP_IRQHandler [WEAK]
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EXPORT RTC_WKUP_IRQHandler [WEAK]
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EXPORT FLASH_IRQHandler [WEAK]
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EXPORT RCC_IRQHandler [WEAK]
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EXPORT EXTI0_IRQHandler [WEAK]
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EXPORT EXTI1_IRQHandler [WEAK]
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EXPORT EXTI2_IRQHandler [WEAK]
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EXPORT EXTI3_IRQHandler [WEAK]
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EXPORT EXTI4_IRQHandler [WEAK]
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EXPORT DMA1_Stream0_IRQHandler [WEAK]
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EXPORT DMA1_Stream1_IRQHandler [WEAK]
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EXPORT DMA1_Stream2_IRQHandler [WEAK]
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EXPORT DMA1_Stream3_IRQHandler [WEAK]
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EXPORT DMA1_Stream4_IRQHandler [WEAK]
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EXPORT DMA1_Stream5_IRQHandler [WEAK]
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EXPORT DMA1_Stream6_IRQHandler [WEAK]
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EXPORT DMA1_Stream7_IRQHandler [WEAK]
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EXPORT ADC_IRQHandler [WEAK]
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EXPORT FDCAN1_IT0_IRQHandler [WEAK]
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EXPORT FDCAN2_IT0_IRQHandler [WEAK]
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EXPORT FDCAN1_IT1_IRQHandler [WEAK]
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EXPORT FDCAN2_IT1_IRQHandler [WEAK]
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EXPORT EXTI9_5_IRQHandler [WEAK]
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EXPORT TIM1_BRK_IRQHandler [WEAK]
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EXPORT TIM1_UP_IRQHandler [WEAK]
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EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
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EXPORT TIM1_CC_IRQHandler [WEAK]
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EXPORT TIM2_IRQHandler [WEAK]
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EXPORT TIM3_IRQHandler [WEAK]
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EXPORT TIM4_IRQHandler [WEAK]
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EXPORT I2C1_EV_IRQHandler [WEAK]
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EXPORT I2C1_ER_IRQHandler [WEAK]
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EXPORT I2C2_EV_IRQHandler [WEAK]
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EXPORT I2C2_ER_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT USART1_IRQHandler [WEAK]
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EXPORT USART2_IRQHandler [WEAK]
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EXPORT USART3_IRQHandler [WEAK]
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EXPORT EXTI15_10_IRQHandler [WEAK]
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EXPORT RTC_Alarm_IRQHandler [WEAK]
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EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
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EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
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EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
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EXPORT TIM8_CC_IRQHandler [WEAK]
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EXPORT DMA1_Stream7_IRQHandler [WEAK]
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EXPORT FMC_IRQHandler [WEAK]
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EXPORT SDMMC1_IRQHandler [WEAK]
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EXPORT TIM5_IRQHandler [WEAK]
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EXPORT SPI3_IRQHandler [WEAK]
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EXPORT UART4_IRQHandler [WEAK]
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EXPORT UART5_IRQHandler [WEAK]
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EXPORT TIM6_DAC_IRQHandler [WEAK]
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EXPORT TIM7_IRQHandler [WEAK]
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EXPORT DMA2_Stream0_IRQHandler [WEAK]
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EXPORT DMA2_Stream1_IRQHandler [WEAK]
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EXPORT DMA2_Stream2_IRQHandler [WEAK]
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EXPORT DMA2_Stream3_IRQHandler [WEAK]
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EXPORT DMA2_Stream4_IRQHandler [WEAK]
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EXPORT ETH_IRQHandler [WEAK]
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EXPORT ETH_WKUP_IRQHandler [WEAK]
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EXPORT FDCAN_CAL_IRQHandler [WEAK]
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EXPORT DMA2_Stream5_IRQHandler [WEAK]
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EXPORT DMA2_Stream6_IRQHandler [WEAK]
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EXPORT DMA2_Stream7_IRQHandler [WEAK]
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EXPORT USART6_IRQHandler [WEAK]
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EXPORT I2C3_EV_IRQHandler [WEAK]
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EXPORT I2C3_ER_IRQHandler [WEAK]
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EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
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EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
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EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
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EXPORT OTG_HS_IRQHandler [WEAK]
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EXPORT DCMI_IRQHandler [WEAK]
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EXPORT RNG_IRQHandler [WEAK]
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EXPORT FPU_IRQHandler [WEAK]
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EXPORT UART7_IRQHandler [WEAK]
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EXPORT UART8_IRQHandler [WEAK]
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EXPORT SPI4_IRQHandler [WEAK]
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EXPORT SPI5_IRQHandler [WEAK]
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EXPORT SPI6_IRQHandler [WEAK]
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EXPORT SAI1_IRQHandler [WEAK]
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EXPORT LTDC_IRQHandler [WEAK]
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EXPORT LTDC_ER_IRQHandler [WEAK]
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EXPORT DMA2D_IRQHandler [WEAK]
|
||
EXPORT SAI2_IRQHandler [WEAK]
|
||
EXPORT QUADSPI_IRQHandler [WEAK]
|
||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||
EXPORT CEC_IRQHandler [WEAK]
|
||
EXPORT I2C4_EV_IRQHandler [WEAK]
|
||
EXPORT I2C4_ER_IRQHandler [WEAK]
|
||
EXPORT SPDIF_RX_IRQHandler [WEAK]
|
||
EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
|
||
EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
|
||
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||
EXPORT OTG_FS_IRQHandler [WEAK]
|
||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||
EXPORT HRTIM1_Master_IRQHandler [WEAK]
|
||
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
|
||
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
|
||
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
|
||
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
|
||
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
|
||
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
|
||
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
|
||
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
|
||
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
|
||
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
|
||
EXPORT SAI3_IRQHandler [WEAK]
|
||
EXPORT SWPMI1_IRQHandler [WEAK]
|
||
EXPORT TIM15_IRQHandler [WEAK]
|
||
EXPORT TIM16_IRQHandler [WEAK]
|
||
EXPORT TIM17_IRQHandler [WEAK]
|
||
EXPORT MDIOS_WKUP_IRQHandler [WEAK]
|
||
EXPORT MDIOS_IRQHandler [WEAK]
|
||
EXPORT JPEG_IRQHandler [WEAK]
|
||
EXPORT MDMA_IRQHandler [WEAK]
|
||
EXPORT SDMMC2_IRQHandler [WEAK]
|
||
EXPORT HSEM1_IRQHandler [WEAK]
|
||
EXPORT ADC3_IRQHandler [WEAK]
|
||
EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
|
||
EXPORT BDMA_Channel0_IRQHandler [WEAK]
|
||
EXPORT BDMA_Channel1_IRQHandler [WEAK]
|
||
EXPORT BDMA_Channel2_IRQHandler [WEAK]
|
||
EXPORT BDMA_Channel3_IRQHandler [WEAK]
|
||
EXPORT BDMA_Channel4_IRQHandler [WEAK]
|
||
EXPORT BDMA_Channel5_IRQHandler [WEAK]
|
||
EXPORT BDMA_Channel6_IRQHandler [WEAK]
|
||
EXPORT BDMA_Channel7_IRQHandler [WEAK]
|
||
EXPORT COMP1_IRQHandler [WEAK]
|
||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||
EXPORT LPTIM3_IRQHandler [WEAK]
|
||
EXPORT LPTIM4_IRQHandler [WEAK]
|
||
EXPORT LPTIM5_IRQHandler [WEAK]
|
||
EXPORT LPUART1_IRQHandler [WEAK]
|
||
EXPORT CRS_IRQHandler [WEAK]
|
||
EXPORT SAI4_IRQHandler [WEAK]
|
||
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
||
|
||
|
||
WWDG_IRQHandler
|
||
PVD_AVD_IRQHandler
|
||
TAMP_STAMP_IRQHandler
|
||
RTC_WKUP_IRQHandler
|
||
FLASH_IRQHandler
|
||
RCC_IRQHandler
|
||
EXTI0_IRQHandler
|
||
EXTI1_IRQHandler
|
||
EXTI2_IRQHandler
|
||
EXTI3_IRQHandler
|
||
EXTI4_IRQHandler
|
||
DMA1_Stream0_IRQHandler
|
||
DMA1_Stream1_IRQHandler
|
||
DMA1_Stream2_IRQHandler
|
||
DMA1_Stream3_IRQHandler
|
||
DMA1_Stream4_IRQHandler
|
||
DMA1_Stream5_IRQHandler
|
||
DMA1_Stream6_IRQHandler
|
||
ADC_IRQHandler
|
||
FDCAN1_IT0_IRQHandler
|
||
FDCAN2_IT0_IRQHandler
|
||
FDCAN1_IT1_IRQHandler
|
||
FDCAN2_IT1_IRQHandler
|
||
EXTI9_5_IRQHandler
|
||
TIM1_BRK_IRQHandler
|
||
TIM1_UP_IRQHandler
|
||
TIM1_TRG_COM_IRQHandler
|
||
TIM1_CC_IRQHandler
|
||
TIM2_IRQHandler
|
||
TIM3_IRQHandler
|
||
TIM4_IRQHandler
|
||
I2C1_EV_IRQHandler
|
||
I2C1_ER_IRQHandler
|
||
I2C2_EV_IRQHandler
|
||
I2C2_ER_IRQHandler
|
||
SPI1_IRQHandler
|
||
SPI2_IRQHandler
|
||
USART1_IRQHandler
|
||
USART2_IRQHandler
|
||
USART3_IRQHandler
|
||
EXTI15_10_IRQHandler
|
||
RTC_Alarm_IRQHandler
|
||
TIM8_BRK_TIM12_IRQHandler
|
||
TIM8_UP_TIM13_IRQHandler
|
||
TIM8_TRG_COM_TIM14_IRQHandler
|
||
TIM8_CC_IRQHandler
|
||
DMA1_Stream7_IRQHandler
|
||
FMC_IRQHandler
|
||
SDMMC1_IRQHandler
|
||
TIM5_IRQHandler
|
||
SPI3_IRQHandler
|
||
UART4_IRQHandler
|
||
UART5_IRQHandler
|
||
TIM6_DAC_IRQHandler
|
||
TIM7_IRQHandler
|
||
DMA2_Stream0_IRQHandler
|
||
DMA2_Stream1_IRQHandler
|
||
DMA2_Stream2_IRQHandler
|
||
DMA2_Stream3_IRQHandler
|
||
DMA2_Stream4_IRQHandler
|
||
ETH_IRQHandler
|
||
ETH_WKUP_IRQHandler
|
||
FDCAN_CAL_IRQHandler
|
||
DMA2_Stream5_IRQHandler
|
||
DMA2_Stream6_IRQHandler
|
||
DMA2_Stream7_IRQHandler
|
||
USART6_IRQHandler
|
||
I2C3_EV_IRQHandler
|
||
I2C3_ER_IRQHandler
|
||
OTG_HS_EP1_OUT_IRQHandler
|
||
OTG_HS_EP1_IN_IRQHandler
|
||
OTG_HS_WKUP_IRQHandler
|
||
OTG_HS_IRQHandler
|
||
DCMI_IRQHandler
|
||
RNG_IRQHandler
|
||
FPU_IRQHandler
|
||
UART7_IRQHandler
|
||
UART8_IRQHandler
|
||
SPI4_IRQHandler
|
||
SPI5_IRQHandler
|
||
SPI6_IRQHandler
|
||
SAI1_IRQHandler
|
||
LTDC_IRQHandler
|
||
LTDC_ER_IRQHandler
|
||
DMA2D_IRQHandler
|
||
SAI2_IRQHandler
|
||
QUADSPI_IRQHandler
|
||
LPTIM1_IRQHandler
|
||
CEC_IRQHandler
|
||
I2C4_EV_IRQHandler
|
||
I2C4_ER_IRQHandler
|
||
SPDIF_RX_IRQHandler
|
||
OTG_FS_EP1_OUT_IRQHandler
|
||
OTG_FS_EP1_IN_IRQHandler
|
||
OTG_FS_WKUP_IRQHandler
|
||
OTG_FS_IRQHandler
|
||
DMAMUX1_OVR_IRQHandler
|
||
HRTIM1_Master_IRQHandler
|
||
HRTIM1_TIMA_IRQHandler
|
||
HRTIM1_TIMB_IRQHandler
|
||
HRTIM1_TIMC_IRQHandler
|
||
HRTIM1_TIMD_IRQHandler
|
||
HRTIM1_TIME_IRQHandler
|
||
HRTIM1_FLT_IRQHandler
|
||
DFSDM1_FLT0_IRQHandler
|
||
DFSDM1_FLT1_IRQHandler
|
||
DFSDM1_FLT2_IRQHandler
|
||
DFSDM1_FLT3_IRQHandler
|
||
SAI3_IRQHandler
|
||
SWPMI1_IRQHandler
|
||
TIM15_IRQHandler
|
||
TIM16_IRQHandler
|
||
TIM17_IRQHandler
|
||
MDIOS_WKUP_IRQHandler
|
||
MDIOS_IRQHandler
|
||
JPEG_IRQHandler
|
||
MDMA_IRQHandler
|
||
SDMMC2_IRQHandler
|
||
HSEM1_IRQHandler
|
||
ADC3_IRQHandler
|
||
DMAMUX2_OVR_IRQHandler
|
||
BDMA_Channel0_IRQHandler
|
||
BDMA_Channel1_IRQHandler
|
||
BDMA_Channel2_IRQHandler
|
||
BDMA_Channel3_IRQHandler
|
||
BDMA_Channel4_IRQHandler
|
||
BDMA_Channel5_IRQHandler
|
||
BDMA_Channel6_IRQHandler
|
||
BDMA_Channel7_IRQHandler
|
||
COMP1_IRQHandler
|
||
LPTIM2_IRQHandler
|
||
LPTIM3_IRQHandler
|
||
LPTIM4_IRQHandler
|
||
LPTIM5_IRQHandler
|
||
LPUART1_IRQHandler
|
||
CRS_IRQHandler
|
||
SAI4_IRQHandler
|
||
WAKEUP_PIN_IRQHandler
|
||
|
||
B .
|
||
|
||
ENDP
|
||
|
||
ALIGN
|
||
|
||
;*******************************************************************************
|
||
; User Stack and Heap initialization
|
||
;*******************************************************************************
|
||
IF :DEF:__MICROLIB
|
||
|
||
EXPORT __initial_sp
|
||
EXPORT __heap_base
|
||
EXPORT __heap_limit
|
||
|
||
ELSE
|
||
|
||
IMPORT __use_two_region_memory
|
||
EXPORT __user_initial_stackheap
|
||
|
||
__user_initial_stackheap
|
||
|
||
LDR R0, = Heap_Mem
|
||
LDR R1, =(Stack_Mem + Stack_Size)
|
||
LDR R2, = (Heap_Mem + Heap_Size)
|
||
LDR R3, = Stack_Mem
|
||
BX LR
|
||
|
||
ALIGN
|
||
|
||
ENDIF
|
||
|
||
END
|
||
|
||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|