34 lines
1.5 KiB
Plaintext
34 lines
1.5 KiB
Plaintext
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\t (00:00:05) allegro 17.4 S035 Windows SPB 64-bit Edition
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\t (00:00:05) Journal start - Sun Mar 24 02:59:48 2024
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\t (00:00:05) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=25828 CPUs=12
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\t (00:00:05) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\smc\sod-l6-w3.dra
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\t (00:00:05)
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(00:00:05) Loading axlcore.cxt
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\t (00:00:05) Opening existing design...
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\i (00:00:05) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sod-l6-w3"
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\d (00:00:05) Design opened: D:/workspace/GitHub/pcb_lib/smc/sod-l6-w3.dra
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\i (00:00:05) trapsize 1180
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\i (00:00:06) trapsize 1212
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\i (00:00:06) trapsize 1180
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\t (00:00:07) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
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\i (00:00:07) trapsize 1368
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\t (00:00:07) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
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\i (00:00:07) trapsize 1404
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\i (00:00:07) updateport CVPane
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\i (00:00:08) shapeedit
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\i (00:00:11) step pkg map
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\i (00:00:12) fillin yes
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\i (00:00:20) setwindow form.pkgmap3d
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\i (00:00:20) FORM pkgmap3d overlay YES
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\i (00:00:30) FORM pkgmap3d stplist RES_CRCW_2512.step
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\i (00:00:31) FORM pkgmap3d stplist SMA-DO-214AC.step
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\i (00:00:38) FORM pkgmap3d save_current
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\i (00:00:40) FORM pkgmap3d done
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\i (00:00:41) setwindow pcb
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\i (00:00:41) shapeedit
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\i (00:00:41) exit
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\e (00:00:41) Do you want to save the changes you made to sod-l6-w3.dra?
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\i (00:00:42) fillin yes
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\t (00:00:42) Symbol 'sod-l6-w3.psm' created.
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\t (00:00:43) Journal end - Sun Mar 24 03:00:26 2024
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