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pcb_lib/thr/thr_dip_2x5.psm

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对封装进行了第一次痛苦的基本标准化
2024-03-17 01:53:28 +08:00
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规范化命名与封装
2024-03-12 21:14:52 +08:00
更新一些封装
2024-03-23 02:02:12 +08:00
<02>B<00><><EFBFBD>D5<>5<>
<00> <00> IH)bat408381/14/all408381/14/..bat408381/14/all408381/14/.....p/<2F><>p/<2F><><EFBFBD><EFBFBD><00><> <00>!#<00><00><00><>'G EE<00><00>EEEEEEEEE TOPBOTTOMAIRCOPPERFR-4PRIMARYNCROUTE_PATHDEFAULT RFETCHSHAPENET!THR1R6_0R9"#NCLEGEND-1-2$__EPB_SCRATCH_ACON_SPACE_POLY%SOLD_BOTTOM&SOLD_TOP'SILK_TOP(SILK_BOTTOM)PASTE_TOP*PASTE_BOTTOM+OUTLINE,ASM_TOP-ASM_BOTTOM.LINEAR_DIMENSION/THR-1R02_1R80THR_DIP_2X51524334251610798897:6+<00>0*<2A><><EFBFBD><EFBFBD>S<EFBFBD><53>2E<00>
[]s<00>z<00>2 @<00><00><00>q<00>2 A@<00><00>oPB<00><00>h THR-1R02_1R82 CA<00><00>mFD^<00>h9MM, -5.090000, -1.270000, 0.000000, 90.000, 0.000, 0.000*<00><00>E*G6H'<00><00><00><00>ski'<00><00><00><00>asm'<00><00><00><00>tip1 N'<00><00><00>tip2'<00><00><00><00>asm1<00><00> l<00><00>asm2<00><00>d<00>dpin8cjJ<00>||D\<00>ĚĚt<00>=z<><00><><00><><00>+N<><00><><00><><00>.*<2A>p<>Ԕ<00>1 <0C>><3E><00><><00>7<00> <0C><00><><00>><00>6<18>t|l5<00><><EFBFBD>terminator.logeclrpt.txteclrep.log<00><EFBFBD>1.0<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><7F><EFBFBD>IPJ<00><00>h THR-1R02_1R82 KC<00><00>kPL<00><00>h THR-1R02_1R82 MK<00><00>i<00>&NMM<00> O6<00>p<><00>1PPPOOh THR-1R02_1R82 QM<00>Og R7O8c<00>1SPSRRh THR-1R02_1R82 TQ<00>Re U8R<00>1VPVUUh THR-1R02_1R82 WT<00>Uc X9UȜ<><C89C><EFBFBD>1YPYXXh THR-1R02_1R82 ZW<00>Xa [:X<00>9<EFBFBD><39><EFBFBD>1\P\[[h THR-1R02_1R82 ]Z<00>[_<00>]^x<00>h<00>MAP_MODE=PACKAGE!OVERLAY=YES!HIDE_BOARD=YES!MAP=STEP_PRIMARY!TRANSPARENT=Symbol!VIEW=Top!PKG=DIP_2x5!DEVICE=!INCREMENT=1.000000!0 <09>_]]`<00>B<EFBFBD><42>1 <09>`_<00>B<EFBFBD><42>60 <09>aZZbĥ<><C4A5>1 <09>baĥ<><C4A5>70 <09>cWWd<00>1 <09>dc<00>80 <09>eTTf4l1 <09>fe4l90 <09>gQQh$<24>1 <09>hg$<24>100 <09>iMMj<00>B<EFBFBD><42>ܺ<EFBFBD><DCBA>1 <09>ji<00>B<EFBFBD><42>ܺ<EFBFBD><DCBA>10 <09>kKKlĥ<><C4A5>ܺ<EFBFBD><DCBA>1 <09>lkĥ<><C4A5>ܺ<EFBFBD><DCBA>20 <09>mCCn<00>ܺ<><DCBA>1 <09>nm<00>ܺ<><DCBA>30 <09>oAAp4lܺ<><DCBA>1 <09>po4lܺ<><DCBA>40 <09>q@@rT<>ܺ<><DCBA>1 <09>rqT<>ܺ<><DCBA>5 <09>s<00><00>ttus<00><00><07><>8c <0C>8cuvs<00> <0C>8c <0C>Ȝ<><C89C>vws<00> <0C>Ȝ<><C89C><EFBFBD><07><>Ȝ<EFBFBD><C89C>wss<00><00><07><>Ȝ<EFBFBD><C89C><EFBFBD><07><>8c0 <0A>x<00><00>y<00><><EFBFBD><EFBFBD>x<EFBFBD><78><EFBFBD>1 <0A>yx<00><><EFBFBD><EFBFBD>x<EFBFBD><78><EFBFBD>U*( <09>z<00><00>
规范化命名与封装
2024-03-12 21:14:52 +08:00
<Cadence_Material_Lib Version="1.050">
<Material name="AIR">
<Flags>
<v>Used</v>
</Flags>
<Dielectric>
<Model>1000 1 0
</Model>
</Dielectric>
<Thermal>
<Model>27 0.0267 1.177 1005 0 0
37 0.0274 1.141 1005 0 0
47 0.0281 1.106 1006 0 0
57 0.0287 1.073 1006 0 0
67 0.0294 1.042 1007 0 0
77 0.03 1.012 1007 0 0
87 0.0306 0.983 1007 0 0
97 0.0313 0.956 1008 0 0
107 0.0319 0.931 1008 0 0
117 0.0325 0.906 1009 0 0
127 0.0331 0.883 1009 0 0
227 0.0389 0.706 1017 0 0
</Model>
</Thermal>
</Material>
<Material DefaultThickness="0.03048MM" name="COPPER">
<Flags>
<v>Used</v>
</Flags>
<Metal>
<Model>20 5.96e+07
25 5.8e+07
40 5.528757e+07
60 5.155709e+07
80 4.829822e+07
100 4.542683e+07
120 4.28777e+07
140 4.059946e+07
</Model>
</Metal>
<Thermal>
<Model>27 401 8933 385 0.07 0
127 393 8933 397 0.07 0
227 386 8933 412 0.07 0
327 379 8933 417 0.07 0
527 366 8933 433 0.07 0
727 352 8933 451 0.07 0
927 339 8933 480 0.07 0
</Model>
</Thermal>
<Structural>
<Elasticity>2.500000e+01 1.210000e+11 3.800000e-01</Elasticity>
<CTE RefTemperature="20">2.500000e+01 1.775000e-05</CTE>
<Viscoplastic>
<Anand Enable="false">0 0 0 0 0 0 0 0 0</Anand>
<ModifiedAnand Enable="false">0 0 0 0 0 0 0 0 0 0 0 0 0 0</ModifiedAnand>
</Viscoplastic>
<Fatigue>
<Darveaux Enable="false">0 0 0 0 0 0 0</Darveaux>
<Solomon Enable="false">0 0</Solomon>
</Fatigue>
<Failure>
<Tension Enable="false">0</Tension>
<Compression Enable="false">0</Compression>
<MaxPressure Enable="false">0</MaxPressure>
<EffectiveStrain Enable="false">0</EffectiveStrain>
<MaxStrain Enable="false">0</MaxStrain>
</Failure>
</Structural>
</Material>
<Material DefaultThickness="0.2032MM" name="FR-4">
<Flags>
<v>Used</v>
</Flags>
<Dielectric>
<Model>1000 4.5 0.035
</Model>
</Dielectric>
<Thermal>
<Model>25 0.23 1900 1200 0 0
</Model>
</Thermal>
<Structural>
<Elasticity>2.500000e+01 1.800000e+10 3.000000e-01</Elasticity>
<CTE RefTemperature="20">2.500000e+01 2.220000e-05</CTE>
<Viscoplastic>
<Anand Enable="false">0 0 0 0 0 0 0 0 0</Anand>
<ModifiedAnand Enable="false">0 0 0 0 0 0 0 0 0 0 0 0 0 0</ModifiedAnand>
</Viscoplastic>
<Fatigue>
<Darveaux Enable="false">0 0 0 0 0 0 0</Darveaux>
<Solomon Enable="false">0 0</Solomon>
</Fatigue>
<Failure>
<Tension Enable="false">0</Tension>
<Compression Enable="false">0</Compression>
<MaxPressure Enable="false">0</MaxPressure>
<EffectiveStrain Enable="false">0</EffectiveStrain>
<MaxStrain Enable="false">0</MaxStrain>
</Failure>
</Structural>
</Material>
</Cadence_Material_Lib>
更加标准化，修改了一下颜色 每一张封装加入三个参数： LAST EDIT：最后修改时间 Approved：审核次数，最少是1（画完的时候简单审核一下） *UNTESTED*:如果该封装没有被实际打出来测试过，就会有这个标识
2024-03-16 22:21:25 +08:00
;)CVLayerSettings<00>i<EFBFBD>e<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
规范化命名与封装
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<!-- Allegro Color/Visibility Layer Settings -->
<!-- Contains layer settings for the Color Dialog and Visiblity Pane -->
<!-- Version 4.0 -->
<ColorVisibility>
<Layers>
<LayerStackUp name="PRIMARY"/>
</Layers>
</ColorVisibility>
更新一些封装
2024-03-23 02:02:12 +08:00
;<00>_QuickViewText_QUICKVIEWS<00><><EFBFBD>eMINX=0|MINY=0|MAXX=8825|MAXY=3695|BK_RED=0|BK_GRN=0|BK_BLU=0|STRING=Name: thr_dip_2x5
规范化命名与封装
2024-03-12 21:14:52 +08:00
Type: Package
Units: Millimeters
Accuracy: 4
Pins: 10
更新一些封装
2024-03-23 02:02:12 +08:00
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规范化命名与封装
2024-03-12 21:14:52 +08:00
<Allegro3DSelectState_version_1_0>
<Clines selected="true"/>
<Lines selected="true"/>
<Text selected="true"/>
<Pins selected="true"/>
<Vias selected="true"/>
<Shapes selected="true"/>
<Rectangles selected="true"/>
<Symbols selected="true"/>
<Masks selected="true"/>
<Dielectrics selected="true"/>
</Allegro3DSelectState_version_1_0>
更新一些封装
2024-03-23 02:02:12 +08:00
;DFACSET_DBAttachFile<00><><EFBFBD>e;NEW_DB_FEATURES<00><><EFBFBD>e;!ALLEGRO_DESIGN_WAS_LAST_SAVED<00><><EFBFBD>ecreate_sym 17.4 S035 - 1/14/2023
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