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XerolySkinner
2024-04-10 11:05:21 +08:00
parent cc74dafad2
commit 0570548c91
30 changed files with 39134 additions and 4425 deletions
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chip/stepFacetFiles4Map/stepFileInfo.txt
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@@ -5,6 +5,7 @@ tssop8.STEP ! 174674 ! 1711377980
lqfp48.step ! 1919983 ! 1711219780 lqfp48.step ! 1919983 ! 1711219780
D8-L.step ! 282667 ! 1568096060 D8-L.step ! 282667 ! 1568096060
DIP_2x5.step ! 720870 ! 1710578258 DIP_2x5.step ! 720870 ! 1710578258
SSOP-8.step ! 755497 ! 1712718221
ESP-01.step ! 2352878 ! 1710578258 ESP-01.step ! 2352878 ! 1710578258
LQFP64.step ! 14347354 ! 1710578258 LQFP64.step ! 14347354 ! 1710578258
sop-8.STEP ! 273188 ! 1710578258 sop-8.STEP ! 273188 ! 1710578258

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chip/stepFacetFiles4Map/stepFileInfo.txt,1
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@@ -1,6 +1,7 @@
#STEP_FILE ! FILE_SIZE ! MOD_TIME #STEP_FILE ! FILE_SIZE ! MOD_TIME
D8-M.step ! 282667 ! 1568096060 D8-M.step ! 282667 ! 1568096060
tssop8.STEP ! 174674 ! 1711377980
lqfp48.step ! 1919983 ! 1711219780 lqfp48.step ! 1919983 ! 1711219780
D8-L.step ! 282667 ! 1568096060 D8-L.step ! 282667 ! 1568096060
DIP_2x5.step ! 720870 ! 1710578258 DIP_2x5.step ! 720870 ! 1710578258

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orcad_template/template.opj
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@@ -1,6 +1,6 @@
(ExpressProject "template" (ExpressProject "template"
(ProjectVersion "19981106") (ProjectVersion "19981106")
(SoftwareVersion "17.4-2019 S035 (4083846) [1/14/2023]-[04/08/24]") (SoftwareVersion "17.4-2019 S035 (4083846) [1/14/2023]-[04/10/24]")
(ProjectType "PCB") (ProjectType "PCB")
(Folder "Design Resources" (Folder "Design Resources"
(Folder "Library") (Folder "Library")
@@ -28,13 +28,9 @@
(GlobalState (GlobalState
(FileView (FileView
(Path "Design Resources") (Path "Design Resources")
(Path "Design Resources" (Path "Design Resources" ".\template.dsn")
"d:\workspace\github\pcb_lib\orcad_template\template.dsn") (Path "Design Resources" ".\template.dsn" "TEMPLATE")
(Path "Design Resources" (Select "Design Resources" ".\template.dsn" "TEMPLATE" "3:485"))
"d:\workspace\github\pcb_lib\orcad_template\template.dsn" "TEMPLATE")
(Select "Design Resources"
"d:\workspace\github\pcb_lib\orcad_template\template.dsn" "TEMPLATE"
"1:POWER"))
(HierarchyView) (HierarchyView)
(Doc (Doc
(Type "COrCapturePMDoc") (Type "COrCapturePMDoc")
@@ -44,21 +40,11 @@
(Doc (Doc
(Type "COrSchematicDoc") (Type "COrSchematicDoc")
(Frame (Frame
(Placement "44 0 1 -1 -1 -1 -1 5 913 28 666") (Placement "44 0 1 -1 -1 -1 -1 5 940 28 666")
(Scroll "0 0") (Scroll "0 0")
(Zoom "114") (Zoom "100")
(Occurrence "/")) (Occurrence "/"))
(Path "D:\WORKSPACE\GITHUB\PCB_LIB\ORCAD_TEMPLATE\TEMPLATE.DSN") (Path "D:\¹¤×÷¿â\GITHUB\PCB_LIB\ORCAD_TEMPLATE\TEMPLATE.DSN")
(Schematic "TEMPLATE")
(Page "1:POWER"))
(Doc
(Type "COrSchematicDoc")
(Frame
(Placement "44 0 1 -1 -1 -1 -1 5 913 28 666")
(Scroll "0 0")
(Zoom "200")
(Occurrence "/"))
(Path "D:\WORKSPACE\GITHUB\PCB_LIB\ORCAD_TEMPLATE\TEMPLATE.DSN")
(Schematic "TEMPLATE") (Schematic "TEMPLATE")
(Page "2:USB-CNT"))) (Page "2:USB-CNT")))
(MPSSessionName "XerolySkinner")) (MPSSessionName "XerolySkinner"))

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smc/allegro.jrl
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\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Mon Apr 8 23:55:40 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=15624 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\smc\f0603.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:05) Opening existing design...
\i (00:00:05) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged f0603
\d (00:00:05) Design opened: D:/workspace/GitHub/pcb_lib/smc/f0603.dra
\i (00:00:05) trapsize 431
\i (00:00:06) trapsize 442
\i (00:00:06) trapsize 431
\i (00:00:06) trapsize 378
\i (00:00:06) trapsize 388
\i (00:00:06) trapsize 399
\i (00:00:06) trapsize 512
\i (00:00:10) delete
\i (00:00:12) pick grid 5.0467 0.9783
\t (00:00:12) last pick: 5.0000 1.0000
\t (00:00:12) Text "Approved[1]"
\i (00:00:13) pick grid 5.3131 -0.3948
\t (00:00:13) last pick: 5.3000 -0.4000
\t (00:00:13) Text "*Tested Pass*"
\i (00:00:14) pick grid 6.1226 0.4762
\t (00:00:14) last pick: 6.1000 0.5000
\i (00:00:14) prepopup 6.1226 0.4762
\i (00:00:15) done
\i (00:00:17) text edit
\i (00:00:17) pick grid 1.2451 1.9620
\t (00:00:17) last pick: 1.2000 2.0000
\i (00:00:25) setwindow pcb
\i (00:00:25) pick 1.2451 1.9620
\t (00:00:25) Pick text to edit.
\i (00:00:32) step pkg map
\i (00:00:33) fillin yes
\i (00:00:44) setwindow form.pkgmap3d
\i (00:00:44) FORM pkgmap3d stplist f0603.step
\i (00:00:48) FORM pkgmap3d view_orientation 'Front Left'
\i (00:00:52) FORM pkgmap3d view_orientation Back
\i (00:00:55) FORM pkgmap3d save_current
\i (00:00:57) FORM pkgmap3d done
\i (00:00:58) setwindow pcb
\i (00:00:58) exit
\e (00:00:58) Do you want to save the changes you made to f0603.dra?
\i (00:00:58) fillin yes
\t (00:00:59) Symbol 'f0603.psm' created.
\t (00:00:59) Journal end - Mon Apr 8 23:56:37 2024

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smc/downrev.log
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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : f0603.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Apr 8 23:56:36 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

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smc/downrev.log,1
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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : f0603.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Apr 8 23:56:36 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

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smc/downrev.log,2
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@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : f0603.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Apr 8 23:56:36 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

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smc/f0603.log
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@@ -1,23 +0,0 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : f0603.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Apr 8 23:56:36 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = f0603.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

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thr/stepFacetFiles4Map/stepFileInfo.txt
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@@ -2,7 +2,7 @@
EPS01S.step ! 2352785 ! 1711681659 EPS01S.step ! 2352785 ! 1711681659
CONN-4P-P5.STEP ! 1114691 ! 1711644010 CONN-4P-P5.STEP ! 1114691 ! 1711644010
CONN-2P.STEP ! 360048 ! 1712416291 CONN-2P.STEP ! 539429 ! 1712710914
thr-3r090tb.step ! 2404583 ! 1711452688 thr-3r090tb.step ! 2404583 ! 1711452688
DIP_2x5.step ! 720870 ! 1710578258 DIP_2x5.step ! 720870 ! 1710578258
CONN-2P-P5.step ! 1193777 ! 1710578258 CONN-2P-P5.step ! 1193777 ! 1710578258

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thr/stepFacetFiles4Map/stepFileInfo.txt,1
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@@ -2,7 +2,7 @@
EPS01S.step ! 2352785 ! 1711681659 EPS01S.step ! 2352785 ! 1711681659
CONN-4P-P5.STEP ! 1114691 ! 1711644010 CONN-4P-P5.STEP ! 1114691 ! 1711644010
CONN-2P.STEP ! 247778 ! 1711988735 CONN-2P.STEP ! 360048 ! 1712416291
thr-3r090tb.step ! 2404583 ! 1711452688 thr-3r090tb.step ! 2404583 ! 1711452688
DIP_2x5.step ! 720870 ! 1710578258 DIP_2x5.step ! 720870 ! 1710578258
CONN-2P-P5.step ! 1193777 ! 1710578258 CONN-2P-P5.step ! 1193777 ! 1710578258

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