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更新了一些3D模型和电感

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This commit is contained in:
XerolySkinner
2024-03-24 03:27:26 +08:00
parent fc470544d4
commit 16d073e645
64 changed files with 133060 additions and 87 deletions
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33
chip/allegro.jrl Normal file
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\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:03) Journal start - Sun Mar 24 02:50:56 2024
\t (00:00:03) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=11324 CPUs=12
\t (00:00:03) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\chip\sop-8-gnd.dra
\t (00:00:03)
(00:00:03) Loading axlcore.cxt
\t (00:00:03) Opening existing design...
\i (00:00:03) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sop-8-gnd"
\d (00:00:03) Design opened: D:/workspace/GitHub/pcb_lib/chip/sop-8-gnd.dra
\i (00:00:04) trapsize 53
\i (00:00:04) trapsize 54
\i (00:00:04) trapsize 53
\i (00:00:05) trapsize 61
\i (00:00:05) trapsize 63
\i (00:00:06) updateport CVPane
\i (00:00:06) shapeedit
\i (00:00:12) step pkg map
\i (00:00:13) fillin yes
\i (00:00:17) setwindow form.pkgmap3d
\i (00:00:17) FORM pkgmap3d rotation_z 0
\i (00:00:20) FORM pkgmap3d rotation_z -90
\i (00:00:24) FORM pkgmap3d rotation_z 90
\i (00:00:26) FORM pkgmap3d save_current
\i (00:00:28) FORM pkgmap3d rotation_z -90
\i (00:00:30) FORM pkgmap3d save_current
\i (00:00:32) FORM pkgmap3d done
\i (00:00:32) setwindow pcb
\i (00:00:32) shapeedit
\i (00:00:33) exit
\e (00:00:33) Do you want to save the changes you made to sop-8-gnd.dra?
\i (00:00:33) fillin yes
\t (00:00:34) Symbol 'sop-8-gnd.psm' created.
\t (00:00:34) Journal end - Sun Mar 24 02:51:27 2024

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chip/allegro.jrl,1 Normal file
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\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:03) Journal start - Sun Mar 24 02:48:07 2024
\t (00:00:03) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=22416 CPUs=12
\t (00:00:03) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\chip\lqfp48.dra
\t (00:00:03)
(00:00:03) Loading axlcore.cxt
\t (00:00:03) Opening existing design...
\i (00:00:03) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged lqfp48
\d (00:00:04) Design opened: D:/workspace/GitHub/pcb_lib/chip/lqfp48.dra
\i (00:00:04) trapsize 57
\i (00:00:04) trapsize 59
\i (00:00:05) trapsize 57
\i (00:00:05) trapsize 66
\i (00:00:05) trapsize 68
\i (00:00:06) updateport CVPane
\i (00:00:06) shapeedit
\i (00:02:04) step pkg map
\i (00:02:05) fillin yes
\i (00:02:10) setwindow form.pkgmap3d
\i (00:02:10) FORM pkgmap3d stplist lqfp48.step
\i (00:02:13) FORM pkgmap3d overlay YES
\i (00:02:16) FORM pkgmap3d save_current
\i (00:02:19) FORM pkgmap3d done
\i (00:02:19) setwindow pcb
\i (00:02:19) shapeedit
\i (00:02:20) exit
\e (00:02:20) Do you want to save the changes you made to lqfp48.dra?
\i (00:02:21) fillin yes
\t (00:02:21) Symbol 'lqfp48.psm' created.
\t (00:02:22) Journal end - Sun Mar 24 02:50:26 2024

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chip/downrev.log Normal file
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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : sop-8-gnd.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:51:26 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : lqfp48.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:50:25 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : sop-8-gnd.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:51:26 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
chip/downrev.log,3 Normal file
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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : sop-8-gnd.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:51:26 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

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chip/lqfp48.dra
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chip/lqfp48.log Normal file
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(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : lqfp48.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:50:25 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = lqfp48.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

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chip/lqfp48.psm
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chip/sop-8-gnd.dra
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chip/sop-8-gnd.log Normal file
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(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : sop-8-gnd.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:51:26 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = sop-8-gnd.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

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chip/sop-8-gnd.psm
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60874
chip/stepFacetFiles4Map/lqfp48.xml Normal file
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chip/stepFacetFiles4Map/stepFileInfo.txt
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#STEP_FILE ! FILE_SIZE ! MOD_TIME
D8-M.step ! 282667 ! 1568096060
lqfp48.step ! 1919983 ! 1711219780
D8-L.step ! 282667 ! 1568096060
DIP_2x5.step ! 720870 ! 1710578258
ESP-01.step ! 2352878 ! 1710578258

1
chip/stepFacetFiles4Map/stepFileInfo.txt,1
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#STEP_FILE ! FILE_SIZE ! MOD_TIME
D8-M.step ! 282667 ! 1568096060
lqfp48.step ! 1919983 ! 1711219780
D8-L.step ! 282667 ! 1568096060
DIP_2x5.step ! 720870 ! 1710578258
ESP-01.step ! 2352878 ! 1710578258