xerolyskinner/pcb_lib
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

更新了一些3D模型和电感

Browse Source
This commit is contained in:
XerolySkinner
2024-03-24 03:27:26 +08:00
parent fc470544d4
commit 16d073e645
64 changed files with 133060 additions and 87 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
smc/allegro.jrl Normal file
View File

@@ -0,0 +1,33 @@
\t (00:00:05) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:05) Journal start - Sun Mar 24 02:59:48 2024
\t (00:00:05) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=25828 CPUs=12
\t (00:00:05) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\smc\sod-l6-w3.dra
\t (00:00:05)
(00:00:05) Loading axlcore.cxt
\t (00:00:05) Opening existing design...
\i (00:00:05) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sod-l6-w3"
\d (00:00:05) Design opened: D:/workspace/GitHub/pcb_lib/smc/sod-l6-w3.dra
\i (00:00:05) trapsize 1180
\i (00:00:06) trapsize 1212
\i (00:00:06) trapsize 1180
\t (00:00:07) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:07) trapsize 1368
\t (00:00:07) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:07) trapsize 1404
\i (00:00:07) updateport CVPane
\i (00:00:08) shapeedit
\i (00:00:11) step pkg map
\i (00:00:12) fillin yes
\i (00:00:20) setwindow form.pkgmap3d
\i (00:00:20) FORM pkgmap3d overlay YES
\i (00:00:30) FORM pkgmap3d stplist RES_CRCW_2512.step
\i (00:00:31) FORM pkgmap3d stplist SMA-DO-214AC.step
\i (00:00:38) FORM pkgmap3d save_current
\i (00:00:40) FORM pkgmap3d done
\i (00:00:41) setwindow pcb
\i (00:00:41) shapeedit
\i (00:00:41) exit
\e (00:00:41) Do you want to save the changes you made to sod-l6-w3.dra?
\i (00:00:42) fillin yes
\t (00:00:42) Symbol 'sod-l6-w3.psm' created.
\t (00:00:43) Journal end - Sun Mar 24 03:00:26 2024

31
smc/allegro.jrl,1 Normal file
View File

@@ -0,0 +1,31 @@
\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:03) Journal start - Sun Mar 24 02:51:39 2024
\t (00:00:03) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=13704 CPUs=12
\t (00:00:03) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\smc\sod-l4_6-w2_2.dra
\t (00:00:03)
(00:00:03) Loading axlcore.cxt
\t (00:00:03) Opening existing design...
\i (00:00:03) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sod-l4_6-w2_2"
\d (00:00:03) Design opened: D:/workspace/GitHub/pcb_lib/smc/sod-l4_6-w2_2.dra
\i (00:00:04) trapsize 257
\i (00:00:04) trapsize 264
\i (00:00:04) trapsize 257
\i (00:00:04) trapsize 298
\i (00:00:05) trapsize 306
\i (00:00:05) updateport CVPane
\i (00:00:05) shapeedit
\i (00:00:11) step pkg map
\i (00:00:12) fillin yes
\i (00:00:15) setwindow form.pkgmap3d
\i (00:00:15) FORM pkgmap3d rotation_z -90
\i (00:00:16) FORM pkgmap3d save_current
\i (00:00:18) FORM pkgmap3d rotation_z 90
\i (00:00:20) FORM pkgmap3d save_current
\i (00:00:21) FORM pkgmap3d done
\i (00:00:21) setwindow pcb
\i (00:00:21) shapeedit
\i (00:00:21) exit
\e (00:00:21) Do you want to save the changes you made to sod-l4_6-w2_2.dra?
\i (00:00:22) fillin yes
\t (00:00:22) Symbol 'sod-l4_6-w2_2.psm' created.
\t (00:00:23) Journal end - Sun Mar 24 02:51:58 2024

14
smc/downrev.log Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : sod-l6-w3.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 03:00:26 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
smc/downrev.log,1 Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : sod-l4_6-w2_2.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:51:58 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
smc/downrev.log,2 Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : sod-l6-w3.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 03:00:25 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
smc/downrev.log,3 Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : sod-l6-w3.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 03:00:25 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

BIN
smc/sod-l12_4-w6_4.dra
View File

Binary file not shown.

23
smc/sod-l12_4-w6_4.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : sod-l12_4-w6_4.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:47:56 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = sod-l12_4-w6_4.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
smc/sod-l12_4-w6_4.psm
View File

Binary file not shown.

BIN
smc/sod-l4_6-w2_2.dra
View File

Binary file not shown.

23
smc/sod-l4_6-w2_2.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : sod-l4_6-w2_2.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:51:58 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = sod-l4_6-w2_2.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
smc/sod-l4_6-w2_2.psm
View File

Binary file not shown.

BIN
smc/sod-l6-w3.dra
View File

Binary file not shown.

23
smc/sod-l6-w3.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : sod-l6-w3.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 03:00:26 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = sod-l6-w3.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
smc/sod-l6-w3.psm
View File

Binary file not shown.

1593
smc/stepFacetFiles4Map/RES_CRCW_2512.xml Normal file
View File

File diff suppressed because it is too large Load Diff

7408
smc/stepFacetFiles4Map/SMA-DO-214AC.xml Normal file
View File

File diff suppressed because it is too large Load Diff

8109
smc/stepFacetFiles4Map/SMC.xml Normal file
View File

File diff suppressed because it is too large Load Diff

3
smc/stepFacetFiles4Map/stepFileInfo.txt
View File

@@ -1,8 +1,11 @@
#STEP_FILE ! FILE_SIZE ! MOD_TIME
C0603.stp ! 74996 ! 1710578258
SMA-DO-214AC.step ! 213070 ! 1710578258
SMC.step ! 207133 ! 1710578258
TS-POINT.STEP ! 23849 ! 1710578258
SOD-123FL.step ! 331135 ! 1710578258
LED_0603_G.STEP ! 178570 ! 1710578258
KEY_SOT_P2.step ! 151224 ! 1710578258
RES_CRCW_2512.step ! 33456 ! 1568096060
R0603.step ! 652348 ! 1710578258

2
smc/stepFacetFiles4Map/stepFileInfo.txt,1
View File

@@ -1,7 +1,9 @@
#STEP_FILE ! FILE_SIZE ! MOD_TIME
C0603.stp ! 74996 ! 1710578258
SMC.step ! 207133 ! 1710578258
TS-POINT.STEP ! 23849 ! 1710578258
SOD-123FL.step ! 331135 ! 1710578258
LED_0603_G.STEP ! 178570 ! 1710578258
KEY_SOT_P2.step ! 151224 ! 1710578258
R0603.step ! 652348 ! 1710578258