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XerolySkinner
2024-03-27 12:26:02 +08:00
parent 16d073e645
commit 57373f1805
89 changed files with 298939 additions and 2947 deletions
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3D/STL90N10F7.STEP Normal file
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7599
3D/ll34.step Normal file
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23857
3D/thr-3r090tb.step Normal file
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2355
3D/tssop8.STEP Normal file
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57671
3D/ufqfpn28_2.step Normal file
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3590
XerolySkinner.prm
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BIN
basic_lib/BASIC_OBJ.OLB
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BIN
basic_lib/BASIC_OBJ_0.OBK
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13
basic_lib/basic_obj.opj
View File

@@ -28,10 +28,19 @@
(FileView
(Path "Design Resources")
(Path "Design Resources"
"d:\workspace\github\pcb_lib\basic_lib\basic_obj.olb")
(Select "Design Resources"
"d:\workspace\github\pcb_lib\basic_lib\basic_obj.olb"))
(HierarchyView)
(Doc
(Type "COrCapturePMDoc")
(Frame
(Placement "44 0 1 -1 -1 -1 -1 0 200 0 509"))
(Tab 0))))
(Placement "44 0 1 -1 -1 -1 -1 0 200 0 533"))
(Tab 0))
(Doc
(Type "COrPrmBrowserDoc")
(Frame
(Placement "44 0 1 -1 -1 -8 -31 5 1099 28 555"))
(Path "D:\WORKSPACE\GITHUB\PCB_LIB\BASIC_LIB\BASIC_OBJ.OLB")
(Package "INA240A1")
(PartType "1"))))

33
chip/allegro.jrl
View File

@@ -1,33 +0,0 @@
\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:03) Journal start - Sun Mar 24 02:50:56 2024
\t (00:00:03) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=11324 CPUs=12
\t (00:00:03) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\chip\sop-8-gnd.dra
\t (00:00:03)
(00:00:03) Loading axlcore.cxt
\t (00:00:03) Opening existing design...
\i (00:00:03) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sop-8-gnd"
\d (00:00:03) Design opened: D:/workspace/GitHub/pcb_lib/chip/sop-8-gnd.dra
\i (00:00:04) trapsize 53
\i (00:00:04) trapsize 54
\i (00:00:04) trapsize 53
\i (00:00:05) trapsize 61
\i (00:00:05) trapsize 63
\i (00:00:06) updateport CVPane
\i (00:00:06) shapeedit
\i (00:00:12) step pkg map
\i (00:00:13) fillin yes
\i (00:00:17) setwindow form.pkgmap3d
\i (00:00:17) FORM pkgmap3d rotation_z 0
\i (00:00:20) FORM pkgmap3d rotation_z -90
\i (00:00:24) FORM pkgmap3d rotation_z 90
\i (00:00:26) FORM pkgmap3d save_current
\i (00:00:28) FORM pkgmap3d rotation_z -90
\i (00:00:30) FORM pkgmap3d save_current
\i (00:00:32) FORM pkgmap3d done
\i (00:00:32) setwindow pcb
\i (00:00:32) shapeedit
\i (00:00:33) exit
\e (00:00:33) Do you want to save the changes you made to sop-8-gnd.dra?
\i (00:00:33) fillin yes
\t (00:00:34) Symbol 'sop-8-gnd.psm' created.
\t (00:00:34) Journal end - Sun Mar 24 02:51:27 2024

30
chip/allegro.jrl,1
View File

@@ -1,30 +0,0 @@
\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:03) Journal start - Sun Mar 24 02:48:07 2024
\t (00:00:03) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=22416 CPUs=12
\t (00:00:03) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\chip\lqfp48.dra
\t (00:00:03)
(00:00:03) Loading axlcore.cxt
\t (00:00:03) Opening existing design...
\i (00:00:03) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged lqfp48
\d (00:00:04) Design opened: D:/workspace/GitHub/pcb_lib/chip/lqfp48.dra
\i (00:00:04) trapsize 57
\i (00:00:04) trapsize 59
\i (00:00:05) trapsize 57
\i (00:00:05) trapsize 66
\i (00:00:05) trapsize 68
\i (00:00:06) updateport CVPane
\i (00:00:06) shapeedit
\i (00:02:04) step pkg map
\i (00:02:05) fillin yes
\i (00:02:10) setwindow form.pkgmap3d
\i (00:02:10) FORM pkgmap3d stplist lqfp48.step
\i (00:02:13) FORM pkgmap3d overlay YES
\i (00:02:16) FORM pkgmap3d save_current
\i (00:02:19) FORM pkgmap3d done
\i (00:02:19) setwindow pcb
\i (00:02:19) shapeedit
\i (00:02:20) exit
\e (00:02:20) Do you want to save the changes you made to lqfp48.dra?
\i (00:02:21) fillin yes
\t (00:02:21) Symbol 'lqfp48.psm' created.
\t (00:02:22) Journal end - Sun Mar 24 02:50:26 2024

14
chip/downrev.log
View File

@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : sop-8-gnd.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:51:26 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
chip/downrev.log,1
View File

@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : lqfp48.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:50:25 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
chip/downrev.log,2
View File

@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : sop-8-gnd.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:51:26 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
chip/downrev.log,3
View File

@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : sop-8-gnd.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:51:26 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

23
chip/sop-8-gnd.log
View File

@@ -1,23 +0,0 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : sop-8-gnd.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:51:26 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = sop-8-gnd.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

3
chip/stepFacetFiles4Map/stepFileInfo.txt
View File

@@ -1,12 +1,15 @@
#STEP_FILE ! FILE_SIZE ! MOD_TIME
D8-M.step ! 282667 ! 1568096060
tssop8.STEP ! 174674 ! 1711377980
lqfp48.step ! 1919983 ! 1711219780
D8-L.step ! 282667 ! 1568096060
DIP_2x5.step ! 720870 ! 1710578258
ESP-01.step ! 2352878 ! 1710578258
LQFP64.step ! 14347354 ! 1710578258
sop-8.STEP ! 273188 ! 1710578258
tssop8.step ! 306368 ! 1711457082
LED_0603_G.STEP ! 178570 ! 1710578258
KEY_SOT_P2.step ! 151224 ! 1710578258
sop-14.step ! 521672 ! 1710578258
ufqfpn28_2.step ! 4307335 ! 1711439232

2
chip/stepFacetFiles4Map/stepFileInfo.txt,1
View File

@@ -7,6 +7,8 @@ DIP_2x5.step ! 720870 ! 1710578258
ESP-01.step ! 2352878 ! 1710578258
LQFP64.step ! 14347354 ! 1710578258
sop-8.STEP ! 273188 ! 1710578258
tssop8.step ! 306368 ! 1711457082
LED_0603_G.STEP ! 178570 ! 1710578258
KEY_SOT_P2.step ! 151224 ! 1710578258
sop-14.step ! 521672 ! 1710578258
ufqfpn28_2.step ! 4307335 ! 1711439232

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129364
chip/stepFacetFiles4Map/ufqfpn28_2.xml Normal file
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BIN
chip/tssop-8.dra Normal file
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BIN
chip/tssop-8.pad Normal file
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BIN
chip/tssop-8.psm Normal file
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BIN
chip/ufqfpn28.dra
View File

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BIN
chip/ufqfpn28.psm
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BIN
hold/thr-1r02_1r8.dra
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BIN
hold/thr-1r02_1r8.fsm Normal file
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BIN
hold/thr-1r3-2r0.dra
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BIN
hold/thr-1r3-2r0.fsm Normal file
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BIN
hold/via_0_2-f.pad → hold/via_0_3.pad
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627
ind_smd/allegro.jrl
View File

@@ -1,627 +0,0 @@
\t (00:00:04) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:04) Journal start - Sun Mar 24 00:19:37 2024
\t (00:00:04) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=29220 CPUs=12
\t (00:00:04) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\ind_smd\l1205.dra
\t (00:00:04)
(00:00:04) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged l1205
\d (00:00:04) Design opened: D:/workspace/GitHub/pcb_lib/ind_smd/l1205.dra
\i (00:00:04) trapsize 282
\i (00:00:05) trapsize 290
\i (00:00:05) trapsize 282
\i (00:00:05) trapsize 327
\i (00:00:05) trapsize 336
\i (00:00:06) updateport CVPane
\i (00:00:06) shapeedit
\i (00:00:09) zoom out 1
\i (00:00:09) setwindow pcb
\i (00:00:09) zoom out 8.0474 -1.2675
\i (00:00:09) trapsize 671
\i (00:00:09) zoom out 1
\i (00:00:09) setwindow pcb
\i (00:00:09) zoom out 8.0473 -1.2675
\t (00:00:09) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:09) trapsize 1343
\i (00:00:09) zoom out 1
\i (00:00:09) setwindow pcb
\i (00:00:09) zoom out 8.0475 -1.2675
\i (00:00:09) trapsize 2483
\i (00:00:10) zoom in 1
\i (00:00:10) setwindow pcb
\i (00:00:10) zoom in 3.3019 1.1172
\i (00:00:10) trapsize 1241
\i (00:00:12) new
\i (00:00:25) newdrawfillin "i0603.dra" "Package Symbol"
\t (00:00:25) Starting new design...
\i (00:00:25) trapsize 2146
\i (00:00:25) trapsize 2212
\i (00:00:25) trapsize 2146
\t (00:00:26) Grids are drawn 162.5600, 162.5600 apart for enhanced viewing.
\i (00:00:27) trapsize 2483
\i (00:00:27) trapsize 2483
\i (00:00:27) shapeedit
\i (00:00:46) new
\e (00:00:46) Do you want to save the changes you made to i0603.dra?
\i (00:00:47) fillin no
\i (00:00:53) newdrawfillin "i0630.dra" "Package Symbol"
\t (00:00:53) Starting new design...
\i (00:00:56) trapsize 2146
\i (00:00:56) trapsize 2212
\i (00:00:56) trapsize 2146
\i (00:00:57) trapsize 2483
\i (00:00:57) trapsize 2483
\i (00:00:57) shapeedit
\i (00:01:01) param in
\i (00:01:02) setwindow form.parm_in
\i (00:01:02) FORM parm_in browse
\i (00:01:06) fillin "D:/workspace/GitHub/pcb_lib/XerolySkinner.prm"
\i (00:01:07) FORM parm_in execute
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\t (00:01:07) Opening existing design...
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\i (00:01:08) setwindow pcb
\i (00:01:08) trapsize 2572
\i (00:01:08) trapsize 2668
\i (00:01:08) trapsize 2572
\t (00:01:08) Grids are drawn 0.4000, 0.4000 apart for enhanced viewing.
\i (00:01:08) trapsize 2572
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\i (00:01:09) trapsize 2483
\i (00:01:09) updateport CVPane
\t (00:01:10) Parameter file read completed.
\i (00:01:13) setwindow form.parm_in
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\i (00:01:13) setwindow pcb
\i (00:01:13) shapeedit
\i (00:01:16) add pin
\i (00:01:28) setwindow form.mini
\i (00:01:28) FORM mini x_count 2
\i (00:01:33) FORM mini pad_name i0630
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\i (00:01:38) FORM mini text_name pin
\i (00:01:59) setwindow pcb
\i (00:01:59) pick -3.7 0
\t (00:01:59) last pick: -3.7000 0.0000
\t (00:01:59) Using 'I0630.pad'.
\i (00:02:03) prepopup -3.0536 -1.7130
\i (00:02:04) oops
\t (00:02:04) Using 'I0630.pad'.
\i (00:02:11) setwindow form.mini
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\i (00:02:14) FORM mini next_pin_number 1
\i (00:02:23) setwindow pcb
\i (00:02:23) pick -3.7 0
\t (00:02:23) last pick: -3.7000 0.0000
\t (00:02:23) Using 'I0630.pad'.
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\i (00:02:32) done
\t (00:02:32) Exiting from Add Pin.
\i (00:02:32) shapeedit
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\i (00:02:33) trapsize 621
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\i (00:02:34) trapsize 621
\i (00:02:36) move
\t (00:02:36) Select element(s) to move.
\i (00:02:39) drag_start grid -5.9334 1.9365
\i (00:02:39) drag_stop 6.5170 -5.2383
\i (00:02:40) pick grid 6.5170 -5.2383
\t (00:02:40) last pick: 6.5000 -5.2000
\t (00:02:40) Pick new location for the element(s).
\i (00:02:41) pick grid 6.7156 -3.9598
\t (00:02:41) last pick: 6.7000 -4.0000
\i (00:02:41) prepopup 5.6853 -4.5432
\i (00:02:42) done
\i (00:02:42) shapeedit
\i (00:02:44) add line
\i (00:02:50) setwindow form.mini
\i (00:02:50) FORM mini class 'PACKAGE GEOMETRY'
\i (00:02:52) FORM mini subclass SILKSCREEN_TOP
\i (00:02:52) setwindow pcb
\i (00:02:52) updateport CVPane
\i (00:02:56) setwindow form.mini
\i (00:02:56) FORM mini line_width 0.1500
\i (00:03:26) setwindow pcb
\i (00:03:26) pick -3.7 3.3
\t (00:03:26) last pick: -3.7000 3.3000
\i (00:03:33) ipick 7.4
\t (00:03:33) last pick: 3.7000 3.3000
\i (00:03:46) setwindow form.mini
\i (00:03:46) FORM mini lock_direction 90
\i (00:03:48) setwindow pcb
\i (00:03:48) zoom in 1
\i (00:03:48) setwindow pcb
\i (00:03:48) zoom in 3.5130 2.0110
\i (00:03:48) trapsize 310
\i (00:03:48) zoom in 1
\i (00:03:48) setwindow pcb
\i (00:03:48) zoom in 3.5130 2.0110
\i (00:03:48) trapsize 155
\i (00:03:48) zoom in 1
\i (00:03:48) setwindow pcb
\i (00:03:48) zoom in 3.5130 2.0110
\i (00:03:48) trapsize 78
\i (00:03:53) pick grid 3.6791 1.6511
\t (00:03:53) last pick: 3.7000 1.7000
\i (00:03:55) next
\i (00:03:56) zoom out 1
\i (00:03:56) setwindow pcb
\i (00:03:56) zoom out 3.7489 1.6946
\i (00:03:56) trapsize 155
\i (00:03:56) zoom out 1
\i (00:03:56) setwindow pcb
\i (00:03:56) zoom out 3.7489 1.6945
\i (00:03:56) trapsize 310
\i (00:03:56) zoom out 1
\i (00:03:56) setwindow pcb
\i (00:03:56) zoom out 3.7489 1.6946
\i (00:03:56) trapsize 621
\i (00:03:56) zoom in 1
\i (00:03:56) setwindow pcb
\i (00:03:56) zoom in -4.0220 3.6187
\i (00:03:56) trapsize 310
\i (00:03:57) zoom in 1
\i (00:03:57) setwindow pcb
\i (00:03:57) zoom in -4.0219 3.6188
\i (00:03:57) trapsize 155
\i (00:03:57) zoom in 1
\i (00:03:57) setwindow pcb
\i (00:03:57) zoom in -4.0219 3.6187
\i (00:03:57) trapsize 78
\i (00:03:57) pick grid -3.6991 3.3209
\t (00:03:57) last pick: -3.7000 3.3000
\i (00:03:58) zoom out 1
\i (00:03:58) setwindow pcb
\i (00:03:58) zoom out -3.6122 3.6265
\i (00:03:58) trapsize 155
\i (00:03:58) zoom out 1
\i (00:03:58) setwindow pcb
\i (00:03:58) zoom out -3.6123 3.6266
\i (00:03:58) trapsize 310
\i (00:03:58) zoom out 1
\i (00:03:58) setwindow pcb
\i (00:03:58) zoom out -3.6122 3.6266
\i (00:03:58) trapsize 621
\i (00:03:58) zoom out 1
\i (00:03:58) setwindow pcb
\i (00:03:58) zoom out -3.6121 3.6266
\i (00:03:58) trapsize 1241
\i (00:03:59) zoom in 1
\i (00:03:59) setwindow pcb
\i (00:03:59) zoom in -3.4383 1.2184
\i (00:03:59) trapsize 621
\i (00:03:59) zoom in 1
\i (00:03:59) setwindow pcb
\i (00:03:59) zoom in -3.4383 1.2184
\i (00:03:59) trapsize 310
\i (00:03:59) zoom in 1
\i (00:03:59) setwindow pcb
\i (00:03:59) zoom in -3.4383 1.2184
\i (00:03:59) trapsize 155
\i (00:03:59) zoom in 1
\i (00:03:59) setwindow pcb
\i (00:03:59) zoom in -3.4383 1.2184
\i (00:03:59) trapsize 78
\i (00:04:01) pick grid -3.6912 1.6513
\t (00:04:01) last pick: -3.7000 1.7000
\i (00:04:03) next
\i (00:04:03) zoom out 1
\i (00:04:03) setwindow pcb
\i (00:04:03) zoom out -3.2784 1.2370
\i (00:04:03) trapsize 155
\i (00:04:03) zoom out 1
\i (00:04:03) setwindow pcb
\i (00:04:03) zoom out -3.2785 1.2371
\i (00:04:03) trapsize 310
\i (00:04:03) zoom out 1
\i (00:04:03) setwindow pcb
\i (00:04:03) zoom out -3.2784 1.2371
\i (00:04:03) trapsize 621
\i (00:04:11) pick -3.7 -3.3
\t (00:04:11) last pick: -3.7000 -3.3000
\i (00:04:12) zoom out 1
\i (00:04:12) setwindow pcb
\i (00:04:12) zoom out -3.8370 -1.2332
\i (00:04:12) trapsize 1241
\i (00:04:12) zoom out 1
\i (00:04:12) setwindow pcb
\i (00:04:12) zoom out -3.8370 -1.2331
\i (00:04:12) trapsize 2483
\i (00:04:13) zoom in 1
\i (00:04:13) setwindow pcb
\i (00:04:13) zoom in 3.9474 -1.4647
\i (00:04:13) trapsize 1241
\i (00:04:13) zoom in 1
\i (00:04:13) setwindow pcb
\i (00:04:13) zoom in 3.9474 -1.4647
\i (00:04:13) trapsize 621
\i (00:04:13) zoom in 1
\i (00:04:13) setwindow pcb
\i (00:04:13) zoom in 3.9475 -1.4647
\i (00:04:13) trapsize 310
\i (00:04:18) ipick 7.4
\t (00:04:18) last pick: 3.7000 -3.3000
\i (00:04:19) zoom in 1
\i (00:04:19) setwindow pcb
\i (00:04:19) zoom in 3.5937 -1.8371
\i (00:04:19) trapsize 155
\i (00:04:19) zoom in 1
\i (00:04:19) setwindow pcb
\i (00:04:19) zoom in 3.5937 -1.8370
\i (00:04:20) trapsize 78
\i (00:04:20) zoom in 1
\i (00:04:20) setwindow pcb
\i (00:04:20) zoom in 3.5938 -1.8370
\i (00:04:20) trapsize 39
\i (00:04:26) pick grid 3.6504 -1.6888
\t (00:04:26) last pick: 3.7000 -1.7000
\i (00:04:27) next
\i (00:04:28) zoom out 1
\i (00:04:28) setwindow pcb
\i (00:04:28) zoom out 3.8800 -1.7238
\i (00:04:28) trapsize 78
\i (00:04:28) zoom out 1
\i (00:04:28) setwindow pcb
\i (00:04:28) zoom out 3.8801 -1.7237
\i (00:04:28) trapsize 155
\i (00:04:28) zoom out 1
\i (00:04:28) setwindow pcb
\i (00:04:28) zoom out 3.8800 -1.7237
\i (00:04:28) trapsize 310
\i (00:04:29) zoom out 1
\i (00:04:29) setwindow pcb
\i (00:04:29) zoom out 2.9305 -2.1706
\i (00:04:29) trapsize 621
\i (00:04:29) zoom out 1
\i (00:04:29) setwindow pcb
\i (00:04:29) zoom out 2.9305 -2.1706
\i (00:04:29) trapsize 1241
\i (00:04:29) zoom out 1
\i (00:04:29) setwindow pcb
\i (00:04:29) zoom out 2.9306 -2.1706
\i (00:04:29) trapsize 2483
\i (00:04:29) zoom out 1
\i (00:04:29) setwindow pcb
\i (00:04:29) zoom out 11.8421 -0.7696
\i (00:04:29) trapsize 2483
\i (00:04:30) zoom in 1
\i (00:04:30) setwindow pcb
\i (00:04:30) zoom in -4.6425 -1.4151
\i (00:04:30) trapsize 1241
\i (00:04:30) zoom in 1
\i (00:04:30) setwindow pcb
\i (00:04:30) zoom in -4.6425 -1.4151
\i (00:04:30) trapsize 621
\i (00:04:30) zoom in 1
\i (00:04:30) setwindow pcb
\i (00:04:30) zoom in -4.6424 -1.4151
\i (00:04:30) trapsize 310
\i (00:04:30) zoom in 1
\i (00:04:30) setwindow pcb
\i (00:04:30) zoom in -4.6424 -1.4151
\i (00:04:30) trapsize 155
\i (00:04:30) zoom out 1
\i (00:04:30) setwindow pcb
\i (00:04:30) zoom out -3.7859 -2.1350
\i (00:04:30) trapsize 310
\i (00:04:30) zoom out 1
\i (00:04:30) setwindow pcb
\i (00:04:30) zoom out -3.7858 -2.1350
\i (00:04:30) trapsize 621
\i (00:04:30) zoom out 1
\i (00:04:30) setwindow pcb
\i (00:04:30) zoom out -3.7858 -2.1350
\i (00:04:30) trapsize 1241
\i (00:04:31) zoom in 1
\i (00:04:31) setwindow pcb
\i (00:04:31) zoom in -2.6686 -3.7487
\i (00:04:31) trapsize 621
\i (00:04:31) zoom in 1
\i (00:04:31) setwindow pcb
\i (00:04:31) zoom in -2.6686 -3.7487
\i (00:04:31) trapsize 310
\i (00:04:32) pick grid -3.7113 -3.2894
\t (00:04:32) last pick: -3.7000 -3.3000
\i (00:04:33) zoom in 1
\i (00:04:33) setwindow pcb
\i (00:04:33) zoom in -3.6803 -1.7936
\i (00:04:33) trapsize 155
\i (00:04:33) zoom in 1
\i (00:04:33) setwindow pcb
\i (00:04:33) zoom in -3.6802 -1.7936
\i (00:04:33) trapsize 78
\i (00:04:33) zoom in 1
\i (00:04:33) setwindow pcb
\i (00:04:33) zoom in -3.6801 -1.7935
\i (00:04:33) trapsize 39
\i (00:04:35) pick grid -3.6980 -1.6508
\t (00:04:35) last pick: -3.7000 -1.7000
\i (00:04:36) prepopup -3.6080 -1.7028
\i (00:04:37) done
\i (00:04:37) shapeedit
\i (00:04:38) prepopup -3.6507 -1.7478
\i (00:04:38) pick grid -3.4839 -1.6989
\t (00:04:38) last pick: -3.5000 -1.7000
\i (00:04:39) zoom out 1
\i (00:04:39) setwindow pcb
\i (00:04:39) zoom out -3.6639 -1.8424
\i (00:04:39) trapsize 78
\i (00:04:39) zoom out 1
\i (00:04:39) setwindow pcb
\i (00:04:39) zoom out -3.6638 -1.8424
\i (00:04:39) trapsize 155
\i (00:04:39) zoom out 1
\i (00:04:39) setwindow pcb
\i (00:04:39) zoom out -3.6638 -1.8424
\i (00:04:39) trapsize 310
\i (00:04:39) zoom out 1
\i (00:04:39) setwindow pcb
\i (00:04:39) zoom out -3.6825 -2.5003
\i (00:04:39) trapsize 621
\i (00:04:39) zoom out 1
\i (00:04:39) setwindow pcb
\i (00:04:39) zoom out -3.6825 -2.5004
\i (00:04:39) trapsize 1241
\i (00:04:40) zoom in 1
\i (00:04:40) setwindow pcb
\i (00:04:40) zoom in 1.4316 0.6276
\i (00:04:40) trapsize 621
\i (00:04:41) pick grid 0.0166 -0.3157
\t (00:04:41) last pick: 0.0000 -0.3000
\i (00:06:08) add rect
\i (00:06:16) setwindow form.mini
\i (00:06:16) FORM mini subclass ASSEMBLY_TOP
\i (00:06:16) setwindow pcb
\i (00:06:16) updateport CVPane
\i (00:06:18) pick grid -3.6451 3.2591
\t (00:06:18) last pick: -3.6000 3.3000
\i (00:06:19) prepopup 1.9654 -0.8743
\i (00:06:20) oops
\i (00:06:24) zoom in 1
\i (00:06:24) setwindow pcb
\i (00:06:24) zoom in -2.9252 3.0233
\i (00:06:24) trapsize 310
\i (00:06:24) zoom in 1
\i (00:06:24) setwindow pcb
\i (00:06:24) zoom in -2.9252 3.0233
\i (00:06:24) trapsize 155
\i (00:06:25) pick grid -3.7786 3.3988
\t (00:06:25) last pick: -3.8000 3.4000
\i (00:06:26) zoom out 1
\i (00:06:26) setwindow pcb
\i (00:06:26) zoom out -3.3534 2.9209
\i (00:06:26) trapsize 310
\i (00:06:26) zoom out 1
\i (00:06:26) setwindow pcb
\i (00:06:26) zoom out -3.3535 2.9210
\i (00:06:26) trapsize 621
\i (00:06:28) zoom in 1
\i (00:06:28) setwindow pcb
\i (00:06:28) zoom in 3.8459 -3.3599
\i (00:06:28) trapsize 310
\i (00:06:28) zoom in 1
\i (00:06:28) setwindow pcb
\i (00:06:28) zoom in 3.8459 -3.3598
\i (00:06:28) trapsize 155
\i (00:06:29) pick grid 3.8459 -3.3598
\t (00:06:29) last pick: 3.8000 -3.4000
\i (00:06:30) prepopup 4.0631 -2.7578
\i (00:06:30) done
\i (00:06:30) shapeedit
\i (00:06:38) shape add rect
\i (00:06:58) setwindow form.mini
\i (00:06:58) FORM mini subclass PLACE_BOUND_TOP
\i (00:06:58) setwindow pcb
\i (00:06:58) updateport CVPane
\i (00:06:59) zoom out 1
\i (00:06:59) setwindow pcb
\i (00:06:59) zoom out 4.3672 -2.5592
\i (00:06:59) trapsize 310
\i (00:06:59) zoom out 1
\i (00:06:59) setwindow pcb
\i (00:06:59) zoom out 4.3673 -2.5591
\i (00:06:59) trapsize 621
\i (00:06:59) zoom out 1
\i (00:06:59) setwindow pcb
\i (00:06:59) zoom out 4.3673 -2.5591
\i (00:06:59) trapsize 1241
\i (00:07:00) zoom in 1
\i (00:07:00) setwindow pcb
\i (00:07:00) zoom in -4.8430 3.7466
\i (00:07:00) trapsize 621
\i (00:07:00) zoom in 1
\i (00:07:00) setwindow pcb
\i (00:07:00) zoom in -4.8430 3.7466
\i (00:07:00) trapsize 310
\i (00:07:00) zoom in 1
\i (00:07:00) setwindow pcb
\i (00:07:00) zoom in -4.8430 3.7466
\i (00:07:00) trapsize 155
\i (00:07:00) zoom in 1
\i (00:07:00) setwindow pcb
\i (00:07:00) zoom in -4.8429 3.7467
\i (00:07:00) trapsize 78
\i (00:07:00) zoom out 1
\i (00:07:00) setwindow pcb
\i (00:07:00) zoom out -4.6598 3.5776
\i (00:07:00) trapsize 155
\i (00:07:00) zoom out 1
\i (00:07:00) setwindow pcb
\i (00:07:00) zoom out -4.6599 3.5775
\i (00:07:00) trapsize 310
\i (00:07:00) zoom out 1
\i (00:07:00) setwindow pcb
\i (00:07:00) zoom out -4.6598 3.5775
\i (00:07:00) trapsize 621
\i (00:07:01) zoom in 1
\i (00:07:01) setwindow pcb
\i (00:07:01) zoom in -2.5001 2.8204
\i (00:07:01) trapsize 310
\i (00:07:03) pick grid -3.8034 3.3914
\t (00:07:03) last pick: -3.8000 3.4000
\i (00:07:04) zoom out 1
\i (00:07:04) setwindow pcb
\i (00:07:04) zoom out -4.0144 3.1059
\i (00:07:04) trapsize 621
\i (00:07:04) zoom out 1
\i (00:07:04) setwindow pcb
\i (00:07:04) zoom out -4.0144 3.1060
\i (00:07:04) trapsize 1241
\i (00:07:04) zoom out 1
\i (00:07:04) setwindow pcb
\i (00:07:04) zoom out -4.0143 3.1059
\i (00:07:04) trapsize 2483
\i (00:07:05) zoom in 1
\i (00:07:05) setwindow pcb
\i (00:07:05) zoom in 3.8977 -3.6991
\i (00:07:05) trapsize 1241
\i (00:07:05) zoom in 1
\i (00:07:05) setwindow pcb
\i (00:07:05) zoom in 3.8977 -3.6991
\i (00:07:05) trapsize 621
\i (00:07:05) zoom in 1
\i (00:07:05) setwindow pcb
\i (00:07:05) zoom in 3.8977 -3.6991
\i (00:07:05) trapsize 310
\i (00:07:06) pick grid 3.8480 -3.3391
\t (00:07:06) last pick: 3.8000 -3.3000
\i (00:07:06) prepopup 4.5370 -3.5626
\i (00:07:08) done
\i (00:07:08) shapeedit
\i (00:07:08) zoom out 1
\i (00:07:08) setwindow pcb
\i (00:07:08) zoom out 4.9218 -4.4315
\i (00:07:08) trapsize 621
\i (00:07:08) zoom out 1
\i (00:07:08) setwindow pcb
\i (00:07:08) zoom out 4.9218 -4.4314
\i (00:07:08) trapsize 1241
\i (00:07:09) zoom in 1
\i (00:07:09) setwindow pcb
\i (00:07:09) zoom in -0.9868 -0.0124
\i (00:07:09) trapsize 621
\i (00:07:40) label refdes
\t (00:07:40) Pick text location.
\i (00:11:22) label refdes
\t (00:11:22) Pick text location.
\i (00:11:24) pick grid -0.6765 -0.1613
\t (00:11:24) last pick: -0.7000 -0.2000
\t (00:11:24) Enter text string.
\i (00:11:28) setwindow pcb
\i (00:11:28) pick -0.7000 -0.2000
\i (00:11:30) setwindow form.mini
\i (00:11:30) FORM mini subclass SILKSCREEN_TOP
\i (00:11:30) setwindow pcb
\i (00:11:30) updateport CVPane
\i (00:11:31) pick grid -0.8379 4.4191
\t (00:11:31) last pick: -0.8000 4.4000
\t (00:11:31) Enter text string.
\i (00:11:33) setwindow pcb
\i (00:11:33) pick -0.8000 4.4000
\i (00:11:35) move
\t (00:11:35) Select element(s) to move.
\i (00:11:36) pick grid -0.2917 4.6922
\t (00:11:36) last pick: -0.3000 4.7000
\t (00:11:36) Pick user-pick origin.
\i (00:11:37) pick grid -0.6020 4.2577
\t (00:11:37) last pick: -0.6000 4.3000
\t (00:11:37) Pick new location for the element(s).
\i (00:11:40) pick grid -0.5399 0.9558
\t (00:11:40) last pick: -0.5000 1.0000
\i (00:11:42) change
\i (00:11:47) setwindow form.mini
\i (00:11:47) FORM mini change_class 'PACKAGE GEOMETRY'
\i (00:11:51) FORM mini change_class 'REF DES'
\i (00:11:53) FORM mini change_subclass SILKSCREEN_TOP
\i (00:11:58) FORM mini text_name ski
\i (00:11:59) setwindow pcb
\i (00:11:59) pick grid 2.2406 4.3322
\t (00:11:59) last pick: 2.2000 4.3000
\i (00:12:00) pick grid 0.1552 1.4400
\t (00:12:00) last pick: 0.2000 1.4000
\t (00:12:00) No DRC errors detected.
\t (00:12:00) Changed 1 items out of 1 items found.
\i (00:12:00) prepopup 2.4020 3.4881
\i (00:12:02) done
\i (00:12:02) shapeedit
\i (00:12:03) label refdes
\t (00:12:03) Pick text location.
\i (00:12:05) setwindow form.mini
\i (00:12:05) FORM mini class 'BOARD GEOMETRY'
\i (00:12:08) setwindow pcb
\i (00:12:08) pick grid -4.7728 5.3377
\t (00:12:08) last pick: -4.8000 5.3000
\t (00:12:08) Enter text string.
\i (00:12:22) setwindow pcb
\i (00:12:22) pick -4.8000 5.3000
\t (00:12:22) Enter text string.
\i (00:12:24) pick grid -4.7356 3.8605
\t (00:12:24) last pick: -4.7000 3.9000
\t (00:12:24) Enter text string.
\i (00:12:31) setwindow pcb
\i (00:12:31) pick grid 2.6130 4.1088
\t (00:12:31) last pick: 2.6000 4.1000
\i (00:12:31) setwindow pcb
\i (00:12:31) pick -4.7000 3.9000
\t (00:12:31) Enter text string.
\i (00:12:36) setwindow pcb
\i (00:12:36) pick 2.6000 4.1000
\t (00:12:36) Enter text string.
\i (00:12:37) setwindow pcb
\i (00:12:37) move
\t (00:12:37) Select element(s) to move.
\i (00:12:38) pick grid 3.8791 4.3074
\t (00:12:38) last pick: 3.9000 4.3000
\t (00:12:38) Pick user-pick origin.
\i (00:12:39) pick grid 4.4129 3.6991
\t (00:12:39) last pick: 4.4000 3.7000
\t (00:12:39) Pick new location for the element(s).
\i (00:12:40) pick grid 3.7302 3.3516
\t (00:12:40) last pick: 3.7000 3.4000
\i (00:12:41) pick grid 6.2004 1.6262
\t (00:12:41) last pick: 6.2000 1.6000
\i (00:12:41) prepopup 6.2004 1.6262
\i (00:12:42) done
\i (00:12:42) shapeedit
\i (00:12:42) zoom out 1
\i (00:12:42) setwindow pcb
\i (00:12:42) zoom out 0.4283 -1.3902
\i (00:12:42) trapsize 1241
\i (00:12:42) zoom out 1
\i (00:12:42) setwindow pcb
\i (00:12:42) zoom out 0.4283 -1.3903
\i (00:12:42) trapsize 2483
\i (00:12:42) zoom out 1
\i (00:12:42) setwindow pcb
\i (00:12:42) zoom out 5.9335 -6.2314
\i (00:12:42) trapsize 2483
\i (00:12:44) zoom in 1
\i (00:12:44) setwindow pcb
\i (00:12:44) zoom in -1.1668 -0.9682
\i (00:12:44) trapsize 1241
\i (00:12:45) save
\t (00:12:45) Symbol 'i0630.psm' created.
\i (00:12:45) shapeedit
\i (00:12:46) exit
\t (00:12:47) Journal end - Sun Mar 24 00:32:20 2024

14
ind_smd/downrev.log
View File

@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : i0630.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 00:32:19 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
ind_smd/downrev.log,1
View File

@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : i0630.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 00:20:41 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
ind_smd/downrev.log,2
View File

@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : i0630.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 00:32:18 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
ind_smd/downrev.log,3
View File

@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : i0630.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 00:32:18 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

23
ind_smd/i0630.log
View File

@@ -1,23 +0,0 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : i0630.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 00:32:19 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/ind_smd
Name = i0630.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

1
ind_smd/master.tag
View File

@@ -1 +0,0 @@
i0630.dra

56
ind_smd/padstack_editor.jrl
View File

@@ -1,56 +0,0 @@
\t (00:00:02) padstack_editor 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Sun Mar 24 00:16:16 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=1756 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\padstack_editor.exe D:\workspace\GitHub\pcb_lib\ind_smd\l1205.pad
\t (00:00:02)
\d (00:00:16) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:19) QtSignal MainWindow New triggered
\d (00:00:21) QtFillin No
\d (00:00:25) QtSignal fileNewDialog dataCombo CurrentIndexChanged "SMD Pin"
\d (00:00:47) QtSignal fileNewDialog dirPath editingFinished I0630
\d (00:00:47) QtSignal fileNewDialog OK clicked
\d (00:00:50) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:51) QtSignal GuidedDesignLayersTab LayersTable cellClicked 0 "Regular Pad" 0 2
\d (00:00:53) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:53) QtSignal 1
\d (00:01:19) QtFillin OK
\d (00:01:21) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777248 33554432 false +
\d (00:01:21) QtSignal 1
\d (00:01:22) QtSignal GuidedDesignLayersTab PadWidth editingFinished "3.0000"
\d (00:01:23) QtSignal GuidedDesignLayersTab PadHeight editingFinished "1.6000"
\d (00:02:30) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777248 33554432 false +
\d (00:02:30) QtSignal 1
\d (00:02:32) QtSignal GuidedDesignLayersTab PadHeight editingFinished "2.5000"
\d (00:02:34) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:02:35) QtSignal GuidedMaskLayersTab LayersTable cellClicked 0 Pad 0 1
\d (00:02:37) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:02:37) QtSignal 1
\d (00:02:40) QtSignal GuidedMaskLayersTab PadWidth editingFinished "2.5000"
\d (00:02:41) QtSignal GuidedMaskLayersTab PadHeight editingFinished "3.0000"
\d (00:02:45) QtSignal GuidedMaskLayersTab PadWidth editingFinished "2.5500"
\d (00:02:47) QtSignal GuidedMaskLayersTab PadHeight editingFinished "3.0500"
\d (00:02:48) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 Pad
\d (00:02:49) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 Pad 2 1
\d (00:02:50) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:02:50) QtSignal 1
\d (00:02:53) QtSignal GuidedMaskLayersTab PadWidth editingFinished "2.5000"
\d (00:02:54) QtSignal GuidedMaskLayersTab PadHeight editingFinished "3.0000"
\d (00:02:55) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:02:59) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:03:00) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:03:00) QtSignal 1
\d (00:03:01) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777252 0 false 1
\d (00:03:01) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:03:01) QtSignal 1
\d (00:03:03) QtSignal GuidedMaskLayersTab PadWidth editingFinished "3.0000"
\d (00:03:03) QtSignal GuidedMaskLayersTab PadHeight editingFinished "2.5000"
\d (00:03:05) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 0 Pad
\d (00:03:05) QtSignal GuidedMaskLayersTab LayersTable cellClicked 0 Pad 0 1
\d (00:03:06) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:03:06) QtSignal 1
\d (00:03:09) QtSignal GuidedMaskLayersTab PadWidth editingFinished "3.0500"
\d (00:03:13) QtSignal GuidedMaskLayersTab PadHeight editingFinished "2.5500"
\d (00:03:13) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
\d (00:03:15) QtSignal MainWindow Save triggered
\w (00:03:15) WARNING(SPMHUT-48): Scaled value has been rounded off.

61
smc/allegro.jrl
View File

@@ -1,33 +1,28 @@
\t (00:00:05) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:05) Journal start - Sun Mar 24 02:59:48 2024
\t (00:00:05) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=25828 CPUs=12
\t (00:00:05) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\smc\sod-l6-w3.dra
\t (00:00:05)
(00:00:05) Loading axlcore.cxt
\t (00:00:05) Opening existing design...
\i (00:00:05) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sod-l6-w3"
\d (00:00:05) Design opened: D:/workspace/GitHub/pcb_lib/smc/sod-l6-w3.dra
\i (00:00:05) trapsize 1180
\i (00:00:06) trapsize 1212
\i (00:00:06) trapsize 1180
\t (00:00:07) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:07) trapsize 1368
\t (00:00:07) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:07) trapsize 1404
\i (00:00:07) updateport CVPane
\i (00:00:08) shapeedit
\i (00:00:11) step pkg map
\i (00:00:12) fillin yes
\i (00:00:20) setwindow form.pkgmap3d
\i (00:00:20) FORM pkgmap3d overlay YES
\i (00:00:30) FORM pkgmap3d stplist RES_CRCW_2512.step
\i (00:00:31) FORM pkgmap3d stplist SMA-DO-214AC.step
\i (00:00:38) FORM pkgmap3d save_current
\i (00:00:40) FORM pkgmap3d done
\i (00:00:41) setwindow pcb
\i (00:00:41) shapeedit
\i (00:00:41) exit
\e (00:00:41) Do you want to save the changes you made to sod-l6-w3.dra?
\i (00:00:42) fillin yes
\t (00:00:42) Symbol 'sod-l6-w3.psm' created.
\t (00:00:43) Journal end - Sun Mar 24 03:00:26 2024
\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Wed Mar 27 12:20:21 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=23644 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\smc\pdfnwb5x6-8l.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "pdfnwb5x6-8l"
\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/smc/pdfnwb5x6-8l.dra
\t (00:00:02) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:02) trapsize 1512
\i (00:00:02) trapsize 1552
\i (00:00:02) trapsize 1512
\i (00:00:03) trapsize 1326
\i (00:00:03) trapsize 1363
\i (00:00:03) trapsize 1401
\t (00:00:03) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:03) trapsize 1438
\i (00:00:05) step pkg map
\i (00:00:06) fillin yes
\i (00:00:09) setwindow form.pkgmap3d
\i (00:00:09) FORM pkgmap3d done
\i (00:00:10) setwindow pcb
\i (00:00:10) exit
\e (00:00:10) Do you want to save the changes you made to pdfnwb5x6-8l.dra?
\i (00:00:11) fillin yes
\t (00:00:11) Symbol 'pdfnwb5x6-8l.psm' created.
\t (00:00:11) Journal end - Wed Mar 27 12:20:30 2024

60
smc/allegro.jrl,1
View File

@@ -1,31 +1,29 @@
\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:03) Journal start - Sun Mar 24 02:51:39 2024
\t (00:00:03) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=13704 CPUs=12
\t (00:00:03) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\smc\sod-l4_6-w2_2.dra
\t (00:00:03)
(00:00:03) Loading axlcore.cxt
\t (00:00:03) Opening existing design...
\i (00:00:03) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sod-l4_6-w2_2"
\d (00:00:03) Design opened: D:/workspace/GitHub/pcb_lib/smc/sod-l4_6-w2_2.dra
\i (00:00:04) trapsize 257
\i (00:00:04) trapsize 264
\i (00:00:04) trapsize 257
\i (00:00:04) trapsize 298
\i (00:00:05) trapsize 306
\i (00:00:05) updateport CVPane
\i (00:00:05) shapeedit
\i (00:00:11) step pkg map
\i (00:00:12) fillin yes
\i (00:00:15) setwindow form.pkgmap3d
\i (00:00:15) FORM pkgmap3d rotation_z -90
\i (00:00:16) FORM pkgmap3d save_current
\i (00:00:18) FORM pkgmap3d rotation_z 90
\i (00:00:20) FORM pkgmap3d save_current
\i (00:00:21) FORM pkgmap3d done
\i (00:00:21) setwindow pcb
\i (00:00:21) shapeedit
\i (00:00:21) exit
\e (00:00:21) Do you want to save the changes you made to sod-l4_6-w2_2.dra?
\i (00:00:22) fillin yes
\t (00:00:22) Symbol 'sod-l4_6-w2_2.psm' created.
\t (00:00:23) Journal end - Sun Mar 24 02:51:58 2024
\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Wed Mar 27 12:19:12 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=17660 CPUs=12
\t (00:00:02) CmdLine= D:\SOFTWARE\Cadence\SPB_17.4\tools\bin\allegro.exe
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sod-123"
\d (00:00:04) Design opened: D:/workspace/GitHub/pcb_lib/smc/sod-123.dra
\i (00:00:05) trapsize 335
\i (00:00:05) trapsize 344
\i (00:00:05) trapsize 335
\i (00:00:05) trapsize 294
\i (00:00:05) trapsize 302
\i (00:00:05) trapsize 310
\i (00:00:05) trapsize 319
\i (00:00:11) open
\i (00:00:34) fillin "D:/¹¤×÷¿â/Cadence/motor/allegro/motor.brd"
\i (00:00:34) cd "D:/¹¤×÷¿â/Cadence/motor/allegro"
\t (00:00:34) Opening existing design...
\t (00:00:34) Grids are drawn 0.4004, 0.4004 apart for enhanced viewing.
\i (00:00:34) trapsize 3013
\i (00:00:34) trapsize 3087
\t (00:00:34) Grids are drawn 205.0048, 205.0048 apart for enhanced viewing.
\t (00:00:35) Grids are drawn 0.4004, 0.4004 apart for enhanced viewing.
\i (00:00:35) trapsize 3252
\i (00:00:35) trapsize 3252
\t (00:00:35) > Sending response DoneOpenBoard
\t (00:00:35) Journal end - Wed Mar 27 12:19:45 2024

4
smc/downrev.log
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : sod-l6-w3.dra )
( Drawing : pdfnwb5x6-8l.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 03:00:26 2024 )
( Date/Time : Wed Mar 27 12:20:30 2024 )
( )
(---------------------------------------------------------------------)

4
smc/downrev.log,1
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : sod-l4_6-w2_2.dra )
( Drawing : pdfnwb5x6-8l.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:51:58 2024 )
( Date/Time : Wed Mar 27 12:19:01 2024 )
( )
(---------------------------------------------------------------------)

4
smc/downrev.log,2
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : sod-l6-w3.dra )
( Drawing : pdfnwb5x6-8l.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 03:00:25 2024 )
( Date/Time : Wed Mar 27 12:20:30 2024 )
( )
(---------------------------------------------------------------------)

4
smc/downrev.log,3
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : sod-l6-w3.dra )
( Drawing : pdfnwb5x6-8l.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 03:00:25 2024 )
( Date/Time : Wed Mar 27 12:20:30 2024 )
( )
(---------------------------------------------------------------------)

BIN
smc/led3528.dra Normal file
View File

Binary file not shown.

BIN
hold/via_0_25-f.pad → smc/led3528.pad
View File

Binary file not shown.

BIN
smc/led3528.psm Normal file
View File

Binary file not shown.

BIN
smc/ll34.dra Normal file
View File

Binary file not shown.

BIN
smc/ll34.pad Normal file
View File

Binary file not shown.

BIN
smc/ll34.psm Normal file
View File

Binary file not shown.

1
smc/master.tag Normal file
View File

@@ -0,0 +1 @@
sod-123.dra

26
smc/padstack_editor.jrl Normal file
View File

@@ -0,0 +1,26 @@
\t (00:00:02) padstack_editor 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Wed Mar 27 10:55:22 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=27336 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\padstack_editor.exe D:\workspace\GitHub\pcb_lib\smc\sod-123.pad
\t (00:00:02)
\d (00:00:10) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:12) QtSignal GuidedDesignLayersTab LayersTable cellClicked 0 "Regular Pad" 0 2
\d (00:00:18) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:18) QtSignal 1
\d (00:00:24) QtSignal GuidedDesignLayersTab PadWidth editingFinished "0.9100"
\d (00:00:28) QtSignal GuidedDesignLayersTab PadHeight editingFinished "1.2200"
\d (00:00:30) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:31) QtSignal GuidedMaskLayersTab LayersTable cellClicked 0 Pad 0 1
\d (00:00:32) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:32) QtSignal 1
\d (00:00:35) QtSignal GuidedMaskLayersTab PadWidth editingFinished "0.9600"
\d (00:00:40) QtSignal GuidedMaskLayersTab PadHeight editingFinished "1.2700"
\d (00:00:41) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 Pad
\d (00:00:41) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 Pad 2 1
\d (00:00:42) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:42) QtSignal 1
\d (00:00:46) QtSignal GuidedMaskLayersTab PadWidth editingFinished "0.9100"
\d (00:00:47) QtSignal GuidedMaskLayersTab PadHeight editingFinished "1.2200"
\d (00:00:49) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:51) QtSignal MainWindow Save triggered
\t (00:00:53) Journal end - Wed Mar 27 10:56:13 2024

6
ind_smd/param_read.log → smc/param_read.log
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : i0630.dra )
( Drawing : sod-123.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 00:20:41 2024 )
( Date/Time : Wed Mar 27 10:57:42 2024 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : i0630.dra
Layout Name : sod-123.dra
Reading...parameter_header:
Reading...db_common_type:

BIN
smc/pdfnwb5x6-8l-1.dra Normal file
View File

Binary file not shown.

BIN
smc/pdfnwb5x6-8l-1.pad Normal file
View File

Binary file not shown.

BIN
smc/pdfnwb5x6-8l-1.ssm Normal file
View File

Binary file not shown.

BIN
smc/pdfnwb5x6-8l-2.pad Normal file
View File

Binary file not shown.

BIN
smc/pdfnwb5x6-8l.dra Normal file
View File

Binary file not shown.

6
smc/sod-l4_6-w2_2.log → smc/pdfnwb5x6-8l.log
View File

@@ -2,16 +2,16 @@
( )
( CREATE SYMBOL )
( )
( Drawing : sod-l4_6-w2_2.dra )
( Drawing : pdfnwb5x6-8l.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:51:58 2024 )
( Date/Time : Wed Mar 27 12:20:30 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = sod-l4_6-w2_2.psm
Name = pdfnwb5x6-8l.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK

6
smc/sod-l12_4-w6_4.log → smc/pdfnwb5x6-8l.log,1
View File

@@ -2,16 +2,16 @@
( )
( CREATE SYMBOL )
( )
( Drawing : sod-l12_4-w6_4.dra )
( Drawing : pdfnwb5x6-8l.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:47:56 2024 )
( Date/Time : Wed Mar 27 12:19:01 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = sod-l12_4-w6_4.psm
Name = pdfnwb5x6-8l.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK

BIN
smc/pdfnwb5x6-8l.psm Normal file
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Binary file not shown.

BIN
smc/sod-123.dra Normal file
View File

Binary file not shown.

6
smc/sod-l6-w3.log → smc/sod-123.log
View File

@@ -2,16 +2,16 @@
( )
( CREATE SYMBOL )
( )
( Drawing : sod-l6-w3.dra )
( Drawing : sod-123.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 03:00:26 2024 )
( Date/Time : Wed Mar 27 11:04:21 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = sod-l6-w3.psm
Name = sod-123.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK

8
chip/lqfp48.log → smc/sod-123.log,1
View File

@@ -2,16 +2,16 @@
( )
( CREATE SYMBOL )
( )
( Drawing : lqfp48.dra )
( Drawing : sod-123.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:50:25 2024 )
( Date/Time : Wed Mar 27 11:03:51 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = lqfp48.psm
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = sod-123.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK

BIN
smc/sod-123.pad Normal file
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Binary file not shown.

BIN
smc/sod-123.psm Normal file
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BIN
smc/sod-l4_6-w2_2.dra
View File

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BIN
smc/sod-l4_6-w2_2.psm
View File

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2021
smc/stepFacetFiles4Map/STL90N10F7.xml Normal file
View File

File diff suppressed because it is too large Load Diff

35049
smc/stepFacetFiles4Map/ll34.xml Normal file
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2
smc/stepFacetFiles4Map/stepFileInfo.txt
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@@ -5,7 +5,9 @@ SMA-DO-214AC.step ! 213070 ! 1710578258
SMC.step ! 207133 ! 1710578258
TS-POINT.STEP ! 23849 ! 1710578258
SOD-123FL.step ! 331135 ! 1710578258
ll34.step ! 547277 ! 1711502096
LED_0603_G.STEP ! 178570 ! 1710578258
KEY_SOT_P2.step ! 151224 ! 1710578258
RES_CRCW_2512.step ! 33456 ! 1568096060
R0603.step ! 652348 ! 1710578258
STL90N10F7.STEP ! 62745 ! 1711513016

4
smc/stepFacetFiles4Map/stepFileInfo.txt,1
View File

@@ -1,9 +1,13 @@
#STEP_FILE ! FILE_SIZE ! MOD_TIME
C0603.stp ! 74996 ! 1710578258
SMA-DO-214AC.step ! 213070 ! 1710578258
SMC.step ! 207133 ! 1710578258
TS-POINT.STEP ! 23849 ! 1710578258
SOD-123FL.step ! 331135 ! 1710578258
ll34.step ! 547277 ! 1711502096
LED_0603_G.STEP ! 178570 ! 1710578258
KEY_SOT_P2.step ! 151224 ! 1710578258
RES_CRCW_2512.step ! 33456 ! 1568096060
R0603.step ! 652348 ! 1710578258
STL90N10F7.STEP ! 62745 ! 1711513016

BIN
smc/wifi2_4ghz.dra Normal file
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smc/wifi2_4ghz.ssm Normal file
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33
thr/allegro.jrl
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@@ -1,33 +0,0 @@
\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:03) Journal start - Sun Mar 24 02:52:14 2024
\t (00:00:03) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=12348 CPUs=12
\t (00:00:03) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\thr\thr_dip_2x5.dra
\t (00:00:03)
(00:00:03) Loading axlcore.cxt
\t (00:00:03) Opening existing design...
\i (00:00:03) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "thr_dip_2x5"
\d (00:00:03) Design opened: D:/workspace/GitHub/pcb_lib/thr/thr_dip_2x5.dra
\i (00:00:03) trapsize 1100
\i (00:00:04) trapsize 1129
\i (00:00:04) trapsize 1100
\t (00:00:04) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:04) trapsize 1274
\t (00:00:04) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:04) trapsize 1308
\i (00:00:05) updateport CVPane
\i (00:00:05) shapeedit
\i (00:00:12) step pkg map
\i (00:00:13) fillin yes
\i (00:00:16) setwindow form.pkgmap3d
\i (00:00:16) FORM pkgmap3d rotation_z 90
\i (00:00:19) FORM pkgmap3d save_current
\i (00:00:21) FORM pkgmap3d rotation_z 0
\i (00:00:22) FORM pkgmap3d save_current
\i (00:00:24) FORM pkgmap3d done
\i (00:00:24) setwindow pcb
\i (00:00:24) shapeedit
\i (00:00:24) exit
\e (00:00:24) Do you want to save the changes you made to thr_dip_2x5.dra?
\i (00:00:25) fillin yes
\t (00:00:25) Symbol 'thr_dip_2x5.psm' created.
\t (00:00:26) Journal end - Sun Mar 24 02:52:37 2024

38
thr/allegro.jrl,1
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@@ -1,38 +0,0 @@
\t (00:00:04) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:04) Journal start - Sat Mar 23 01:49:19 2024
\t (00:00:04) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=26640 CPUs=12
\t (00:00:04) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\thr\thr_dip_2x5.dra
\t (00:00:04)
(00:00:04) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "thr_dip_2x5"
\d (00:00:04) Design opened: D:/workspace/GitHub/pcb_lib/thr/thr_dip_2x5.dra
\i (00:00:04) trapsize 1071
\i (00:00:05) trapsize 1100
\i (00:00:05) trapsize 1071
\i (00:00:05) trapsize 1241
\t (00:00:05) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:06) trapsize 1274
\i (00:00:06) updateport CVPane
\i (00:00:06) shapeedit
\i (00:00:15) replace padstack
\i (00:00:16) setwindow form.mini
\i (00:00:16) FORM mini oldname_browse
\i (00:00:19) fillin "Thr-1r6_0R9"
\i (00:00:20) FORM mini newname_browse
\t (00:00:33) No valid name selected.
\i (00:00:35) fillin "Thr-1r02_1R8"
\i (00:00:37) FORM mini replace
\t (00:00:37) Done, updated padstack.
\t (00:00:37) 10 out of 10 old padstack THR-1R6_0R9 were replaced with new padstack THR-1R02_1R8.
\i (00:00:39) setwindow pcb
\i (00:00:39) pick grid 0.1418 -7.9086
\t (00:00:39) last pick: 0.1000 -7.9000
\i (00:00:40) save
\t (00:00:40) Performing DRC...
\t (00:00:40) No DRC errors detected.
\i (00:00:41) fillin yes
\t (00:00:42) Symbol 'thr_dip_2x5.psm' created.
\i (00:00:42) shapeedit
\i (00:00:43) exit
\t (00:00:43) Journal end - Sat Mar 23 01:49:59 2024

27
thr/batch_drc.log
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@@ -1,27 +0,0 @@
(---------------------------------------------------------------------)
( )
( DRC Update )
( )
( Drawing : thr_dip_2x5.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 23 01:49:55 2024 )
( )
(---------------------------------------------------------------------)
========= check shapes 0:00:00
========= check standalone pins 0:00:00
========= check symbols (pins,lines,text) 0:00:00
========= check xnets 0:00:00
========= check nets 0:00:00
========= check standalone branches 0:00:00
========= check standalone filled rectangles 0:00:00
========= check standalone lines 0:00:00
========= check standalone text 0:00:00
========= check standalone rectangles 0:00:00
..... Total number of DRC errors 0
..... DRC update completed, total CPU time 0:00:00
*************************************************************************

14
thr/downrev.log
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@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : thr_dip_2x5.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:52:36 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
thr/downrev.log,1
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@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : thr_dip_2x5.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 23 01:49:57 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
thr/downrev.log,2
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@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : thr_dip_2x5.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:52:36 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
thr/downrev.log,3
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@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : thr_dip_2x5.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:52:36 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

1
thr/master.tag
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@@ -1 +0,0 @@
thr_dip_2x5.dra

1
thr/stepFacetFiles4Map/stepFileInfo.txt
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@@ -1,3 +1,4 @@
#STEP_FILE ! FILE_SIZE ! MOD_TIME
thr-3r090tb.step ! 2404583 ! 1711452688
DIP_2x5.step ! 720870 ! 1710578258

3
thr/stepFacetFiles4Map/stepFileInfo.txt,1 Normal file
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@@ -0,0 +1,3 @@
#STEP_FILE ! FILE_SIZE ! MOD_TIME
DIP_2x5.step ! 720870 ! 1710578258

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thr/stepFacetFiles4Map/thr-3r090tb.xml Normal file
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thr/thr-3r090tb.dra Normal file
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thr/thr-3r090tb.psm Normal file
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23
thr/thr_dip_2x5.log
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@@ -1,23 +0,0 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : thr_dip_2x5.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Mar 24 02:52:36 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/thr
Name = thr_dip_2x5.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
thr/thr_dip_2x5.log,1
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@@ -1,23 +0,0 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : thr_dip_2x5.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 23 01:49:57 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/thr
Name = thr_dip_2x5.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.