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XerolySkinner
2024-04-05 22:00:32 +08:00
parent 6cc71db2c5
commit 573ad096d3
46 changed files with 15994 additions and 477 deletions
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smc/allegro.jrl
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\t (00:00:04) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:04) Journal start - Sat Mar 30 19:30:03 2024
\t (00:00:04) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=32852 CPUs=12
\t (00:00:04) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\smc\c0805.dra
\t (00:00:04)
(00:00:04) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged c0805
\d (00:00:04) Design opened: D:/workspace/GitHub/pcb_lib/smc/c0805.dra
\i (00:00:04) trapsize 568
\i (00:00:04) trapsize 583
\i (00:00:05) trapsize 568
\i (00:00:05) trapsize 498
\i (00:00:05) trapsize 512
\i (00:00:06) trapsize 526
\i (00:00:06) trapsize 540
\i (00:00:08) zoom in 1
\i (00:00:08) setwindow pcb
\i (00:00:08) zoom in -0.7485 0.6725
\i (00:00:08) trapsize 270
\i (00:00:08) zoom in 1
\i (00:00:08) setwindow pcb
\i (00:00:08) zoom in -0.7485 0.6725
\i (00:00:08) trapsize 135
\i (00:00:08) zoom in 1
\i (00:00:08) setwindow pcb
\i (00:00:08) zoom in -0.7484 0.6725
\i (00:00:08) trapsize 67
\i (00:00:09) zoom out 1
\i (00:00:09) setwindow pcb
\i (00:00:09) zoom out -0.5905 0.6455
\i (00:00:09) trapsize 135
\i (00:00:09) zoom out 1
\i (00:00:09) setwindow pcb
\i (00:00:09) zoom out -0.5905 0.6456
\i (00:00:09) trapsize 270
\i (00:00:10) zoom in 1
\i (00:00:10) setwindow pcb
\i (00:00:10) zoom in -0.3152 0.3702
\i (00:00:10) trapsize 135
\i (00:00:10) zoom in 1
\i (00:00:10) setwindow pcb
\i (00:00:10) zoom in -0.3151 0.3702
\i (00:00:10) trapsize 67
\i (00:00:10) zoom out 1
\i (00:00:10) setwindow pcb
\i (00:00:10) zoom out -0.3151 0.3702
\i (00:00:10) trapsize 135
\i (00:00:21) delete
\i (00:00:23) move
\t (00:00:23) Select element(s) to move.
\i (00:00:24) pick grid 0.1114 0.7427
\t (00:00:24) last pick: 0.1000 0.7000
\i (00:00:26) pick grid -0.2368 1.0126
\t (00:00:26) last pick: -0.2000 1.0000
\i (00:00:27) pick grid 1.0508 1.1800
\t (00:00:27) last pick: 1.1000 1.2000
\i (00:00:29) color192
\i (00:00:33) QtSignal CVDTabs CVDLayerContainer keyPressEvent 16777248 33554432 false 1
\i (00:00:35) QtSignal CVDLayerContainer CVDFilterLayerEntry editingFinished place
\i (00:00:35) QtSignal CVDLayerContainer CVDVisibilityOn clicked
\i (00:00:36) QtSignal CVDLayerContainer CVDVisibilityOff clicked
\i (00:00:37) QtSignal CVDLayerTable VertHeader clickedCheckBox "Place_Bound_Top" 1
\i (00:00:37) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:38) QtSignal CVDLayerTable VertHeader clickedCheckBox "Place_Bound_Top" 0
\i (00:00:38) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:38) QtSignal CVDLayerTable VertHeader clickedCheckBox "Place_Bound_Top" 1
\i (00:00:38) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:39) QtSignal CVDLayerTable VertHeader clickedCheckBox "Place_Bound_Top" 0
\i (00:00:39) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:40) QtSignal CVDTabs CVDLayerContainer keyPressEvent 16777216 0 false 1 ""
\i (00:00:42) QtSignal CVDLayerContainer CVDVisibilityOn clicked
\i (00:00:43) QtSignal ColorVisibilityDialog CVDOkButton clicked
\i (00:00:44) exit
\e (00:00:45) Do you want to save the changes you made to c0805.dra?
\i (00:00:45) fillin yes
\t (00:00:46) Symbol 'c0805.psm' created.
\t (00:00:46) Journal end - Sat Mar 30 19:30:46 2024

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smc/allegro.jrl,1
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\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Fri Mar 29 14:48:12 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=29424 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\smc\id8.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged id8
\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/smc/id8.dra
\t (00:00:02) Grids are drawn 0.2002, 0.2002 apart for enhanced viewing.
\i (00:00:02) trapsize 1375
\i (00:00:02) trapsize 1412
\i (00:00:02) trapsize 1375
\i (00:00:02) trapsize 1206
\i (00:00:02) trapsize 1239
\i (00:00:02) trapsize 1274
\t (00:00:03) Grids are drawn 0.2002, 0.2002 apart for enhanced viewing.
\i (00:00:03) trapsize 1308
\i (00:00:07) step pkg map
\i (00:00:09) fillin yes
\i (00:00:12) setwindow form.pkgmap3d
\i (00:00:12) FORM pkgmap3d save_current
\i (00:00:14) FORM pkgmap3d done
\i (00:00:15) setwindow pcb
\i (00:00:15) exit
\e (00:00:15) Do you want to save the changes you made to id8.dra?
\i (00:00:16) fillin yes
\t (00:00:16) Symbol 'id8.psm' created.
\t (00:00:16) Journal end - Fri Mar 29 14:48:27 2024

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smc/c0805.log
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(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : c0805.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 30 19:30:45 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = c0805.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

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smc/downrev.log
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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : c0805.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 30 19:30:45 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

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smc/downrev.log,1
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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : id8.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Mar 29 14:48:27 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : c0805.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 30 19:30:45 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : c0805.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 30 19:30:45 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

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smc/id8.log
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(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : id8.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Mar 29 14:48:27 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = id8.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

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