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This commit is contained in:
XerolySkinner
2024-04-05 22:00:32 +08:00
parent 6cc71db2c5
commit 573ad096d3
46 changed files with 15994 additions and 477 deletions
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basic_lib/basic_obj.opj
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@@ -27,20 +27,11 @@
(GlobalState
(FileView
(Path "Design Resources")
(Path "Design Resources"
"d:\workspace\github\pcb_lib\basic_lib\basic_obj.olb")
(Select "Design Resources"
"d:\workspace\github\pcb_lib\basic_lib\basic_obj.olb"))
(Path "Design Resources" ".\basic_obj.olb")
(Select "Design Resources" ".\basic_obj.olb" "XML-DEBUG"))
(HierarchyView)
(Doc
(Type "COrCapturePMDoc")
(Frame
(Placement "44 0 1 -1 -1 -1 -1 0 200 0 533"))
(Tab 0))
(Doc
(Type "COrPrmBrowserDoc")
(Frame
(Placement "44 0 1 -1 -1 -8 -31 5 1099 28 555"))
(Path "D:\WORKSPACE\GITHUB\PCB_LIB\BASIC_LIB\BASIC_OBJ.OLB")
(Package "INA240A1")
(PartType "1"))))
(Placement "44 0 1 -1 -1 -1 -1 0 289 0 644"))
(Tab 0))))

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ind_smd/allegro.jrl
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@@ -1,49 +0,0 @@
\t (00:00:04) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:04) Journal start - Sat Mar 30 19:30:59 2024
\t (00:00:04) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=29116 CPUs=12
\t (00:00:04) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\ind_smd\i0630.dra
\t (00:00:04)
(00:00:04) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged i0630
\d (00:00:04) Design opened: D:/workspace/GitHub/pcb_lib/ind_smd/i0630.dra
\i (00:00:05) trapsize 1071
\i (00:00:05) trapsize 1100
\i (00:00:05) trapsize 1071
\i (00:00:06) trapsize 940
\i (00:00:06) trapsize 965
\i (00:00:06) trapsize 993
\t (00:00:06) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:06) trapsize 1274
\i (00:00:07) zoom in 1
\i (00:00:07) setwindow pcb
\i (00:00:07) zoom in -0.8265 1.7713
\i (00:00:07) trapsize 637
\i (00:00:07) zoom in 1
\i (00:00:07) setwindow pcb
\i (00:00:07) zoom in -0.8265 1.7713
\i (00:00:07) trapsize 319
\i (00:00:07) zoom in 1
\i (00:00:07) setwindow pcb
\i (00:00:07) zoom in -0.8265 1.7713
\i (00:00:07) trapsize 159
\i (00:00:08) zoom out 1
\i (00:00:08) setwindow pcb
\i (00:00:08) zoom out -0.6194 1.6598
\i (00:00:08) trapsize 319
\i (00:00:08) zoom out 1
\i (00:00:08) setwindow pcb
\i (00:00:08) zoom out -0.6195 1.6598
\i (00:00:08) trapsize 637
\i (00:00:09) color192
\i (00:00:14) QtSignal CVDLayerContainer CVDFilterLayerEntry editingFinished place
\i (00:00:14) QtSignal CVDLayerContainer CVDVisibilityOff clicked
\i (00:00:15) QtSignal CVDLayerTable VertHeader clickedCheckBox "Place_Bound_Top" 1
\i (00:00:15) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:18) QtSignal CVDLayerContainer CVDVisibilityOn clicked
\i (00:00:19) QtSignal ColorVisibilityDialog CVDOkButton clicked
\i (00:00:20) exit
\e (00:00:20) Do you want to save the changes you made to i0630.dra?
\i (00:00:20) fillin yes
\t (00:00:21) Symbol 'i0630.psm' created.
\t (00:00:21) Journal end - Sat Mar 30 19:31:16 2024

31
ind_smd/allegro.jrl,1
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@@ -1,31 +0,0 @@
\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:03) Journal start - Sat Mar 30 19:29:45 2024
\t (00:00:03) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=33704 CPUs=12
\t (00:00:03) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\ind_smd\i0630.dra
\t (00:00:03)
(00:00:03) Loading axlcore.cxt
\t (00:00:03) Opening existing design...
\i (00:00:03) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged i0630
\d (00:00:03) Design opened: D:/workspace/GitHub/pcb_lib/ind_smd/i0630.dra
\i (00:00:04) trapsize 1071
\i (00:00:04) trapsize 1100
\i (00:00:04) trapsize 1071
\i (00:00:04) trapsize 940
\i (00:00:04) trapsize 965
\i (00:00:04) trapsize 993
\t (00:00:04) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:05) trapsize 1274
\i (00:00:07) zoom in 1
\i (00:00:07) setwindow pcb
\i (00:00:07) zoom in -0.3423 0.9303
\i (00:00:07) trapsize 637
\i (00:00:07) zoom in 1
\i (00:00:07) setwindow pcb
\i (00:00:07) zoom in -0.3423 0.9303
\i (00:00:07) trapsize 319
\i (00:00:07) zoom in 1
\i (00:00:07) setwindow pcb
\i (00:00:07) zoom in -0.3422 0.9303
\i (00:00:07) trapsize 159
\i (00:00:09) exit
\t (00:00:09) Journal end - Sat Mar 30 19:29:51 2024

14
ind_smd/downrev.log
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@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : i0630.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 30 19:31:16 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
ind_smd/downrev.log,1
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@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : i0630.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 30 19:31:15 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
ind_smd/downrev.log,2
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@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : i0630.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 30 19:31:15 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

23
ind_smd/i0630.log
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@@ -1,23 +0,0 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : i0630.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 30 19:31:16 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/ind_smd
Name = i0630.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
smc/3710fxxx037xxfx01-hold0_9.pad Normal file
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smc/3710fxxx037xxfx01-hold1_3.pad Normal file
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smc/allegro.jrl
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@@ -1,78 +0,0 @@
\t (00:00:04) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:04) Journal start - Sat Mar 30 19:30:03 2024
\t (00:00:04) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=32852 CPUs=12
\t (00:00:04) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\smc\c0805.dra
\t (00:00:04)
(00:00:04) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged c0805
\d (00:00:04) Design opened: D:/workspace/GitHub/pcb_lib/smc/c0805.dra
\i (00:00:04) trapsize 568
\i (00:00:04) trapsize 583
\i (00:00:05) trapsize 568
\i (00:00:05) trapsize 498
\i (00:00:05) trapsize 512
\i (00:00:06) trapsize 526
\i (00:00:06) trapsize 540
\i (00:00:08) zoom in 1
\i (00:00:08) setwindow pcb
\i (00:00:08) zoom in -0.7485 0.6725
\i (00:00:08) trapsize 270
\i (00:00:08) zoom in 1
\i (00:00:08) setwindow pcb
\i (00:00:08) zoom in -0.7485 0.6725
\i (00:00:08) trapsize 135
\i (00:00:08) zoom in 1
\i (00:00:08) setwindow pcb
\i (00:00:08) zoom in -0.7484 0.6725
\i (00:00:08) trapsize 67
\i (00:00:09) zoom out 1
\i (00:00:09) setwindow pcb
\i (00:00:09) zoom out -0.5905 0.6455
\i (00:00:09) trapsize 135
\i (00:00:09) zoom out 1
\i (00:00:09) setwindow pcb
\i (00:00:09) zoom out -0.5905 0.6456
\i (00:00:09) trapsize 270
\i (00:00:10) zoom in 1
\i (00:00:10) setwindow pcb
\i (00:00:10) zoom in -0.3152 0.3702
\i (00:00:10) trapsize 135
\i (00:00:10) zoom in 1
\i (00:00:10) setwindow pcb
\i (00:00:10) zoom in -0.3151 0.3702
\i (00:00:10) trapsize 67
\i (00:00:10) zoom out 1
\i (00:00:10) setwindow pcb
\i (00:00:10) zoom out -0.3151 0.3702
\i (00:00:10) trapsize 135
\i (00:00:21) delete
\i (00:00:23) move
\t (00:00:23) Select element(s) to move.
\i (00:00:24) pick grid 0.1114 0.7427
\t (00:00:24) last pick: 0.1000 0.7000
\i (00:00:26) pick grid -0.2368 1.0126
\t (00:00:26) last pick: -0.2000 1.0000
\i (00:00:27) pick grid 1.0508 1.1800
\t (00:00:27) last pick: 1.1000 1.2000
\i (00:00:29) color192
\i (00:00:33) QtSignal CVDTabs CVDLayerContainer keyPressEvent 16777248 33554432 false 1
\i (00:00:35) QtSignal CVDLayerContainer CVDFilterLayerEntry editingFinished place
\i (00:00:35) QtSignal CVDLayerContainer CVDVisibilityOn clicked
\i (00:00:36) QtSignal CVDLayerContainer CVDVisibilityOff clicked
\i (00:00:37) QtSignal CVDLayerTable VertHeader clickedCheckBox "Place_Bound_Top" 1
\i (00:00:37) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:38) QtSignal CVDLayerTable VertHeader clickedCheckBox "Place_Bound_Top" 0
\i (00:00:38) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:38) QtSignal CVDLayerTable VertHeader clickedCheckBox "Place_Bound_Top" 1
\i (00:00:38) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:39) QtSignal CVDLayerTable VertHeader clickedCheckBox "Place_Bound_Top" 0
\i (00:00:39) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:40) QtSignal CVDTabs CVDLayerContainer keyPressEvent 16777216 0 false 1 ""
\i (00:00:42) QtSignal CVDLayerContainer CVDVisibilityOn clicked
\i (00:00:43) QtSignal ColorVisibilityDialog CVDOkButton clicked
\i (00:00:44) exit
\e (00:00:45) Do you want to save the changes you made to c0805.dra?
\i (00:00:45) fillin yes
\t (00:00:46) Symbol 'c0805.psm' created.
\t (00:00:46) Journal end - Sat Mar 30 19:30:46 2024

29
smc/allegro.jrl,1
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@@ -1,29 +0,0 @@
\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Fri Mar 29 14:48:12 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=29424 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\smc\id8.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged id8
\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/smc/id8.dra
\t (00:00:02) Grids are drawn 0.2002, 0.2002 apart for enhanced viewing.
\i (00:00:02) trapsize 1375
\i (00:00:02) trapsize 1412
\i (00:00:02) trapsize 1375
\i (00:00:02) trapsize 1206
\i (00:00:02) trapsize 1239
\i (00:00:02) trapsize 1274
\t (00:00:03) Grids are drawn 0.2002, 0.2002 apart for enhanced viewing.
\i (00:00:03) trapsize 1308
\i (00:00:07) step pkg map
\i (00:00:09) fillin yes
\i (00:00:12) setwindow form.pkgmap3d
\i (00:00:12) FORM pkgmap3d save_current
\i (00:00:14) FORM pkgmap3d done
\i (00:00:15) setwindow pcb
\i (00:00:15) exit
\e (00:00:15) Do you want to save the changes you made to id8.dra?
\i (00:00:16) fillin yes
\t (00:00:16) Symbol 'id8.psm' created.
\t (00:00:16) Journal end - Fri Mar 29 14:48:27 2024

23
smc/c0805.log
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@@ -1,23 +0,0 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : c0805.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 30 19:30:45 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = c0805.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

14
smc/downrev.log
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@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : c0805.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 30 19:30:45 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
smc/downrev.log,1
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@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : id8.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Mar 29 14:48:27 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
smc/downrev.log,2
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@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : c0805.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 30 19:30:45 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
smc/downrev.log,3
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@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : c0805.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 30 19:30:45 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

23
smc/id8.log
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@@ -1,23 +0,0 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : id8.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Mar 29 14:48:27 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = id8.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

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44
thr/allegro.jrl
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@@ -1,44 +0,0 @@
\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Fri Mar 29 16:03:03 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=3376 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\thr\thr_conn-th-2x5p.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "thr_conn-th-2x5p"
\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/thr/thr_conn-th-2x5p.dra
\t (00:00:02) Grids are drawn 0.2002, 0.2002 apart for enhanced viewing.
\i (00:00:02) trapsize 1375
\i (00:00:02) trapsize 1412
\i (00:00:03) trapsize 1375
\i (00:00:03) trapsize 1206
\i (00:00:03) trapsize 1239
\i (00:00:03) trapsize 1274
\t (00:00:03) Grids are drawn 0.2002, 0.2002 apart for enhanced viewing.
\i (00:00:03) trapsize 1308
\i (00:00:23) step pkg map
\i (00:00:24) fillin yes
\i (00:00:38) setwindow form.pkgmap3d
\i (00:00:38) FORM pkgmap3d stplist thr_conn-th-2x5p.STEP
\i (00:00:39) FORM pkgmap3d overlay YES
\i (00:00:42) FORM pkgmap3d rotation_x 90
\i (00:00:45) FORM pkgmap3d view_orientation Back
\i (00:00:48) FORM pkgmap3d view_orientation Top
\i (00:00:51) FORM pkgmap3d view_orientation Bottom
\i (00:00:52) FORM pkgmap3d hide_board YES
\i (00:00:56) FORM pkgmap3d offset_y -1
\i (00:00:58) FORM pkgmap3d offset_y -2
\i (00:01:01) FORM pkgmap3d offset_y 1
\i (00:01:02) FORM pkgmap3d offset_y 2
\i (00:01:04) FORM pkgmap3d offset_y 0
\i (00:01:08) FORM pkgmap3d offset_y 0.5
\i (00:01:13) FORM pkgmap3d view_orientation Top
\i (00:01:17) FORM pkgmap3d view_orientation 'Front Left'
\i (00:01:20) FORM pkgmap3d save_current
\i (00:01:21) FORM pkgmap3d done
\i (00:01:24) setwindow pcb
\i (00:01:24) save
\i (00:01:25) fillin yes
\t (00:01:25) Symbol 'thr_conn-th-2x5p.psm' created.
\i (00:01:26) exit
\t (00:01:27) Journal end - Fri Mar 29 16:04:28 2024

14
thr/downrev.log
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@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : thr_conn-th-2x5p.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Mar 29 16:04:27 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
thr/downrev.log,1
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@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : thr_conn-th-2x5p.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Mar 29 16:04:26 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
thr/downrev.log,2
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@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : thr_conn-th-2x5p.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Mar 29 16:04:26 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

1
thr/master.tag
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@@ -1 +0,0 @@
thr_conn-th-2x5p.dra

12558
thr/stepFacetFiles4Map/CONN-2P.xml Normal file
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1
thr/stepFacetFiles4Map/stepFileInfo.txt
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@@ -2,6 +2,7 @@
EPS01S.step ! 2352785 ! 1711681659
CONN-4P-P5.STEP ! 1114691 ! 1711644010
CONN-2P.STEP ! 247778 ! 1711988735
thr-3r090tb.step ! 2404583 ! 1711452688
DIP_2x5.step ! 720870 ! 1710578258
CONN-2P-P5.step ! 1193777 ! 1710578258

1
thr/stepFacetFiles4Map/stepFileInfo.txt,1
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@@ -5,5 +5,6 @@ CONN-4P-P5.STEP ! 1114691 ! 1711644010
thr-3r090tb.step ! 2404583 ! 1711452688
DIP_2x5.step ! 720870 ! 1710578258
CONN-2P-P5.step ! 1193777 ! 1710578258
thr_conn-th-2x5p.STEP ! 642474 ! 1711699369
thr_dip_1x4.step ! 336882 ! 1711691285
CONN-8P-P5.STEP ! 1116390 ! 1711644114

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23
thr/thr_conn-th-2x5p.log
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@@ -1,23 +0,0 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : thr_conn-th-2x5p.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Mar 29 16:04:27 2024 )
( )
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Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/thr
Name = thr_conn-th-2x5p.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.