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XerolySkinner
2024-04-17 11:37:48 +08:00
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commit 70f78434d9
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\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Mon Apr 15 22:50:21 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=2828 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\thr\thr_conn-th-2p-p5.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "thr_conn-th-2p-p5"
\d (00:00:04) Design opened: D:/workspace/GitHub/pcb_lib/thr/thr_conn-th-2p-p5.dra
\i (00:00:05) trapsize 227
\i (00:00:05) trapsize 233
\i (00:00:05) trapsize 227
\i (00:00:05) trapsize 199
\i (00:00:05) trapsize 204
\i (00:00:05) trapsize 210
\i (00:00:05) trapsize 216
\i (00:00:05) exit
\t (00:00:06) Journal end - Mon Apr 15 22:50:26 2024