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This commit is contained in:
XerolySkinner
2024-04-12 20:23:24 +08:00
parent 0570548c91
commit 8a6edd498d
79 changed files with 224075 additions and 83332 deletions
Download Patch File Download Diff File Expand all files Collapse all files

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3D/CONN-8P-P5.STEP
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other/stepFacetFiles4Map/stepFileInfo.txt
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@@ -2,7 +2,10 @@
TYPE-C.stp ! 1362496 ! 1710578258 TYPE-C.stp ! 1362496 ! 1710578258
rtl8189-board.STEP ! 1900144 ! 1712473643 rtl8189-board.STEP ! 1900144 ! 1712473643
EC11.STEP ! 1541194 ! 1712715932
rj45-8p8c.step ! 2080205 ! 1712409758 rj45-8p8c.step ! 2080205 ! 1712409758
fpc0_5-40p.stp ! 9221743 ! 1584132940 fpc0_5-40p.stp ! 9221743 ! 1584132940
fpc0_5-6p.stp ! 1966209 ! 1584132963 fpc0_5-6p.stp ! 1966209 ! 1584132963
fpc0_5-50p.stp ! 11408226 ! 1584132947 fpc0_5-50p.stp ! 11408226 ! 1584132947
wh-gm5.STEP ! 888098 ! 1712839932
oled-0_96.step ! 601137 ! 1712757601

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other/stepFacetFiles4Map/stepFileInfo.txt,1
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@@ -1,7 +1,11 @@
#STEP_FILE ! FILE_SIZE ! MOD_TIME #STEP_FILE ! FILE_SIZE ! MOD_TIME
TYPE-C.stp ! 1362496 ! 1710578258 TYPE-C.stp ! 1362496 ! 1710578258
EC11.STEP ! 1541194 ! 1712715932
rtl8189-board.STEP ! 1900144 ! 1712473643
rj45-8p8c.step ! 2080205 ! 1712409758 rj45-8p8c.step ! 2080205 ! 1712409758
fpc0_5-40p.stp ! 9221743 ! 1584132940 fpc0_5-40p.stp ! 9221743 ! 1584132940
fpc0_5-6p.stp ! 1966209 ! 1584132963 fpc0_5-6p.stp ! 1966209 ! 1584132963
fpc0_5-50p.stp ! 11408226 ! 1584132947 fpc0_5-50p.stp ! 11408226 ! 1584132947
wh-gm5.STEP ! 838718 ! 1712836646
oled-0_96.step ! 601137 ! 1712757601

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other/stepFacetFiles4Map/wh-gm5.xml Normal file
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other/wh-gm5.dra
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smc/allegro.jrl Normal file
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\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Fri Apr 12 18:47:52 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=10460 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\smc\c1206.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged c1206
\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/smc/c1206.dra
\i (00:00:02) trapsize 181
\i (00:00:02) trapsize 186
\i (00:00:03) trapsize 181
\i (00:00:03) trapsize 159
\i (00:00:03) trapsize 163
\i (00:00:03) trapsize 168
\i (00:00:03) trapsize 172
\i (00:00:15) step pkg map
\i (00:00:16) fillin yes
\i (00:00:29) setwindow form.pkgmap3d
\i (00:00:29) FORM pkgmap3d stplist c1206.stp
\i (00:00:38) FORM pkgmap3d done
\i (00:00:41) setwindow pcb
\i (00:00:41) step pkg map
\i (00:00:43) fillin yes
\i (00:01:09) setwindow form.pkgmap3d
\i (00:01:09) FORM pkgmap3d stplist C0603.stp
\i (00:01:13) FORM pkgmap3d stplist c1206.stp
\i (00:01:23) FORM pkgmap3d view_orientation Right
\i (00:01:27) FORM pkgmap3d offset_z -10
\i (00:01:29) FORM pkgmap3d offset_z -100
\i (00:01:32) FORM pkgmap3d offset_z -50
\i (00:01:34) FORM pkgmap3d offset_z -20
\i (00:01:38) FORM pkgmap3d offset_z -30
\i (00:01:40) FORM pkgmap3d offset_z -40
\i (00:01:44) FORM pkgmap3d view_orientation 'Front Right'
\i (00:01:48) FORM pkgmap3d rotation_x 90
\i (00:02:08) FORM pkgmap3d view_orientation 'Front Left'
\i (00:02:11) FORM pkgmap3d view_orientation Top
\i (00:02:22) FORM pkgmap3d view_orientation Bottom
\i (00:02:24) FORM pkgmap3d view_orientation 'Front Left'
\i (00:02:25) FORM pkgmap3d overlay NO
\i (00:02:26) FORM pkgmap3d hide_board YES
\i (00:02:27) FORM pkgmap3d overlay YES
\i (00:02:29) FORM pkgmap3d view_orientation Top
\i (00:02:31) FORM pkgmap3d view_orientation Bottom
\i (00:02:33) FORM pkgmap3d view_orientation Right
\i (00:02:34) FORM pkgmap3d hide_board NO
\i (00:02:34) FORM pkgmap3d hide_board YES
\i (00:02:35) FORM pkgmap3d save_current
\i (00:02:36) FORM pkgmap3d done
\i (00:02:39) setwindow pcb
\i (00:02:39) step pkg map
\i (00:02:40) fillin yes
\i (00:02:48) setwindow form.pkgmap3d
\i (00:02:48) FORM pkgmap3d hide_board NO
\i (00:02:52) FORM pkgmap3d view_orientation Top
\i (00:02:58) FORM pkgmap3d view_orientation 'Front Right'
\i (00:03:02) FORM pkgmap3d view_orientation Right
\i (00:03:03) FORM pkgmap3d save_current
\i (00:03:04) FORM pkgmap3d done
\i (00:03:06) setwindow pcb
\i (00:03:06) step pkg map
\i (00:03:07) fillin yes
\i (00:03:16) setwindow form.pkgmap3d
\i (00:03:16) FORM pkgmap3d offset_z --11
\w (00:03:16) Illegal value
\i (00:03:20) FORM pkgmap3d offset_z -15
\i (00:03:22) FORM pkgmap3d offset_z -10
\i (00:03:25) FORM pkgmap3d offset_z -11
\i (00:03:28) FORM pkgmap3d offset_z -10.5
\i (00:03:30) FORM pkgmap3d save_current
\i (00:03:31) FORM pkgmap3d done
\i (00:03:31) setwindow pcb
\i (00:03:31) exit
\e (00:03:31) Do you want to save the changes you made to c1206.dra?
\i (00:03:32) fillin yes
\t (00:03:32) Symbol 'c1206.psm' created.
\t (00:03:32) Journal end - Fri Apr 12 18:51:22 2024

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smc/allegro.jrl,1 Normal file
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\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Fri Apr 12 18:40:47 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=21924 CPUs=12
\t (00:00:02) CmdLine= D:\SOFTWARE\Cadence\SPB_17.4\tools\bin\allegro.exe
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "pdfnwb5x6-8l"
\d (00:00:04) Design opened: D:/workspace/GitHub/pcb_lib/smc/pdfnwb5x6-8l.dra
\t (00:00:05) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:05) trapsize 1593
\i (00:00:05) trapsize 1636
\i (00:00:05) trapsize 1593
\i (00:00:05) trapsize 1398
\i (00:00:05) trapsize 1436
\i (00:00:05) trapsize 1476
\t (00:00:05) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:05) trapsize 1515
\i (00:00:14) open
\i (00:00:32) fillin "D:/workspace/Cadence/motor/allegro/motor.brd"
\i (00:00:32) cd "D:/workspace/Cadence/motor/allegro"
\t (00:00:32) Opening existing design...
\t (00:00:32) Grids are drawn 0.3200, 0.3200 apart for enhanced viewing.
\i (00:00:32) trapsize 3981
\t (00:00:33) Grids are drawn 0.6400, 0.6400 apart for enhanced viewing.
\i (00:00:33) trapsize 4079
\t (00:00:33) Grids are drawn 163.8400, 163.8400 apart for enhanced viewing.
\t (00:00:33) Grids are drawn 0.6400, 0.6400 apart for enhanced viewing.
\i (00:00:33) trapsize 4071
\i (00:00:33) setwindow form.mini
\i (00:00:33) FORM mini tree 'Components by refdes'
\i (00:00:33) setwindow pcb
\i (00:00:33) trapsize 4071
\t (00:00:33) > Sending response DoneOpenBoard
\t (00:00:33) Journal end - Fri Apr 12 18:41:19 2024

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(---------------------------------------------------------------------)
( )
( DRC Update )
( )
( Drawing : f1206.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Apr 12 17:55:14 2024 )
( )
(---------------------------------------------------------------------)
========= check shapes 0:00:00
========= check standalone pins 0:00:00
========= check symbols (pins,lines,text) 0:00:00
========= check xnets 0:00:00
========= check nets 0:00:00
========= check standalone branches 0:00:00
========= check standalone filled rectangles 0:00:00
========= check standalone lines 0:00:00
========= check standalone text 0:00:00
========= check standalone rectangles 0:00:00
..... Total number of DRC errors 0
..... DRC update completed, total CPU time 0:00:00
*************************************************************************

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(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : c1206.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Apr 12 18:51:22 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = c1206.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

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smc/c1206.log,1 Normal file
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(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : c1206.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Apr 12 17:56:15 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = c1206.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

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smc/downrev.log Normal file
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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : c1206.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Apr 12 18:51:22 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

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smc/downrev.log,1 Normal file
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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : pdfnwb5x6-8l.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Apr 12 18:02:09 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
smc/downrev.log,2 Normal file
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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : c1206.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Apr 12 18:51:22 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
smc/downrev.log,3 Normal file
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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : c1206.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Apr 12 18:51:22 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

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(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : f1206.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Apr 12 17:55:15 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = f1206.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

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smc/master.tag Normal file
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pdfnwb5x6-8l.dra

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(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : pdfnwb5x6-8l.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Apr 12 18:02:09 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = pdfnwb5x6-8l.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

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2
smc/stepFacetFiles4Map/stepFileInfo.txt
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@@ -11,6 +11,7 @@ SMC.step ! 207133 ! 1710578258
TS-POINT.STEP ! 23849 ! 1710578258 TS-POINT.STEP ! 23849 ! 1710578258
SOD-123FL.step ! 331135 ! 1710578258 SOD-123FL.step ! 331135 ! 1710578258
ll34.step ! 547277 ! 1711502096 ll34.step ! 547277 ! 1711502096
F1206.step ! 87372 ! 1712834850
sot-23-6p.step ! 308752 ! 1712410134 sot-23-6p.step ! 308752 ! 1712410134
zdyz_imx6ull_core.STEP ! 892431 ! 1712414488 zdyz_imx6ull_core.STEP ! 892431 ! 1712414488
M3x8.step ! 519917 ! 1710578258 M3x8.step ! 519917 ! 1710578258
@@ -24,3 +25,4 @@ f0603.step ! 196072 ! 1712591701
R0603.step ! 652348 ! 1710578258 R0603.step ! 652348 ! 1710578258
STL90N10F7.STEP ! 62745 ! 1711513016 STL90N10F7.STEP ! 62745 ! 1711513016
C0805.stp ! 348325 ! 1600360029 C0805.stp ! 348325 ! 1600360029
c1206.stp ! 348212 ! 1600360320

3
smc/stepFacetFiles4Map/stepFileInfo.txt,1
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@@ -11,6 +11,7 @@ SMC.step ! 207133 ! 1710578258
TS-POINT.STEP ! 23849 ! 1710578258 TS-POINT.STEP ! 23849 ! 1710578258
SOD-123FL.step ! 331135 ! 1710578258 SOD-123FL.step ! 331135 ! 1710578258
ll34.step ! 547277 ! 1711502096 ll34.step ! 547277 ! 1711502096
F1206.step ! 87372 ! 1712834850
sot-23-6p.step ! 308752 ! 1712410134 sot-23-6p.step ! 308752 ! 1712410134
zdyz_imx6ull_core.STEP ! 892431 ! 1712414488 zdyz_imx6ull_core.STEP ! 892431 ! 1712414488
M3x8.step ! 519917 ! 1710578258 M3x8.step ! 519917 ! 1710578258
@@ -20,6 +21,8 @@ SOT-23-5P.step ! 185960 ! 1710578258
KEY_SOT_P2.step ! 151224 ! 1710578258 KEY_SOT_P2.step ! 151224 ! 1710578258
RES_CRCW_2512.step ! 33456 ! 1568096060 RES_CRCW_2512.step ! 33456 ! 1568096060
0805.step ! 57849 ! 1568096060 0805.step ! 57849 ! 1568096060
f0603.step ! 196072 ! 1712591701
R0603.step ! 652348 ! 1710578258 R0603.step ! 652348 ! 1710578258
STL90N10F7.STEP ! 62745 ! 1711513016 STL90N10F7.STEP ! 62745 ! 1711513016
C0805.stp ! 348325 ! 1600360029 C0805.stp ! 348325 ! 1600360029
c1206.stp ! 348212 ! 1600360320

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thr/thr_conn-th-2x5p.dra → smc/utdfn-1x1-4l.dra
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thr/stepFacetFiles4Map/stepFileInfo.txt
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@@ -3,9 +3,11 @@
EPS01S.step ! 2352785 ! 1711681659 EPS01S.step ! 2352785 ! 1711681659
CONN-4P-P5.STEP ! 1114691 ! 1711644010 CONN-4P-P5.STEP ! 1114691 ! 1711644010
CONN-2P.STEP ! 539429 ! 1712710914 CONN-2P.STEP ! 539429 ! 1712710914
thr_dip_2x2.STEP ! 85207 ! 1712840371
thr-3r090tb.step ! 2404583 ! 1711452688 thr-3r090tb.step ! 2404583 ! 1711452688
DIP_2x5.step ! 720870 ! 1710578258 DIP_2x5.step ! 720870 ! 1710578258
CONN-2P-P5.step ! 1193777 ! 1710578258 CONN-2P-P5.step ! 1193777 ! 1710578258
thr_conn-th-2x5p.STEP ! 642474 ! 1711699369 thr_conn-th-2x5p.STEP ! 642474 ! 1711699369
thr_dip_2x3.step ! 86870 ! 1712835219
thr_dip_1x4.step ! 336882 ! 1711691285 thr_dip_1x4.step ! 336882 ! 1711691285
CONN-8P-P5.STEP ! 1116390 ! 1711644114 CONN-8P-P5.STEP ! 557855 ! 1712837489

5
thr/stepFacetFiles4Map/stepFileInfo.txt,1
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@@ -2,10 +2,11 @@
EPS01S.step ! 2352785 ! 1711681659 EPS01S.step ! 2352785 ! 1711681659
CONN-4P-P5.STEP ! 1114691 ! 1711644010 CONN-4P-P5.STEP ! 1114691 ! 1711644010
CONN-2P.STEP ! 360048 ! 1712416291 CONN-2P.STEP ! 539429 ! 1712710914
thr-3r090tb.step ! 2404583 ! 1711452688 thr-3r090tb.step ! 2404583 ! 1711452688
DIP_2x5.step ! 720870 ! 1710578258 DIP_2x5.step ! 720870 ! 1710578258
CONN-2P-P5.step ! 1193777 ! 1710578258 CONN-2P-P5.step ! 1193777 ! 1710578258
thr_conn-th-2x5p.STEP ! 642474 ! 1711699369 thr_conn-th-2x5p.STEP ! 642474 ! 1711699369
thr_dip_2x3.step ! 86870 ! 1712835219
thr_dip_1x4.step ! 336882 ! 1711691285 thr_dip_1x4.step ! 336882 ! 1711691285
CONN-8P-P5.STEP ! 1116390 ! 1711644114 CONN-8P-P5.STEP ! 557855 ! 1712837489

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