diff --git a/3D/PC817.STEP b/3D/PC817.STEP
new file mode 100644
index 0000000..949df76
--- /dev/null
+++ b/3D/PC817.STEP
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diff --git a/basic_lib/BASIC_OBJ.OLB b/basic_lib/BASIC_OBJ.OLB
index 66f18eb..865e5fa 100644
Binary files a/basic_lib/BASIC_OBJ.OLB and b/basic_lib/BASIC_OBJ.OLB differ
diff --git a/basic_lib/BASIC_OBJ_0.OBK b/basic_lib/BASIC_OBJ_0.OBK
index ae0197a..f10935c 100644
Binary files a/basic_lib/BASIC_OBJ_0.OBK and b/basic_lib/BASIC_OBJ_0.OBK differ
diff --git a/chip/allegro.jrl b/chip/allegro.jrl
index f78f8d6..1be0980 100644
--- a/chip/allegro.jrl
+++ b/chip/allegro.jrl
@@ -1,45 +1,20 @@
 \t (00:00:02) allegro 23.1 P001 Windows SPB 64-bit Edition
-\t (00:00:02)     Journal start - Fri Apr 25 15:00:50 2025
-\t (00:00:02)         Host=XEROLYSKINNER User=Xeroly Pid=5220 CPUs=16
-\t (00:00:02) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\chip\tqfp-48-ep.dra
+\t (00:00:02)     Journal start - Sat May 10 04:57:54 2025
+\t (00:00:02)         Host=XEROLYSKINNER User=Xeroly Pid=35792 CPUs=16
+\t (00:00:02) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe
 \t (00:00:02) 
    (00:00:02) Loading axlcore.cxt 
-\t (00:00:04) Opening existing design...
-\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "tqfp-48-ep"
-\d (00:00:04) Design opened: D:/Workspace/GitHub/pcb_lib/chip/tqfp-48-ep.dra
-\t (00:00:05) Grids are drawn 0.160, 0.160 apart for enhanced viewing.
-\i (00:00:05) trapsize 102
-\i (00:00:05) trapsize 104
-\i (00:00:05) trapsize 102
-\t (00:00:05) Grids are drawn 0.160, 0.160 apart for enhanced viewing.
-\i (00:00:05) trapsize 108
+\t (00:00:05) Opening existing design...
+\i (00:00:05) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "wsoic-8"
+\d (00:00:05) Design opened: D:/workspace/GitHub/pcb_lib/chip/wsoic-8.dra
 \t (00:00:05) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
-\i (00:00:05) trapsize 74
-\i (00:00:12) add pin 
-\i (00:00:16) setwindow form.mini
-\i (00:00:16) FORM mini pad_name tqfp-48-ep-gnd 
-\w (00:00:16) WARNING(SPMHUT-48): Scaled value has been rounded off.
-\t (00:00:16) Using 'TQFP-48-EP-GND.pad'.
-\e (00:00:20) Command not found: X 0 0
-\i (00:00:22) setwindow pcb
-\i (00:00:22) pick 0 0 
-\t (00:00:22) last pick:  0.000 0.000
-\t (00:00:22) Using 'TQFP-48-EP-GND.pad'.
-\i (00:00:23) prepopup 6.355 6.505
-\i (00:00:27) oops 
-\t (00:00:27) Using 'TQFP-48-EP-GND.pad'.
-\i (00:00:32) setwindow form.mini
-\i (00:00:32) FORM mini text_name pin 
-\i (00:00:34) FORM mini next_pin_number 49 
-\i (00:00:36) setwindow pcb
-\i (00:00:36) pick 0 0 
-\t (00:00:36) last pick:  0.000 0.000
-\t (00:00:36) Using 'TQFP-48-EP-GND.pad'.
-\i (00:00:37) prepopup 7.902 3.812
-\i (00:00:38) done 
-\t (00:00:38) Exiting from Add Pin.
-\i (00:00:39) save 
-\i (00:00:40) fillin yes 
-\t (00:00:40) Symbol 'tqfp-48-ep.psm' created.
-\i (00:00:41) exit 
-\t (00:00:41)     Journal end - Fri Apr 25 15:01:29 2025
+\i (00:00:05) trapsize 71
+\i (00:00:05) trapsize 73
+\i (00:00:06) trapsize 71
+\i (00:00:06) trapsize 76
+\t (00:00:06) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
+\i (00:00:06) trapsize 79
+\i (00:00:06) trapsize 53
+\i (00:00:20) new 
+\i (00:00:37) newdrawfillin "smd_4.dra" "Package Symbol (Wizard)"
+\t (00:00:37)     Journal end - Sat May 10 04:58:28 2025
diff --git a/chip/allegro.jrl,1 b/chip/allegro.jrl,1
index da8fdab..17ebb47 100644
--- a/chip/allegro.jrl,1
+++ b/chip/allegro.jrl,1
@@ -1,838 +1,574 @@
-\t (00:00:56) allegro 23.1 P001 Windows SPB 64-bit Edition
-\t (00:00:56)     Journal start - Thu Apr 24 23:16:25 2025
-\t (00:00:56)         Host=XEROLYSKINNER User=Xeroly Pid=30172 CPUs=16
-\t (00:00:56) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe
-\t (00:00:56) 
-\t (00:00:56) Starting new design...
-\i (00:00:56) trapsize 14970
-\i (00:00:56) trapsize 15291
-\i (00:00:56) trapsize 14970
-\t (00:00:56) Grids are drawn 1300.4800, 1300.4800 apart for enhanced viewing.
-\i (00:00:56) trapsize 21701
-\i (00:00:56) trapsize 21701
-\i (00:00:56) trapsize 21061
-\i (00:00:56) package symbol wizard 
-   (00:00:59) Loading cmds.cxt 
-\i (00:00:59) setwindow form.sym_wizard
-\i (00:00:59) FORM sym_wizard soic YES 
-\i (00:01:00) FORM sym_wizard plcc YES 
-\i (00:01:04) FORM sym_wizard wiz_next  
-\i (00:01:07) FORM sym_wizard load_template  
-\t (00:01:07) Opening existing design...
-\i (00:01:07) setwindow pcb
-\i (00:01:07) trapsize 121
-\i (00:01:07) trapsize 123
-\i (00:01:07) trapsize 121
-\t (00:01:08) Grids are drawn 200, 200 apart for enhanced viewing.
-\i (00:01:08) trapsize 148
-\d (00:01:08) Design opened: D:/software/Cadence/SPB_23.1/share/pcb/pcb_lib/symbols/template/sym_template.dra
-\i (00:01:08) trapsize 143
-\i (00:01:09) setwindow form.sym_wizard
-\i (00:01:09) FORM sym_wizard wiz_next  
-\i (00:01:13) FORM sym_wizard pack_units Millimeter 
-\i (00:01:16) FORM sym_wizard pack_units_create Millimeter 
-\i (00:01:18) FORM sym_wizard wiz_next  
-\i (00:01:27) FORM sym_wizard qfp_pin_count_v 12 
-\i (00:01:28) FORM sym_wizard qfp_pin_count_h 12 
-\i (00:01:35) FORM sym_wizard qfp_pin1_corner YES 
-\i (00:03:56) FORM sym_wizard qfp_e 0.500 
-\i (00:03:58) FORM sym_wizard wiz_next  
-\i (00:04:44) FORM sym_wizard qfp_e1 8.800 
-\i (00:04:45) FORM sym_wizard qfp_e2 8.800 
-\i (00:05:00) FORM sym_wizard qfp_width 7.000 
-\i (00:05:01) FORM sym_wizard qfp_len 7.000 
-\i (00:05:03) FORM sym_wizard wiz_next  
-\i (00:05:06) FORM sym_wizard default_pad_browse  
-\i (00:05:18) fillin "Tqfp-48-ep"
-\i (00:05:20) FORM sym_wizard wiz_next  
-\i (00:05:24) FORM sym_wizard wiz_next  
-\i (00:05:26) FORM sym_wizard wiz_finish  
-\w (00:05:26) WARNING(SPMHUT-48): Scaled value has been rounded off.
-\t (00:05:26) Grids are drawn 5.080, 5.080 apart for enhanced viewing.
+\t (00:00:28) allegro 23.1 P001 Windows SPB 64-bit Edition
+\t (00:00:28)     Journal start - Sat May 10 04:29:09 2025
+\t (00:00:28)         Host=XEROLYSKINNER User=Xeroly Pid=39640 CPUs=16
+\t (00:00:28) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe
+\t (00:00:28) 
+\t (00:00:28) Starting new design...
+\i (00:00:28) trapsize 14970
+\i (00:00:28) trapsize 15291
+\i (00:00:28) trapsize 14970
+\t (00:00:28) Grids are drawn 1300.4800, 1300.4800 apart for enhanced viewing.
+\i (00:00:28) trapsize 19763
+\i (00:00:28) trapsize 19763
+\i (00:00:28) trapsize 18903
+\i (00:00:28) package symbol wizard 
+   (00:00:31) Loading cmds.cxt 
+\i (00:00:31) setwindow form.sym_wizard
+\i (00:00:31) FORM sym_wizard soic YES 
+\i (00:00:32) FORM sym_wizard wiz_next  
+\i (00:00:34) FORM sym_wizard load_template  
+\t (00:00:34) Opening existing design...
+\t (00:00:34) Grids are drawn 200, 200 apart for enhanced viewing.
+\i (00:00:34) setwindow pcb
+\i (00:00:34) trapsize 126
+\i (00:00:34) trapsize 129
+\i (00:00:34) trapsize 126
+\t (00:00:34) Grids are drawn 200, 200 apart for enhanced viewing.
+\i (00:00:34) trapsize 148
+\d (00:00:34) Design opened: D:/software/Cadence/SPB_23.1/share/pcb/pcb_lib/symbols/template/sym_template.dra
+\i (00:00:34) trapsize 143
+\i (00:00:35) setwindow form.sym_wizard
+\i (00:00:35) FORM sym_wizard wiz_next  
+\i (00:00:43) FORM sym_wizard pack_units Millimeter 
+\i (00:00:45) FORM sym_wizard pack_units_create Millimeter 
+\i (00:00:47) FORM sym_wizard wiz_next  
+\i (00:00:50) FORM sym_wizard sop_pin_count 13 
+\i (00:00:51) FORM sym_wizard sop_pin_count 12 
+\i (00:00:51) FORM sym_wizard sop_pin_count 11 
+\i (00:00:51) FORM sym_wizard sop_pin_count 10 
+\i (00:00:51) FORM sym_wizard sop_pin_count 9 
+\i (00:00:51) FORM sym_wizard sop_pin_count 8 
+\i (00:00:52) FORM sym_wizard sop_pin_count 7 
+\i (00:00:52) FORM sym_wizard sop_pin_count 8 
+\i (00:02:27) FORM sym_wizard sop_e1 7.250 
+\i (00:02:39) FORM sym_wizard sop_width 5.280 
+\i (00:02:56) FORM sym_wizard sop_len 5.280 
+\i (00:03:14) FORM sym_wizard wiz_next  
+\i (00:03:19) FORM sym_wizard default_padstack wsoic-8 
+\i (00:03:20) FORM sym_wizard wiz_next  
+\i (00:03:29) FORM sym_wizard wiz_next  
+\i (00:03:30) FORM sym_wizard wiz_finish  
+\w (00:03:30) WARNING(SPMHUT-48): Scaled value has been rounded off.
+\t (00:03:30) Grids are drawn 5.080, 5.080 apart for enhanced viewing.
+\i (00:03:30) setwindow pcb
+\i (00:03:30) trapsize 3638
+\t (00:03:30) Performing DRC...
+\t (00:03:30) No DRC errors detected.
+\w (00:03:30) WARNING(SPMHUT-48): Scaled value has been rounded off.
+\i (00:03:30) trapsize 3638
+\i (00:03:31) trapsize 64
+\i (00:03:31) trapsize 38
+\i (00:03:31) trapsize 38
+\i (00:03:31) trapsize 38
+\t (00:03:31) Performing DRC...
+\t (00:03:31) No DRC errors detected.
+\t (00:03:31) Creating package symbol 'D:/workspace/GitHub/pcb_lib/chip/wsoic-8.psm'.
+\t (00:03:31) Starting Create symbol...
+\i (00:03:33) zoom out 1 
+\i (00:03:33) setwindow pcb
+\i (00:03:33) zoom out 1.185 -2.439
+\i (00:03:33) trapsize 76
+\i (00:03:33) zoom out 1 
+\i (00:03:33) setwindow pcb
+\i (00:03:33) zoom out 1.184 -3.488
+\i (00:03:33) trapsize 101
+\i (00:03:37) param in 
+\i (00:03:39) setwindow form.parm_in
+\i (00:03:39) FORM parm_in browse  
+\i (00:03:41) fillin "D:/workspace/GitHub/pcb_lib/XerolySkinner.prm"
+\i (00:03:43) FORM parm_in execute  
+\t (00:03:43) Starting Importing parameter file...
+\w (00:03:43) WARNING(SPMHGE-269): param in had warnings, use Viewlog to review the log file.
+\t (00:03:43) Opening existing design...
+\t (00:03:43) Grids are drawn 40.640, 40.640 apart for enhanced viewing.
+\i (00:03:43) setwindow pcb
+\i (00:03:43) trapsize 101
+\i (00:03:45) setwindow text
+\i (00:03:45) close
+\i (00:03:46) setwindow form.parm_in
+\i (00:03:46) FORM parm_in cancel  
+\i (00:03:48) setwindow pcb
+\i (00:03:48) change 
+\i (00:03:49) setwindow form.find
+\i (00:03:49) FORM find all_off  
+\i (00:03:52) FORM find text YES 
+\i (00:03:55) setwindow form.mini
+\i (00:03:55) FORM mini change_class 'PACKAGE GEOMETRY' 
+\i (00:03:57) FORM mini change_subclass PIN_NUMBER 
+\i (00:03:58) setwindow form.find
+\i (00:03:58) FORM find all_off  
+\i (00:04:00) FORM find text YES 
+\i (00:04:00) FORM find all_on  
+\i (00:04:02) FORM find all_off  
+\i (00:04:03) FORM find text YES 
+\i (00:04:06) setwindow form.mini
+\i (00:04:06) FORM mini text_name pin 
+\i (00:04:07) setwindow pcb
+\i (00:04:07) drag_start grid 3.359 3.662
+\i (00:04:08) drag_stop 4.348 -3.219
+\t (00:04:08) No DRC errors detected.
+\t (00:04:08) Changed 4 items out of 4 items found.
+\i (00:04:09) drag_start grid -4.249 3.844
+\i (00:04:10) drag_stop -2.594 -2.675
+\t (00:04:10) No DRC errors detected.
+\t (00:04:10) Changed 4 items out of 4 items found.
+\i (00:04:10) prepopup -2.291 0.897
+\i (00:04:11) done 
+\i (00:04:12) zoom in 1 
+\i (00:04:12) setwindow pcb
+\i (00:04:12) zoom in -0.899 1.402
+\i (00:04:12) trapsize 50
+\i (00:04:19) color192 
+\i (00:04:20) QtSignal CVDLayerContainer CVDVisibilityOff clicked
+\i (00:04:24) QtSignal CVDLayerContainer CVDFilterLayerEntry editingFinished silk
+\i (00:04:24) QtSignal CVDLayerTable VertHeader clickedCheckBox "Silkscreen_Top" 1
+\i (00:04:24) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 1 0
+\i (00:04:26) QtSignal ColorVisibilityDialog CVDOkButton clicked
+\i (00:04:27) delete 
+\i (00:04:30) setwindow form.find
+\i (00:04:30) FORM find all_on  
+\i (00:04:32) setwindow pcb
+\i (00:04:32) pick grid 2.017 2.653
+\t (00:04:32) last pick:  1.905 2.540
+\t (00:04:32) Line "Package Geometry/Silkscreen_Top"
+\i (00:04:33) prepopup 3.379 2.875
+\i (00:04:33) done 
+\i (00:04:34) color192 
+\i (00:04:35) QtSignal CVDLayerContainer CVDVisibilityOn clicked
+\i (00:04:36) QtSignal ColorVisibilityDialog CVDOkButton clicked
+\i (00:04:38) prmed 
+\i (00:04:39) setwindow form.prmedit
+\i (00:04:39) FORM prmedit text  
+\i (00:04:40) FORM prmedit shapes  
+\i (00:04:41) FORM prmedit design  
+\i (00:04:43) FORM prmedit cancel  
+\i (00:04:45) setwindow pcb
+\i (00:04:45) define grid 
+\t (00:04:45) Spacing fields allow simple equations to aid calculations; prefix with =
+\i (00:04:47) setwindow form.grid
+\i (00:04:47) FORM grid non_etch non_etch_x_grids 0.01 
+\i (00:04:48) FORM grid non_etch non_etch_y_grids 0.01 
+\i (00:04:49) FORM grid done  
+\i (00:04:51) setwindow pcb
+\i (00:04:51) define grid 
+\t (00:04:51) Spacing fields allow simple equations to aid calculations; prefix with =
+\i (00:04:53) setwindow form.grid
+\i (00:04:53) FORM grid all_etch all_etch_x_grids 0.01 
+\i (00:04:54) FORM grid all_etch all_etch_y_grids 0.01 
+\i (00:04:54) FORM grid all_etch all_etch_x_offset 0.000 
+\i (00:04:55) FORM grid all_etch all_etch_y_offset 0.000 
+\i (00:04:55) FORM grid top subclass_x_grids 0.010 
+\i (00:04:55) FORM grid top subclass_x_grids 0.010 
+\i (00:04:55) FORM grid done  
+\t (00:04:55) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
+\i (00:04:57) setwindow pcb
+\i (00:04:57) add connect 
+\w (00:04:57) WARNING(SPMHUT-48): Scaled value has been rounded off.
+\w (00:04:57) WARNING(SPMHUT-48): Scaled value has been rounded off.
+\t (00:04:57) Pick first element.
+\i (00:05:03) add line 
+\i (00:05:04) setwindow form.mini
+\i (00:05:04) FORM mini class 'PACKAGE GEOMETRY' 
+\i (00:05:08) FORM mini subclass SILKSCREEN_TOP 
+\i (00:05:08) setwindow pcb
+\i (00:05:08) updateport CVPane
+\i (00:05:10) setwindow form.mini
+\i (00:05:10) FORM mini line_width 0.150 
+\i (00:05:11) setwindow pcb
+\i (00:05:11) zoom in 1 
+\i (00:05:11) setwindow pcb
+\i (00:05:11) zoom in -2.564 2.623
+\t (00:05:11) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
+\i (00:05:11) trapsize 25
+\i (00:05:11) zoom in 1 
+\i (00:05:11) setwindow pcb
+\i (00:05:11) zoom in -2.564 2.623
+\t (00:05:11) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
+\i (00:05:11) trapsize 13
+\i (00:05:11) zoom in 1 
+\i (00:05:11) setwindow pcb
+\i (00:05:11) zoom in -2.563 2.624
+\i (00:05:11) trapsize 6
+\i (00:05:11) zoom in 1 
+\i (00:05:11) setwindow pcb
+\i (00:05:11) zoom in -2.563 2.624
+\i (00:05:11) trapsize 3
+\i (00:05:13) pick grid -2.640 2.650
+\t (00:05:13) last pick:  -2.640 2.650
+\i (00:05:14) zoom out 1 
+\i (00:05:14) setwindow pcb
+\i (00:05:14) zoom out -2.710 2.517
+\i (00:05:14) trapsize 6
+\i (00:05:14) zoom out 1 
+\i (00:05:14) setwindow pcb
+\i (00:05:14) zoom out -2.710 2.518
+\i (00:05:14) trapsize 13
+\i (00:05:14) zoom out 1 
+\i (00:05:14) setwindow pcb
+\i (00:05:14) zoom out -2.710 2.518
+\t (00:05:14) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
+\i (00:05:14) trapsize 25
+\i (00:05:14) zoom out 1 
+\i (00:05:14) setwindow pcb
+\i (00:05:14) zoom out -2.710 2.518
+\t (00:05:14) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
+\i (00:05:14) trapsize 50
+\i (00:05:15) zoom in 1 
+\i (00:05:15) setwindow pcb
+\i (00:05:15) zoom in 2.693 2.851
+\t (00:05:15) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
+\i (00:05:15) trapsize 25
+\i (00:05:16) zoom in 1 
+\i (00:05:16) setwindow pcb
+\i (00:05:16) zoom in 2.618 2.664
+\t (00:05:16) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
+\i (00:05:16) trapsize 13
+\i (00:05:16) zoom in 1 
+\i (00:05:16) setwindow pcb
+\i (00:05:16) zoom in 2.618 2.664
+\i (00:05:16) trapsize 6
+\i (00:05:16) zoom in 1 
+\i (00:05:16) setwindow pcb
+\i (00:05:16) zoom in 2.618 2.665
+\i (00:05:16) trapsize 3
+\i (00:05:19) pick grid 2.638 2.645
+\t (00:05:19) last pick:  2.640 2.650
+\i (00:05:20) zoom out 1 
+\i (00:05:20) setwindow pcb
+\i (00:05:20) zoom out 2.652 2.690
+\i (00:05:20) trapsize 6
+\i (00:05:20) zoom out 1 
+\i (00:05:20) setwindow pcb
+\i (00:05:20) zoom out 2.652 2.690
+\i (00:05:20) trapsize 13
+\i (00:05:20) zoom out 1 
+\i (00:05:20) setwindow pcb
+\i (00:05:20) zoom out 2.653 2.690
+\t (00:05:20) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
+\i (00:05:20) trapsize 25
+\i (00:05:20) zoom out 1 
+\i (00:05:20) setwindow pcb
+\i (00:05:20) zoom out 2.653 2.691
+\t (00:05:20) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
+\i (00:05:20) trapsize 50
+\i (00:05:21) zoom in 1 
+\i (00:05:21) setwindow pcb
+\i (00:05:21) zoom in 2.654 -2.823
+\t (00:05:21) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
+\i (00:05:21) trapsize 25
+\i (00:05:21) zoom in 1 
+\i (00:05:21) setwindow pcb
+\i (00:05:21) zoom in 2.654 -2.823
+\t (00:05:21) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
+\i (00:05:21) trapsize 13
+\i (00:05:21) zoom in 1 
+\i (00:05:21) setwindow pcb
+\i (00:05:21) zoom in 2.654 -2.823
+\i (00:05:21) trapsize 6
+\i (00:05:21) zoom in 1 
+\i (00:05:21) setwindow pcb
+\i (00:05:21) zoom in 2.654 -2.823
+\i (00:05:21) trapsize 3
+\i (00:05:21) zoom in 1 
+\i (00:05:21) setwindow pcb
+\i (00:05:21) zoom in 2.654 -2.822
+\i (00:05:21) trapsize 2
+\i (00:05:21) zoom in 1 
+\i (00:05:21) setwindow pcb
+\i (00:05:21) zoom in 2.654 -2.822
+\i (00:05:21) trapsize 1
+\i (00:05:21) zoom in 1 
+\i (00:05:21) setwindow pcb
+\i (00:05:21) zoom in 2.654 -2.822
+\i (00:05:21) trapsize 1
+\i (00:05:22) zoom out 1 
+\i (00:05:22) setwindow pcb
+\i (00:05:22) zoom out 2.656 -2.811
+\i (00:05:22) trapsize 1
+\i (00:05:22) zoom out 1 
+\i (00:05:22) setwindow pcb
+\i (00:05:22) zoom out 2.656 -2.811
+\i (00:05:22) trapsize 2
+\i (00:05:22) zoom out 1 
+\i (00:05:22) setwindow pcb
+\i (00:05:22) zoom out 2.656 -2.811
+\i (00:05:22) trapsize 3
+\i (00:05:25) pick grid 2.644 -2.654
+\t (00:05:25) last pick:  2.640 -2.650
+\i (00:05:25) zoom out 1 
+\i (00:05:25) setwindow pcb
+\i (00:05:25) zoom out 2.747 -2.718
+\i (00:05:25) trapsize 6
+\i (00:05:26) zoom out 1 
 \i (00:05:26) setwindow pcb
-\i (00:05:26) trapsize 3638
-\t (00:05:26) Performing DRC...
-\t (00:05:26) No DRC errors detected.
-\w (00:05:26) WARNING(SPMHUT-48): Scaled value has been rounded off.
-\i (00:05:26) trapsize 3638
-\i (00:05:27) trapsize 64
-\i (00:05:27) trapsize 51
-\i (00:05:27) trapsize 51
-\i (00:05:27) trapsize 51
-\t (00:05:27) Performing DRC...
-\t (00:05:27) No DRC errors detected.
-\t (00:05:27) Creating package symbol 'D:/Workspace/GitHub/pcb_lib/chip/tqfp-48-ep.psm'.
-\t (00:05:27) Starting Create symbol...
-\i (00:05:35) zoom out 1 
+\i (00:05:26) zoom out 2.746 -2.718
+\i (00:05:26) trapsize 13
+\i (00:05:26) zoom out 1 
+\i (00:05:26) setwindow pcb
+\i (00:05:26) zoom out 2.746 -2.717
+\t (00:05:26) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
+\i (00:05:26) trapsize 25
+\i (00:05:28) zoom in 1 
+\i (00:05:28) setwindow pcb
+\i (00:05:28) zoom in -2.811 -2.647
+\t (00:05:28) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
+\i (00:05:28) trapsize 13
+\i (00:05:29) zoom in 1 
+\i (00:05:29) setwindow pcb
+\i (00:05:29) zoom in -2.709 -2.649
+\i (00:05:29) trapsize 6
+\i (00:05:29) zoom in 1 
+\i (00:05:29) setwindow pcb
+\i (00:05:29) zoom in -2.709 -2.649
+\i (00:05:29) trapsize 3
+\i (00:05:29) zoom in 1 
+\i (00:05:29) setwindow pcb
+\i (00:05:29) zoom in -2.709 -2.649
+\i (00:05:29) trapsize 2
+\i (00:05:29) zoom in 1 
+\i (00:05:29) setwindow pcb
+\i (00:05:29) zoom in -2.708 -2.649
+\i (00:05:29) trapsize 1
+\i (00:05:31) pick grid -2.639 -2.646
+\t (00:05:31) last pick:  -2.640 -2.650
+\i (00:05:32) zoom out 1 
+\i (00:05:32) setwindow pcb
+\i (00:05:32) zoom out -2.626 -2.674
+\i (00:05:32) trapsize 2
+\i (00:05:32) zoom out 1 
+\i (00:05:32) setwindow pcb
+\i (00:05:32) zoom out -2.626 -2.674
+\i (00:05:32) trapsize 3
+\i (00:05:32) zoom out 1 
+\i (00:05:32) setwindow pcb
+\i (00:05:32) zoom out -2.626 -2.673
+\i (00:05:32) trapsize 6
+\i (00:05:32) zoom out 1 
+\i (00:05:32) setwindow pcb
+\i (00:05:32) zoom out -2.627 -2.672
+\i (00:05:32) trapsize 13
+\i (00:05:32) zoom out 1 
+\i (00:05:32) setwindow pcb
+\i (00:05:32) zoom out -2.628 -2.672
+\t (00:05:32) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
+\i (00:05:32) trapsize 25
+\i (00:05:32) zoom out 1 
+\i (00:05:32) setwindow pcb
+\i (00:05:32) zoom out -2.628 -2.672
+\t (00:05:32) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
+\i (00:05:32) trapsize 51
+\i (00:05:32) zoom out 1 
+\i (00:05:32) setwindow pcb
+\i (00:05:32) zoom out -2.629 -2.673
+\t (00:05:32) Grids are drawn 0.160, 0.160 apart for enhanced viewing.
+\i (00:05:32) trapsize 101
+\i (00:05:33) zoom in 1 
+\i (00:05:33) setwindow pcb
+\i (00:05:33) zoom in -2.372 2.593
+\t (00:05:33) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
+\i (00:05:33) trapsize 50
+\i (00:05:33) zoom in 1 
+\i (00:05:33) setwindow pcb
+\i (00:05:33) zoom in -2.372 2.593
+\t (00:05:33) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
+\i (00:05:33) trapsize 25
+\i (00:05:33) zoom in 1 
+\i (00:05:33) setwindow pcb
+\i (00:05:33) zoom in -2.371 2.593
+\t (00:05:33) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
+\i (00:05:33) trapsize 13
+\i (00:05:35) zoom in 1 
 \i (00:05:35) setwindow pcb
-\i (00:05:35) zoom out 0.669 2.141
-\i (00:05:35) trapsize 103
-\i (00:05:36) zoom in 1 
-\i (00:05:36) setwindow pcb
-\i (00:05:36) zoom in -0.937 -0.467
-\i (00:05:36) trapsize 51
-\i (00:08:07) param in 
-\i (00:08:08) setwindow form.parm_in
-\i (00:08:08) FORM parm_in cancel  
-\i (00:14:09) setwindow pcb
-\i (00:14:09) step pkg map 
-\i (00:14:10) fillin yes 
-\i (00:14:14) setwindow form.pkgmap3d
-\i (00:14:14) FORM pkgmap3d namefilter_stp tqfp-48.STEP 
-\i (00:14:15) FORM pkgmap3d stplist tqfp-48.STEP 
-\i (00:14:20) FORM pkgmap3d overlay YES 
-\i (00:14:22) FORM pkgmap3d hide_board YES 
-\i (00:14:27) FORM pkgmap3d view_orientation Bottom 
-\i (00:14:31) FORM pkgmap3d view_orientation Top 
-\i (00:16:12) FORM pkgmap3d save_current  
-\i (00:16:14) FORM pkgmap3d done  
-\i (00:17:49) setwindow pcb
-\i (00:17:49) add pin 
-\i (00:17:53) add pin 
-\t (00:17:53) Exiting from Add Pin.
-\i (00:17:56) change 
-\t (00:17:56) Exiting from Add Pin.
-\i (00:17:59) setwindow form.find
-\i (00:17:59) FORM find all_off  
-\i (00:18:03) setwindow pcb
-\i (00:18:03) add pin 
-\i (00:19:30) replace padstack 
-\t (00:19:30) Exiting from Add Pin.
-\i (00:19:36) setwindow form.mini
-\i (00:19:36) FORM mini oldname_browse  
-\t (00:19:43) No valid name selected.
-\t (00:19:44) No valid name selected.
-\i (00:19:48) fillin "Tqfp-48-ep"
-\i (00:19:50) FORM mini newname_browse  
-\i (00:19:55) fillin "Tqfp-48-ep"
-\w (00:19:55) WARNING(SPMHUT-48): Scaled value has been rounded off.
-\i (00:19:57) FORM mini replace  
-\t (00:19:57) Done, updated padstack.
-\t (00:19:58) 48 out of 48 old padstack TQFP-48-EP were replaced with new padstack TQFP-48-EP.
-\i (00:20:08) setwindow pcb
-\i (00:20:08) step pkg map 
-\t (00:20:08) Performing DRC...
-\t (00:20:08) No DRC errors detected.
-\i (00:20:09) fillin yes 
-\i (00:20:24) setwindow form.pkgmap3d
-\i (00:20:24) FORM pkgmap3d done  
-\i (00:21:24) setwindow pcb
-\i (00:21:24) replace padstack 
-\i (00:21:26) setwindow form.mini
-\i (00:21:26) FORM mini oldname_browse  
-\t (00:21:33) No valid name selected.
-\t (00:21:34) No valid name selected.
-\i (00:21:37) fillin "Tqfp-48-ep"
-\i (00:21:38) FORM mini newname_browse  
-\i (00:21:41) fillin "Tqfp-48-ep"
-\w (00:21:41) WARNING(SPMHUT-48): Scaled value has been rounded off.
-\i (00:21:42) FORM mini replace  
-\t (00:21:42) Done, updated padstack.
-\t (00:21:42) 48 out of 48 old padstack TQFP-48-EP were replaced with new padstack TQFP-48-EP.
-\i (00:21:50) setwindow pcb
-\i (00:21:50) step pkg map 
-\t (00:21:50) Performing DRC...
-\t (00:21:50) No DRC errors detected.
-\i (00:21:51) fillin yes 
-\i (00:21:59) setwindow form.pkgmap3d
-\i (00:21:59) FORM pkgmap3d view_orientation Front 
-\i (00:22:03) FORM pkgmap3d offset_z 2 
-\i (00:22:05) FORM pkgmap3d offset_z 1 
-\i (00:22:09) FORM pkgmap3d offset_z 0.5 
-\i (00:22:12) FORM pkgmap3d offset_z 0.75 
-\i (00:22:16) FORM pkgmap3d view_orientation Top 
-\i (00:22:20) FORM pkgmap3d save_current  
-\i (00:22:22) FORM pkgmap3d done  
-\i (00:22:24) setwindow pcb
-\i (00:22:24) save 
-\i (00:22:26) fillin yes 
-\t (00:22:27) Symbol 'tqfp-48-ep.psm' created.
-\i (00:22:34) param in 
-\i (00:22:35) setwindow form.parm_in
-\i (00:22:35) FORM parm_in browse  
-\i (00:22:43) fillin "D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm"
-\i (00:22:44) FORM parm_in execute  
-\t (00:22:44) Starting Importing parameter file...
-\w (00:22:46) WARNING(SPMHGE-269): param in had warnings, use Viewlog to review the log file.
-\t (00:22:46) Opening existing design...
-\t (00:22:46) Grids are drawn 40.640, 40.640 apart for enhanced viewing.
-\i (00:22:46) setwindow pcb
-\i (00:22:46) trapsize 51
-\i (00:22:50) setwindow text
-\i (00:22:50) close
-\i (00:22:50) setwindow form.parm_in
-\i (00:22:50) FORM parm_in cancel  
-\i (00:22:53) setwindow pcb
-\i (00:22:53) zoom out 1 
-\i (00:22:53) setwindow pcb
-\i (00:22:53) zoom out 0.532 0.324
-\i (00:22:53) trapsize 103
-\i (00:23:02) add line 
-\i (00:23:05) setwindow form.mini
-\i (00:23:05) FORM mini class 'EMBEDDED GEOMETRY' 
-\i (00:23:12) FORM mini class 'PACKAGE GEOMETRY' 
-\i (00:23:17) FORM mini subclass SILKSCREEN_TOP 
-\i (00:23:18) setwindow pcb
-\i (00:23:18) updateport CVPane
-\i (00:23:21) setwindow form.mini
-\i (00:23:21) FORM mini line_width 0.150 
-\i (00:23:29) setwindow pcb
-\i (00:23:29) define grid 
-\t (00:23:29) Spacing fields allow simple equations to aid calculations; prefix with =
-\i (00:23:33) setwindow form.grid
-\i (00:23:33) FORM grid non_etch non_etch_x_grids 0.01 
-\i (00:23:35) FORM grid non_etch non_etch_y_grids 0.01 
-\i (00:23:36) FORM grid all_etch all_etch_x_grids 0.01 
-\i (00:23:38) FORM grid all_etch all_etch_y_grids 0.01 
-\i (00:23:39) FORM grid all_etch all_etch_x_offset 0.000 
-\i (00:23:39) FORM grid all_etch all_etch_y_offset 0.000 
-\i (00:23:39) FORM grid top subclass_x_grids 0.010 
-\i (00:23:39) FORM grid top subclass_x_grids 0.010 
-\i (00:23:39) FORM grid done  
-\t (00:23:39) Grids are drawn 0.160, 0.160 apart for enhanced viewing.
-\i (00:23:43) setwindow pcb
-\i (00:23:43) zoom in 1 
-\i (00:23:43) setwindow pcb
-\i (00:23:43) zoom in -2.847 3.035
-\t (00:23:43) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
-\i (00:23:43) trapsize 51
-\i (00:23:43) zoom in 1 
-\i (00:23:43) setwindow pcb
-\i (00:23:43) zoom in -2.847 3.035
-\t (00:23:43) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:23:43) trapsize 26
-\i (00:23:43) zoom in 1 
-\i (00:23:43) setwindow pcb
-\i (00:23:43) zoom in -2.846 3.036
-\t (00:23:43) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
-\i (00:23:43) trapsize 13
-\i (00:23:44) zoom out 1 
-\i (00:23:44) setwindow pcb
-\i (00:23:44) zoom out -2.846 3.036
-\t (00:23:44) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:23:44) trapsize 26
-\i (00:23:44) zoom out 1 
-\i (00:23:44) setwindow pcb
-\i (00:23:44) zoom out -2.846 3.036
-\t (00:23:44) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
-\i (00:23:44) trapsize 51
-\i (00:23:55) save 
-\i (00:23:56) fillin yes 
-\t (00:23:56) Symbol 'tqfp-48-ep.psm' created.
-\i (00:23:59) change 
-\i (00:24:03) setwindow form.mini
-\i (00:24:03) FORM mini change_class 'PACKAGE GEOMETRY' 
-\i (00:24:07) FORM mini change_subclass PIN_NUMBER 
-\i (00:24:17) FORM mini text_name pin 
-\i (00:24:20) setwindow pcb
-\i (00:24:20) color192 
-\i (00:24:22) QtSignal CVDLayerContainer CVDVisibilityOff clicked
-\i (00:24:26) QtSignal CVDLayerContainer CVDFilterLayerEntry editingFinished pin
-\i (00:24:26) QtSignal CVDLayerTable CVDLayerTableDelegate clickedBox "Pin_Number" PkgGeo 1
-\i (00:24:26) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 0 0
-\i (00:24:27) QtSignal CVDLayerSplitter CVDLayerTable selectionChanged
-\i (00:24:28) QtSignal ColorVisibilityDialog CVDOkButton clicked
-\i (00:24:29) drag_start grid -6.246 5.870
-\i (00:24:30) roam y 128
-\i (00:24:31) roam y 128
-\i (00:24:31) roam y 128
-\i (00:24:31) roam y 128
-\i (00:24:31) roam y 112
-\i (00:24:31) roam y 96
-\i (00:24:31) roam y 64
-\i (00:24:32) roam y 48
-\i (00:24:32) roam y 16
-\i (00:24:32) drag_stop 6.665 -12.642
-\t (00:24:32) No DRC errors detected.
-\t (00:24:32) Changed 48 items out of 48 items found.
-\i (00:24:33) prepopup 3.953 -10.311
-\i (00:24:33) done 
-\i (00:24:36) color192 
-\i (00:24:37) QtSignal CVDLayerContainer CVDVisibilityOff clicked
-\i (00:24:38) QtSignal CVDLayerContainer CVDVisibilityOn clicked
-\i (00:24:48) QtSignal CVDLayerContainer CVDFilterLayerEntry editingFinished sil
-\i (00:24:48) QtSignal CVDLayerContainer CVDVisibilityOff clicked
-\i (00:24:49) QtSignal CVDLayerTable VertHeader clickedCheckBox "Silkscreen_Top" 1
-\i (00:24:49) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 1 0
-\i (00:24:51) QtSignal ColorVisibilityDialog CVDOkButton clicked
-\i (00:24:54) delete 
-\i (00:24:59) pick grid -3.299 -3.501
-\t (00:24:59) last pick:  -3.300 -3.500
-\i (00:25:01) color192 
-\i (00:25:03) QtSignal CVDLayerContainer CVDVisibilityOn clicked
-\i (00:25:04) QtSignal ColorVisibilityDialog CVDOkButton clicked
-\i (00:25:05) zoom in 1 
-\i (00:25:05) setwindow pcb
-\i (00:25:05) zoom in -4.100 -12.488
-\t (00:25:05) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:25:05) trapsize 26
-\i (00:25:05) zoom out 1 
-\i (00:25:05) setwindow pcb
-\i (00:25:05) zoom out -4.100 -12.488
-\t (00:25:05) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
-\i (00:25:05) trapsize 51
-\i (00:25:05) zoom out 1 
-\i (00:25:05) setwindow pcb
-\i (00:25:05) zoom out -4.100 -12.488
-\t (00:25:05) Grids are drawn 0.160, 0.160 apart for enhanced viewing.
-\i (00:25:05) trapsize 103
-\i (00:25:05) zoom out 1 
-\i (00:25:05) setwindow pcb
-\i (00:25:05) zoom out -5.353 -12.489
-\i (00:25:05) trapsize 140
-\i (00:25:06) zoom out 1 
-\i (00:25:06) setwindow pcb
-\i (00:25:06) zoom out -1.848 -13.138
-\i (00:25:06) trapsize 140
-\i (00:25:06) zoom out 1 
-\i (00:25:06) setwindow pcb
-\i (00:25:06) zoom out -1.848 -13.138
-\i (00:25:06) trapsize 140
-\i (00:25:09) done 
-\i (00:25:10) save 
-\i (00:25:12) fillin yes 
-\t (00:25:13) Symbol 'tqfp-48-ep.psm' created.
-\i (00:25:13) zoom in 1 
-\i (00:25:13) setwindow pcb
-\i (00:25:13) zoom in -0.563 -1.174
-\t (00:25:13) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
-\i (00:25:13) trapsize 70
-\e (00:25:25) Command not found: de
-\e (00:25:25) Command not found: ete
-\i (00:25:25) trapsize 70
-\i (00:25:26) delete 
-\i (00:25:30) setwindow form.find
-\i (00:25:30) FORM find all_on  
-\i (00:25:35) setwindow pcb
-\i (00:25:35) color192 
-\i (00:25:37) trapsize 70
-\i (00:25:37) trapsize 70
-\i (00:25:41) add line 
-\i (00:25:49) zoom in 1 
-\i (00:25:49) setwindow pcb
-\i (00:25:49) zoom in -3.436 3.606
-\t (00:25:49) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:25:49) trapsize 35
-\i (00:25:50) zoom in 1 
-\i (00:25:50) setwindow pcb
-\i (00:25:50) zoom in -3.463 3.522
-\t (00:25:50) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
-\i (00:25:50) trapsize 17
-\i (00:25:50) zoom in 1 
-\i (00:25:50) setwindow pcb
-\i (00:25:50) zoom in -3.464 3.523
-\i (00:25:50) trapsize 9
-\i (00:25:50) zoom in 1 
-\i (00:25:50) setwindow pcb
-\i (00:25:50) zoom in -3.463 3.524
-\i (00:25:50) trapsize 4
-\i (00:25:50) zoom in 1 
-\i (00:25:50) setwindow pcb
-\i (00:25:50) zoom in -3.463 3.524
-\i (00:25:50) trapsize 2
-\i (00:25:50) zoom in 1 
-\i (00:25:50) setwindow pcb
-\i (00:25:50) zoom in -3.463 3.524
-\i (00:25:50) trapsize 1
-\i (00:25:50) zoom in 1 
-\i (00:25:50) setwindow pcb
-\i (00:25:50) zoom in -3.463 3.524
-\i (00:25:50) trapsize 1
-\i (00:25:50) zoom in 1 
-\i (00:25:50) setwindow pcb
-\i (00:25:50) zoom in -3.462 3.524
-\i (00:25:50) trapsize 1
-\i (00:25:50) zoom in 1 
-\i (00:25:50) setwindow pcb
-\i (00:25:50) zoom in -3.463 3.524
-\i (00:25:50) trapsize 1
-\i (00:25:50) zoom in 1 
-\i (00:25:50) setwindow pcb
-\i (00:25:50) zoom in -3.464 3.525
-\i (00:25:50) trapsize 1
-\i (00:25:50) zoom in 1 
-\i (00:25:50) setwindow pcb
-\i (00:25:50) zoom in -3.466 3.526
-\i (00:25:50) trapsize 1
-\i (00:25:50) zoom in 1 
-\i (00:25:50) setwindow pcb
-\i (00:25:50) zoom in -3.470 3.529
-\i (00:25:50) trapsize 1
-\i (00:25:50) zoom out 1 
-\i (00:25:50) setwindow pcb
-\i (00:25:50) zoom out -3.474 3.532
-\i (00:25:50) trapsize 1
-\i (00:25:50) zoom out 1 
-\i (00:25:50) setwindow pcb
-\i (00:25:50) zoom out -3.474 3.532
-\i (00:25:50) trapsize 1
-\i (00:25:50) zoom out 1 
-\i (00:25:50) setwindow pcb
-\i (00:25:50) zoom out -3.473 3.533
-\i (00:25:50) trapsize 1
-\i (00:25:50) zoom out 1 
-\i (00:25:50) setwindow pcb
-\i (00:25:50) zoom out -3.474 3.532
-\i (00:25:50) trapsize 2
-\i (00:25:50) zoom out 1 
-\i (00:25:50) setwindow pcb
-\i (00:25:50) zoom out -3.474 3.533
-\i (00:25:50) trapsize 3
-\i (00:25:53) pick grid -3.499 3.501
-\t (00:25:53) last pick:  -3.500 3.500
-\i (00:25:54) zoom out 1 
-\i (00:25:54) setwindow pcb
-\i (00:25:54) zoom out -3.422 3.466
-\i (00:25:54) trapsize 7
-\i (00:25:54) zoom out 1 
-\i (00:25:54) setwindow pcb
-\i (00:25:54) zoom out -3.422 3.467
-\i (00:25:54) trapsize 13
-\i (00:25:54) zoom out 1 
-\i (00:25:54) setwindow pcb
-\i (00:25:54) zoom out -3.423 3.466
-\t (00:25:54) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:25:54) trapsize 26
-\i (00:25:54) zoom out 1 
-\i (00:25:54) setwindow pcb
-\i (00:25:54) zoom out -3.422 3.466
-\t (00:25:54) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
-\i (00:25:54) trapsize 52
-\i (00:25:55) zoom in 1 
-\i (00:25:56) setwindow pcb
-\i (00:25:56) zoom in 3.624 3.634
-\t (00:25:56) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:25:56) trapsize 26
-\i (00:25:56) zoom in 1 
-\i (00:25:56) setwindow pcb
-\i (00:25:56) zoom in 3.624 3.634
-\t (00:25:56) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
-\i (00:25:56) trapsize 13
-\i (00:25:58) zoom in 1 
-\i (00:25:58) setwindow pcb
-\i (00:25:58) zoom in 3.504 3.483
-\i (00:25:58) trapsize 7
-\i (00:25:58) zoom in 1 
-\i (00:25:58) setwindow pcb
-\i (00:25:58) zoom in 3.505 3.483
-\i (00:25:58) trapsize 3
-\i (00:25:58) zoom in 1 
-\i (00:25:58) setwindow pcb
-\i (00:25:58) zoom in 3.505 3.483
-\i (00:25:58) trapsize 2
-\i (00:25:58) zoom in 1 
-\i (00:25:58) setwindow pcb
-\i (00:25:58) zoom in 3.505 3.483
-\i (00:25:58) trapsize 1
-\i (00:25:58) zoom in 1 
-\i (00:25:58) setwindow pcb
-\i (00:25:58) zoom in 3.505 3.483
-\i (00:25:58) trapsize 1
-\i (00:26:00) pick grid 3.502 3.495
-\t (00:26:00) last pick:  3.500 3.500
-\i (00:26:01) zoom out 1 
-\i (00:26:01) setwindow pcb
-\i (00:26:01) zoom out 3.481 3.484
-\i (00:26:01) trapsize 1
-\i (00:26:01) zoom out 1 
-\i (00:26:01) setwindow pcb
-\i (00:26:01) zoom out 3.482 3.484
-\i (00:26:01) trapsize 2
-\i (00:26:01) zoom out 1 
-\i (00:26:01) setwindow pcb
-\i (00:26:01) zoom out 3.481 3.484
-\i (00:26:01) trapsize 3
-\i (00:26:01) zoom out 1 
-\i (00:26:01) setwindow pcb
-\i (00:26:01) zoom out 3.481 3.484
-\i (00:26:01) trapsize 7
-\i (00:26:01) zoom out 1 
-\i (00:26:02) setwindow pcb
-\i (00:26:02) zoom out 3.482 3.485
-\i (00:26:02) trapsize 13
-\i (00:26:02) zoom out 1 
-\i (00:26:02) setwindow pcb
-\i (00:26:02) zoom out 3.482 3.485
-\t (00:26:02) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:26:02) trapsize 26
-\i (00:26:02) zoom out 1 
-\i (00:26:02) setwindow pcb
-\i (00:26:02) zoom out 3.481 3.484
-\t (00:26:02) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
-\i (00:26:02) trapsize 52
-\i (00:26:03) zoom in 1 
-\i (00:26:03) setwindow pcb
-\i (00:26:03) zoom in 3.492 -3.623
-\t (00:26:03) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:26:04) trapsize 26
-\i (00:26:04) zoom in 1 
-\i (00:26:04) setwindow pcb
-\i (00:26:04) zoom in 3.492 -3.623
-\t (00:26:04) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
-\i (00:26:04) trapsize 13
-\i (00:26:06) zoom in 1 
-\i (00:26:06) setwindow pcb
-\i (00:26:06) zoom in 3.503 -3.523
-\i (00:26:06) trapsize 7
-\i (00:26:06) zoom in 1 
-\i (00:26:06) setwindow pcb
-\i (00:26:06) zoom in 3.503 -3.523
-\i (00:26:06) trapsize 3
-\i (00:26:06) zoom in 1 
-\i (00:26:06) setwindow pcb
-\i (00:26:06) zoom in 3.503 -3.523
-\i (00:26:06) trapsize 2
-\i (00:26:06) zoom in 1 
-\i (00:26:06) setwindow pcb
-\i (00:26:06) zoom in 3.504 -3.523
-\i (00:26:06) trapsize 1
-\i (00:26:06) zoom in 1 
-\i (00:26:06) setwindow pcb
-\i (00:26:06) zoom in 3.504 -3.523
-\i (00:26:06) trapsize 1
-\i (00:26:06) zoom in 1 
-\i (00:26:06) setwindow pcb
-\i (00:26:06) zoom in 3.505 -3.522
-\i (00:26:06) trapsize 1
-\i (00:26:06) zoom out 1 
-\i (00:26:06) setwindow pcb
-\i (00:26:06) zoom out 3.505 -3.511
-\i (00:26:06) trapsize 1
-\i (00:26:07) zoom out 1 
-\i (00:26:07) setwindow pcb
-\i (00:26:07) zoom out 3.506 -3.511
-\i (00:26:07) trapsize 1
-\i (00:26:07) zoom out 1 
-\i (00:26:07) setwindow pcb
-\i (00:26:07) zoom out 3.506 -3.512
-\i (00:26:07) trapsize 2
-\i (00:26:07) zoom out 1 
-\i (00:26:07) setwindow pcb
-\i (00:26:07) zoom out 3.506 -3.511
-\i (00:26:07) trapsize 3
-\i (00:26:07) zoom out 1 
-\i (00:26:07) setwindow pcb
-\i (00:26:07) zoom out 3.505 -3.512
-\i (00:26:07) trapsize 7
-\i (00:26:09) zoom in 1 
-\i (00:26:09) setwindow pcb
-\i (00:26:09) zoom in 3.500 -3.504
-\i (00:26:09) trapsize 3
-\i (00:26:11) zoom in 1 
-\i (00:26:11) setwindow pcb
-\i (00:26:11) zoom in 3.500 -3.504
-\i (00:26:11) trapsize 2
-\i (00:26:13) pick grid 3.500 -3.504
-\t (00:26:13) last pick:  3.500 -3.500
-\i (00:26:14) zoom out 1 
-\i (00:26:14) setwindow pcb
-\i (00:26:14) zoom out 3.542 -3.506
-\i (00:26:14) trapsize 3
-\i (00:26:14) zoom out 1 
-\i (00:26:14) setwindow pcb
-\i (00:26:14) zoom out 3.541 -3.507
-\i (00:26:14) trapsize 7
-\i (00:26:14) zoom out 1 
-\i (00:26:14) setwindow pcb
-\i (00:26:14) zoom out 3.542 -3.507
-\i (00:26:14) trapsize 13
-\i (00:26:14) zoom out 1 
-\i (00:26:14) setwindow pcb
-\i (00:26:14) zoom out 3.542 -3.506
-\t (00:26:14) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:26:14) trapsize 26
-\i (00:26:15) zoom out 1 
-\i (00:26:15) setwindow pcb
-\i (00:26:15) zoom out 2.830 -3.262
-\t (00:26:15) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
-\i (00:26:15) trapsize 52
-\i (00:26:15) zoom out 1 
-\i (00:26:15) setwindow pcb
-\i (00:26:15) zoom out 2.830 -3.261
-\t (00:26:15) Grids are drawn 0.160, 0.160 apart for enhanced viewing.
-\i (00:26:15) trapsize 104
-\i (00:26:15) zoom out 1 
-\i (00:26:15) setwindow pcb
-\i (00:26:15) zoom out 4.851 -3.261
-\i (00:26:15) trapsize 140
-\i (00:26:15) zoom out 1 
-\i (00:26:15) setwindow pcb
-\i (00:26:15) zoom out 11.681 -4.836
-\i (00:26:15) trapsize 140
-\i (00:26:17) zoom in 1 
-\i (00:26:17) setwindow pcb
-\i (00:26:17) zoom in -3.358 -3.383
-\t (00:26:17) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
-\i (00:26:17) trapsize 70
-\i (00:26:17) zoom in 1 
-\i (00:26:17) setwindow pcb
-\i (00:26:17) zoom in -5.295 -3.382
-\t (00:26:17) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:26:17) trapsize 35
-\i (00:26:17) zoom in 1 
-\i (00:26:17) setwindow pcb
-\i (00:26:17) zoom in -5.295 -3.382
-\t (00:26:17) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
-\i (00:26:17) trapsize 17
-\i (00:26:17) zoom in 1 
-\i (00:26:17) setwindow pcb
-\i (00:26:17) zoom in -5.296 -3.381
-\i (00:26:17) trapsize 9
-\i (00:26:19) zoom in 1 
-\i (00:26:19) setwindow pcb
-\i (00:26:19) zoom in -3.468 -3.463
-\i (00:26:19) trapsize 4
-\i (00:26:25) pick grid -3.496 -3.499
-\t (00:26:25) last pick:  -3.500 -3.500
-\t (00:26:25) Merged with existing line. Start next line.
-\i (00:26:26) zoom out 1 
-\i (00:26:26) setwindow pcb
-\i (00:26:26) zoom out -3.869 -3.548
-\i (00:26:26) trapsize 9
-\i (00:26:26) zoom out 1 
-\i (00:26:26) setwindow pcb
-\i (00:26:26) zoom out -3.869 -3.548
-\i (00:26:26) trapsize 17
-\i (00:26:26) zoom out 1 
-\i (00:26:26) setwindow pcb
-\i (00:26:26) zoom out -3.869 -3.548
-\t (00:26:26) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:26:26) trapsize 35
-\i (00:26:26) zoom out 1 
-\i (00:26:26) setwindow pcb
-\i (00:26:26) zoom out -3.870 -3.547
-\t (00:26:26) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
-\i (00:26:26) trapsize 70
-\i (00:26:26) zoom out 1 
-\i (00:26:26) setwindow pcb
-\i (00:26:26) zoom out -1.005 -3.547
-\t (00:26:26) Grids are drawn 0.160, 0.160 apart for enhanced viewing.
-\i (00:26:26) trapsize 140
-\i (00:26:29) zoom in 1 
-\i (00:26:29) setwindow pcb
-\i (00:26:29) zoom in -3.442 3.466
-\t (00:26:29) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
-\i (00:26:29) trapsize 70
-\i (00:26:33) zoom in 1 
-\i (00:26:33) setwindow pcb
-\i (00:26:33) zoom in -3.450 3.550
-\t (00:26:33) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:26:33) trapsize 35
-\i (00:26:38) zoom in 1 
-\i (00:26:38) setwindow pcb
-\i (00:26:38) zoom in -3.498 3.487
-\t (00:26:38) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
-\i (00:26:38) trapsize 17
-\i (00:26:41) pick grid -3.502 3.505
-\t (00:26:41) last pick:  -3.500 3.510
-\t (00:26:41) last pick:  -3.500 3.500
-\i (00:26:43) zoom out 1 
-\i (00:26:43) setwindow pcb
-\i (00:26:43) zoom out -3.370 3.180
-\t (00:26:43) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:26:43) trapsize 35
-\i (00:26:43) zoom out 1 
-\i (00:26:43) setwindow pcb
-\i (00:26:43) zoom out -3.370 3.180
-\t (00:26:43) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
-\i (00:26:43) trapsize 70
-\i (00:26:43) zoom out 1 
-\i (00:26:43) setwindow pcb
-\i (00:26:43) zoom out -3.370 3.181
-\t (00:26:43) Grids are drawn 0.160, 0.160 apart for enhanced viewing.
-\i (00:26:43) trapsize 140
-\i (00:26:47) prepopup -7.215 4.500
-\i (00:26:47) done 
-\i (00:26:49) zoom in 1 
-\i (00:26:49) setwindow pcb
-\i (00:26:49) zoom in -0.311 1.565
-\t (00:26:49) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
-\i (00:26:49) trapsize 70
-\i (00:26:51) add line 
-\i (00:26:54) zoom in 1 
-\i (00:26:54) setwindow pcb
-\i (00:26:54) zoom in -3.464 3.438
-\t (00:26:54) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:26:54) trapsize 35
-\i (00:26:54) zoom in 1 
-\i (00:26:54) setwindow pcb
-\i (00:26:54) zoom in -3.463 3.438
-\t (00:26:54) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
-\i (00:26:54) trapsize 17
-\i (00:26:54) zoom in 1 
-\i (00:26:54) setwindow pcb
-\i (00:26:54) zoom in -3.464 3.439
-\i (00:26:54) trapsize 9
-\i (00:26:54) zoom in 1 
-\i (00:26:54) setwindow pcb
-\i (00:26:54) zoom in -3.464 3.439
-\i (00:26:54) trapsize 4
-\i (00:26:54) zoom in 1 
-\i (00:26:54) setwindow pcb
-\i (00:26:54) zoom in -3.463 3.440
-\i (00:26:54) trapsize 2
-\i (00:26:54) zoom in 1 
-\i (00:26:54) setwindow pcb
-\i (00:26:54) zoom in -3.463 3.440
-\i (00:26:54) trapsize 1
-\i (00:26:54) zoom in 1 
-\i (00:26:54) setwindow pcb
-\i (00:26:54) zoom in -3.463 3.440
-\i (00:26:54) trapsize 1
-\i (00:26:55) zoom out 1 
-\i (00:26:55) setwindow pcb
-\i (00:26:55) zoom out -3.470 3.424
-\i (00:26:55) trapsize 1
-\i (00:26:58) pick grid -3.499 3.500
-\t (00:26:58) last pick:  -3.500 3.500
-\i (00:26:59) zoom out 1 
-\i (00:26:59) setwindow pcb
-\i (00:26:59) zoom out -3.454 3.459
-\i (00:26:59) trapsize 2
-\i (00:26:59) zoom out 1 
-\i (00:26:59) setwindow pcb
-\i (00:26:59) zoom out -3.455 3.460
-\i (00:26:59) trapsize 4
-\i (00:26:59) zoom out 1 
-\i (00:26:59) setwindow pcb
-\i (00:26:59) zoom out -3.455 3.460
-\i (00:26:59) trapsize 9
-\i (00:26:59) zoom out 1 
-\i (00:26:59) setwindow pcb
-\i (00:26:59) zoom out -3.456 3.459
-\i (00:26:59) trapsize 17
-\i (00:26:59) zoom out 1 
-\i (00:26:59) setwindow pcb
-\i (00:26:59) zoom out -3.456 3.459
-\t (00:26:59) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:26:59) trapsize 35
-\i (00:27:00) zoom out 1 
-\i (00:27:00) setwindow pcb
-\i (00:27:00) zoom out -3.082 3.203
-\t (00:27:00) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
-\i (00:27:00) trapsize 70
-\i (00:27:02) zoom in 1 
-\i (00:27:02) setwindow pcb
-\i (00:27:02) zoom in -3.472 -3.498
-\t (00:27:02) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:27:02) trapsize 35
-\i (00:27:02) zoom in 1 
-\i (00:27:02) setwindow pcb
-\i (00:27:02) zoom in -3.472 -3.498
-\t (00:27:02) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
-\i (00:27:02) trapsize 17
-\i (00:27:03) zoom in 1 
-\i (00:27:03) setwindow pcb
-\i (00:27:03) zoom in -3.472 -3.497
-\i (00:27:03) trapsize 9
-\i (00:27:03) zoom in 1 
-\i (00:27:03) setwindow pcb
-\i (00:27:03) zoom in -3.472 -3.497
-\i (00:27:03) trapsize 4
-\i (00:27:03) zoom in 1 
-\i (00:27:03) setwindow pcb
-\i (00:27:03) zoom in -3.472 -3.496
-\i (00:27:03) trapsize 2
-\i (00:27:06) pick grid -3.496 -3.502
-\t (00:27:06) last pick:  -3.500 -3.500
-\i (00:27:09) done 
-\i (00:27:10) zoom out 1 
-\i (00:27:10) setwindow pcb
-\i (00:27:10) zoom out -3.457 -3.455
-\i (00:27:10) trapsize 4
-\i (00:27:11) zoom out 1 
-\i (00:27:11) setwindow pcb
-\i (00:27:11) zoom out -3.457 -3.455
-\i (00:27:11) trapsize 9
-\i (00:27:11) zoom out 1 
-\i (00:27:11) setwindow pcb
-\i (00:27:11) zoom out -3.457 -3.454
-\i (00:27:11) trapsize 17
-\i (00:27:11) zoom out 1 
-\i (00:27:11) setwindow pcb
-\i (00:27:11) zoom out -3.459 -3.454
-\t (00:27:11) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:27:11) trapsize 35
-\i (00:27:11) zoom out 1 
-\i (00:27:11) setwindow pcb
-\i (00:27:11) zoom out -3.459 -3.454
-\t (00:27:11) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
-\i (00:27:11) trapsize 70
-\i (00:27:11) zoom out 1 
-\i (00:27:11) setwindow pcb
-\i (00:27:11) zoom out -3.459 -3.453
-\t (00:27:11) Grids are drawn 0.160, 0.160 apart for enhanced viewing.
-\i (00:27:11) trapsize 140
-\i (00:27:11) zoom out 1 
-\i (00:27:11) setwindow pcb
-\i (00:27:11) zoom out 2.233 -6.178
-\i (00:27:11) trapsize 140
-\i (00:27:15) shape add rect 
-\i (00:27:18) pick 0 0 
-\t (00:27:18) last pick:  0.000 0.000
-\i (00:27:20) zoom in 1 
-\i (00:27:20) setwindow pcb
-\i (00:27:20) zoom in -3.246 3.522
-\t (00:27:20) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
-\i (00:27:20) trapsize 70
-\i (00:27:21) zoom in 1 
-\i (00:27:21) setwindow pcb
-\i (00:27:21) zoom in -2.793 3.564
-\t (00:27:21) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:27:22) trapsize 35
-\i (00:27:24) zoom in 1 
-\i (00:27:24) setwindow pcb
-\i (00:27:24) zoom in -3.492 3.508
-\t (00:27:24) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
-\i (00:27:24) trapsize 17
-\i (00:27:24) zoom in 1 
-\i (00:27:24) setwindow pcb
-\i (00:27:24) zoom in -3.493 3.508
-\i (00:27:24) trapsize 9
-\i (00:27:24) zoom in 1 
-\i (00:27:24) setwindow pcb
-\i (00:27:24) zoom in -3.493 3.509
-\i (00:27:24) trapsize 4
-\i (00:27:24) zoom in 1 
-\i (00:27:24) setwindow pcb
-\i (00:27:24) zoom in -3.493 3.509
-\i (00:27:24) trapsize 2
-\i (00:27:24) zoom in 1 
-\i (00:27:24) setwindow pcb
-\i (00:27:24) zoom in -3.493 3.509
-\i (00:27:24) trapsize 1
-\i (00:27:27) pick grid -3.497 3.504
-\t (00:27:27) last pick:  -3.500 3.500
-\i (00:27:27) zoom out 1 
-\i (00:27:27) setwindow pcb
-\i (00:27:27) zoom out -3.474 3.514
-\i (00:27:27) trapsize 2
-\i (00:27:27) zoom out 1 
-\i (00:27:27) setwindow pcb
-\i (00:27:27) zoom out -3.474 3.515
-\i (00:27:27) trapsize 4
-\i (00:27:27) zoom out 1 
-\i (00:27:27) setwindow pcb
-\i (00:27:27) zoom out -3.475 3.516
-\i (00:27:27) trapsize 9
-\i (00:27:27) zoom out 1 
-\i (00:27:27) setwindow pcb
-\i (00:27:27) zoom out -3.474 3.515
-\i (00:27:27) trapsize 17
-\i (00:27:27) zoom out 1 
-\i (00:27:27) setwindow pcb
-\i (00:27:27) zoom out -3.475 3.516
-\t (00:27:27) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
-\i (00:27:27) trapsize 35
-\i (00:27:27) zoom out 1 
-\i (00:27:27) setwindow pcb
-\i (00:27:27) zoom out -3.474 3.516
-\t (00:27:27) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
-\i (00:27:27) trapsize 70
-\i (00:27:28) prepopup -3.475 3.516
-\i (00:27:29) done 
-\i (00:27:31) save 
-\i (00:27:32) fillin yes 
-\t (00:27:32) Symbol 'tqfp-48-ep.psm' created.
-\i (00:27:35) exit 
-\t (00:27:35)     Journal end - Thu Apr 24 23:43:04 2025
+\i (00:05:35) zoom in -2.634 2.661
+\i (00:05:35) trapsize 6
+\i (00:05:35) zoom in 1 
+\i (00:05:35) setwindow pcb
+\i (00:05:35) zoom in -2.634 2.661
+\i (00:05:35) trapsize 3
+\i (00:05:35) zoom in 1 
+\i (00:05:35) setwindow pcb
+\i (00:05:35) zoom in -2.635 2.662
+\i (00:05:35) trapsize 2
+\i (00:05:38) pick grid -2.637 2.654
+\t (00:05:38) last pick:  -2.640 2.650
+\i (00:05:39) prepopup -2.637 2.652
+\i (00:05:39) done 
+\i (00:05:39) zoom out 1 
+\i (00:05:39) setwindow pcb
+\i (00:05:39) zoom out -2.637 2.652
+\i (00:05:39) trapsize 3
+\i (00:05:39) zoom out 1 
+\i (00:05:39) setwindow pcb
+\i (00:05:39) zoom out -2.637 2.653
+\i (00:05:40) trapsize 6
+\i (00:05:40) zoom out 1 
+\i (00:05:40) setwindow pcb
+\i (00:05:40) zoom out -2.636 2.653
+\i (00:05:40) trapsize 13
+\i (00:05:40) zoom out 1 
+\i (00:05:40) setwindow pcb
+\i (00:05:40) zoom out -2.637 2.653
+\t (00:05:40) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
+\i (00:05:40) trapsize 25
+\i (00:05:40) zoom out 1 
+\i (00:05:40) setwindow pcb
+\i (00:05:40) zoom out -2.637 2.653
+\t (00:05:40) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
+\i (00:05:40) trapsize 51
+\i (00:05:46) add rect 
+\i (00:05:49) zoom in 1 
+\i (00:05:49) setwindow pcb
+\i (00:05:49) zoom in -2.565 2.684
+\t (00:05:49) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
+\i (00:05:49) trapsize 25
+\i (00:05:49) zoom in 1 
+\i (00:05:49) setwindow pcb
+\i (00:05:49) zoom in -2.626 2.608
+\t (00:05:49) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
+\i (00:05:49) trapsize 13
+\i (00:05:50) zoom in 1 
+\i (00:05:50) setwindow pcb
+\i (00:05:50) zoom in -2.626 2.609
+\i (00:05:50) trapsize 6
+\i (00:05:50) zoom in 1 
+\i (00:05:50) setwindow pcb
+\i (00:05:50) zoom in -2.626 2.609
+\i (00:05:50) trapsize 3
+\i (00:05:50) zoom in 1 
+\i (00:05:50) setwindow pcb
+\i (00:05:50) zoom in -2.626 2.609
+\i (00:05:50) trapsize 2
+\i (00:05:50) zoom in 1 
+\i (00:05:50) setwindow pcb
+\i (00:05:50) zoom in -2.626 2.609
+\i (00:05:50) trapsize 1
+\i (00:05:51) zoom out 1 
+\i (00:05:51) setwindow pcb
+\i (00:05:51) zoom out -2.635 2.582
+\i (00:05:51) trapsize 2
+\i (00:05:51) zoom out 1 
+\i (00:05:51) setwindow pcb
+\i (00:05:51) zoom out -2.635 2.582
+\i (00:05:51) trapsize 3
+\i (00:05:53) pick grid -2.640 2.647
+\t (00:05:53) last pick:  -2.640 2.650
+\i (00:05:54) zoom out 1 
+\i (00:05:54) setwindow pcb
+\i (00:05:54) zoom out -2.664 2.623
+\i (00:05:54) trapsize 6
+\i (00:05:56) pick 0 0 
+\t (00:05:56) last pick:  0.000 0.000
+\i (00:05:57) prepopup -2.476 2.819
+\i (00:05:57) done 
+\i (00:05:58) zoom out 1 
+\i (00:05:58) setwindow pcb
+\i (00:05:58) zoom out -2.476 2.819
+\i (00:05:58) trapsize 13
+\i (00:05:58) zoom out 1 
+\i (00:05:58) setwindow pcb
+\i (00:05:58) zoom out -2.476 2.819
+\t (00:05:58) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
+\i (00:05:58) trapsize 25
+\i (00:05:58) zoom out 1 
+\i (00:05:58) setwindow pcb
+\i (00:05:58) zoom out -2.476 2.819
+\t (00:05:58) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
+\i (00:05:58) trapsize 51
+\i (00:06:00) 3d 
+\i (00:06:01) QtSignal 3DUniFilterDialog UniFilterOkButton clicked
+\i (00:06:05) QtSignal ViewerPanePanel ViewerPaneRowAllConductors clicked false
+\i (00:06:06) QtSignal ViewerPanePanel ViewerPaneRowAllConductors clicked true
+\i (00:06:07) QtSignal ViewerPanePanel ViewerPaneRowAllDielectrics clicked false
+\i (00:06:07) QtSignal ViewerPanePanel ViewerPaneRowAllDielectrics clicked true
+\i (00:06:10) QtSignal pcb3dViewer pcb3dViewer closed
+\i (00:06:12) save 
+\i (00:06:14) fillin yes 
+\t (00:06:14) Symbol 'wsoic-8.psm' created.
+\i (00:06:16) change 
+\i (00:06:19) setwindow form.mini
+\i (00:06:19) FORM mini change_subclass ASSEMBLY_TOP 
+\i (00:06:22) FORM mini text_name asm 
+\i (00:06:24) setwindow form.find
+\i (00:06:24) FORM find all_on  
+\i (00:06:25) setwindow pcb
+\i (00:06:25) pick grid -0.083 0.303
+\t (00:06:25) last pick:  -0.080 0.300
+\e (00:06:25) ERROR(SPMHGE-551): Text on this class cannot be changed to another class.
+\i (00:06:27) pick grid 0.447 0.292
+\t (00:06:27) last pick:  0.450 0.290
+\e (00:06:27) ERROR(SPMHGE-551): Text on this class cannot be changed to another class.
+\i (00:06:39) setwindow form.mini
+\i (00:06:39) FORM mini change_class 'REF DES' 
+\i (00:06:41) FORM mini change_subclass ASSEMBLY_TOP 
+\i (00:06:43) setwindow pcb
+\i (00:06:43) pick grid 0.213 0.353
+\t (00:06:43) last pick:  0.210 0.350
+\t (00:06:43) No DRC errors detected.
+\t (00:06:43) Changed 1 items out of 1 items found.
+\i (00:06:45) pick grid 7.772 3.705
+\t (00:06:45) last pick:  7.770 3.710
+\i (00:06:48) setwindow form.mini
+\i (00:06:48) FORM mini change_subclass SILKSCREEN_TOP 
+\i (00:06:50) FORM mini text_name ski 
+\i (00:06:51) setwindow pcb
+\i (00:06:51) pick grid 6.050 0.343
+\t (00:06:51) last pick:  6.050 0.340
+\t (00:06:51) No DRC errors detected.
+\t (00:06:51) Changed 1 items out of 1 items found.
+\i (00:06:51) prepopup 6.274 2.106
+\i (00:06:52) done 
+\i (00:06:54) move 
+\t (00:06:54) Select element(s) to move.
+\i (00:06:55) pick grid 5.897 0.343
+\t (00:06:55) last pick:  5.900 0.340
+\t (00:06:55) last pick:  5.075 0.000
+\t (00:06:55) Pick new location for the element(s).
+\i (00:06:57) pick grid 0.875 -2.092
+\t (00:06:57) last pick:  0.880 -2.090
+\i (00:06:57) prepopup 5.378 3.247
+\i (00:06:58) done 
+\i (00:07:01) save 
+\i (00:07:02) fillin yes 
+\t (00:07:02) Symbol 'wsoic-8.psm' created.
+\i (00:09:07) step pkg map 
+\i (00:09:08) fillin yes 
+\i (00:09:10) setwindow form.pkgmap3d
+\i (00:09:10) FORM pkgmap3d namefilter_stp wsop-16.step 
+\i (00:09:11) FORM pkgmap3d stplist wsop-16.step 
+\i (00:09:12) FORM pkgmap3d hide_board YES 
+\i (00:09:13) FORM pkgmap3d overlay YES 
+\i (00:09:19) FORM pkgmap3d view_orientation Front 
+\i (00:09:21) FORM pkgmap3d view_orientation Top 
+\i (00:09:28) FORM pkgmap3d save_current  
+\i (00:09:30) FORM pkgmap3d done  
+\i (00:12:49) setwindow pcb
+\i (00:12:49) step pkg map 
+\i (00:12:50) fillin yes 
+\i (00:12:59) setwindow form.pkgmap3d
+\i (00:12:59) FORM pkgmap3d namefilter_stp  
+\i (00:13:01) FORM pkgmap3d stplist wsop-16.step 
+\i (00:13:03) FORM pkgmap3d done  
+\i (00:16:21) setwindow pcb
+\i (00:16:21) show measure 
+\i (00:16:23) pick grid -3.618 1.892
+\t (00:16:23) last pick:  -3.620 1.890
+\i (00:16:24) pick grid 3.666 1.861
+\t (00:16:24) last pick:  3.670 1.860
+\i (00:16:29) setwindow text
+\i (00:16:29) close
+\i (00:16:30) setwindow pcb
+\i (00:16:30) pick grid -5.340 -0.676
+\t (00:16:30) last pick:  -5.340 -0.680
+\i (00:16:30) setwindow text
+\i (00:16:30) close
+\i (00:16:32) setwindow pcb
+\i (00:16:32) prepopup -0.745 3.777
+\i (00:16:33) done 
+\i (00:16:35) save 
+\i (00:16:36) fillin yes 
+\t (00:16:36) Symbol 'wsoic-8.psm' created.
+\i (00:16:49) save 
+\i (00:16:50) fillin yes 
+\t (00:16:51) Symbol 'wsoic-8.psm' created.
+\i (00:16:51) exit 
+\t (00:16:52)     Journal end - Sat May 10 04:45:32 2025
diff --git a/chip/batch_drc.log b/chip/batch_drc.log
index 4bc9f37..fac76e7 100644
--- a/chip/batch_drc.log
+++ b/chip/batch_drc.log
@@ -2,9 +2,9 @@
 (                                                                     )
 (    DRC Update                                                       )
 (                                                                     )
-(    Drawing          : tqfp-48-ep.dra                                )
+(    Drawing          : sym_template.dra                              )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Thu Apr 24 23:37:19 2025                      )
+(    Date/Time        : Sat May 10 04:32:11 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/chip/batch_drc.log,1 b/chip/batch_drc.log,1
index 83e86d0..8eb3552 100644
--- a/chip/batch_drc.log,1
+++ b/chip/batch_drc.log,1
@@ -2,9 +2,9 @@
 (                                                                     )
 (    DRC Update                                                       )
 (                                                                     )
-(    Drawing          : sym_template.dra                              )
+(    Drawing          : tqfp-48-ep.dra                                )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Thu Apr 24 23:20:55 2025                      )
+(    Date/Time        : Thu Apr 24 23:35:37 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/chip/batch_drc.log,2 b/chip/batch_drc.log,2
index 7b27e5e..4bc9f37 100644
--- a/chip/batch_drc.log,2
+++ b/chip/batch_drc.log,2
@@ -2,9 +2,9 @@
 (                                                                     )
 (    DRC Update                                                       )
 (                                                                     )
-(    Drawing          : sym_template.dra                              )
+(    Drawing          : tqfp-48-ep.dra                                )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Thu Apr 24 23:20:56 2025                      )
+(    Date/Time        : Thu Apr 24 23:37:19 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/chip/batch_drc.log,3 b/chip/batch_drc.log,3
index 8eb3552..fac76e7 100644
--- a/chip/batch_drc.log,3
+++ b/chip/batch_drc.log,3
@@ -2,9 +2,9 @@
 (                                                                     )
 (    DRC Update                                                       )
 (                                                                     )
-(    Drawing          : tqfp-48-ep.dra                                )
+(    Drawing          : sym_template.dra                              )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Thu Apr 24 23:35:37 2025                      )
+(    Date/Time        : Sat May 10 04:32:11 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/chip/dangling_lines.rpt b/chip/dangling_lines.rpt
new file mode 100644
index 0000000..e5bf9f6
--- /dev/null
+++ b/chip/dangling_lines.rpt
@@ -0,0 +1,29 @@
+(---------------------------------------------------------------------)
+(                                                                     )
+(    Dangling Line, Via and Antenna Report                            )
+(                                                                     )
+(    Drawing          : wsoic-8.dra                                   )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sat May 10 04:34:41 2025                      )
+(                                                                     )
+(---------------------------------------------------------------------)
+
+
+Report methodology:
+  - Dangling lines have at least one end not connected.
+  - Dangling vias have one or no connection
+      - Plus are not a test, thieving or netshort property via.
+  - Antenna vias do not have connections on their start and end layers.
+      - Plus they are not a thieving vias.
+      - Optionally, VOLTAGE nets, testvias and through vias can be suppressed with
+        the environment variable report_antennavia.
+      - Section may be suppressed by variable report_noantennavia.
+  - Not part of the current partition.
+  - To suppress items in dangle report add the OK_DANGLE property to the via
+    or connect line.
+
+
+<< Summary >>
+  Total dangling lines:       0
+  Total dangling vias:        0
+  Total antenna vias:         0
diff --git a/chip/downrev.log b/chip/downrev.log
index 92b2024..4382cea 100644
--- a/chip/downrev.log
+++ b/chip/downrev.log
@@ -2,9 +2,9 @@
 (                                                                     )
 (    Downrev Design                                                   )
 (                                                                     )
-(    Drawing          : tqfp-48-ep.dra                                )
+(    Drawing          : wsoic-8.dra                                   )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Fri Apr 25 15:01:28 2025                      )
+(    Date/Time        : Sat May 10 04:45:31 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/chip/downrev.log,1 b/chip/downrev.log,1
index 05e2870..92b6c5b 100644
--- a/chip/downrev.log,1
+++ b/chip/downrev.log,1
@@ -2,9 +2,9 @@
 (                                                                     )
 (    Downrev Design                                                   )
 (                                                                     )
-(    Drawing          : tqfp-48-ep-gnd.pad                            )
+(    Drawing          : wsoic-8.dra                                   )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Fri Apr 25 15:00:42 2025                      )
+(    Date/Time        : Sat May 10 04:45:17 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/chip/downrev.log,2 b/chip/downrev.log,2
index 92b2024..4382cea 100644
--- a/chip/downrev.log,2
+++ b/chip/downrev.log,2
@@ -2,9 +2,9 @@
 (                                                                     )
 (    Downrev Design                                                   )
 (                                                                     )
-(    Drawing          : tqfp-48-ep.dra                                )
+(    Drawing          : wsoic-8.dra                                   )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Fri Apr 25 15:01:28 2025                      )
+(    Date/Time        : Sat May 10 04:45:31 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/chip/downrev.log,3 b/chip/downrev.log,3
index 92b2024..4382cea 100644
--- a/chip/downrev.log,3
+++ b/chip/downrev.log,3
@@ -2,9 +2,9 @@
 (                                                                     )
 (    Downrev Design                                                   )
 (                                                                     )
-(    Drawing          : tqfp-48-ep.dra                                )
+(    Drawing          : wsoic-8.dra                                   )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Fri Apr 25 15:01:28 2025                      )
+(    Date/Time        : Sat May 10 04:45:31 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/chip/master.tag b/chip/master.tag
index ddbaa8b..9bc2642 100644
--- a/chip/master.tag
+++ b/chip/master.tag
@@ -1 +1 @@
-tqfp-48-ep.dra
+wsoic-8.dra
diff --git a/chip/padstack_editor.jrl b/chip/padstack_editor.jrl
index 1304389..fb47528 100644
--- a/chip/padstack_editor.jrl
+++ b/chip/padstack_editor.jrl
@@ -1,24 +1,7 @@
 \t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
-\t (00:00:00)     Journal start - Fri Apr 25 15:00:00 2025
-\t (00:00:00)         Host=XEROLYSKINNER User=Xeroly Pid=24896 CPUs=16
-\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\chip\tqfp-48-ep-gnd.pad
+\t (00:00:00)     Journal start - Sat May 10 04:28:20 2025
+\t (00:00:00)         Host=XEROLYSKINNER User=Xeroly Pid=37520 CPUs=16
+\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\chip\wsoic-8.pad
 \t (00:00:00) 
-\d (00:00:02) QtSignal GuidedTabsParent NewPads currentRowChanged 1
-\d (00:00:02) QtSignal GuidedTabsParent NewPads itemSelectionChanged Square
-\d (00:00:02) QtSignal GuidedTabsParent NewPads itemClicked Square
-\d (00:00:03) QtFillin Yes
-\d (00:00:05) QtSignal GuidedTabsParent GuidedStartTab keyPressEvent 16777251 134217728 false 1
-\d (00:00:07) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
-\d (00:00:08) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
-\d (00:00:08) QtSignal 1
-\d (00:00:22) QtSignal GuidedDesignLayersTab PadWidth editingFinished "5.0000"
-\d (00:00:26) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
-\d (00:00:27) QtSignal GuidedMaskLayersTab LayersTable cellClicked 0 "Regular Pad" 0 1
-\d (00:00:29) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0000"
-\d (00:00:36) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0600"
-\d (00:00:37) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
-\d (00:00:37) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 "Regular Pad" 2 1
-\d (00:00:40) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0000"
-\d (00:00:42) QtSignal MainWindow Save triggered
-\d (00:00:43) QtSignal MainWindow Exit triggered
-\t (00:00:43)     Journal end - Fri Apr 25 15:00:44 2025
+\d (00:00:05) QtSignal MainWindow Exit triggered
+\t (00:00:05)     Journal end - Sat May 10 04:28:26 2025
diff --git a/chip/padstack_editor.jrl,1 b/chip/padstack_editor.jrl,1
index 37155d1..1304389 100644
--- a/chip/padstack_editor.jrl,1
+++ b/chip/padstack_editor.jrl,1
@@ -1,21 +1,24 @@
-\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
-\t (00:00:00)     Journal start - Thu Apr 24 23:36:01 2025
-\t (00:00:00)         Host=XEROLYSKINNER User=Xeroly Pid=13068 CPUs=16
-\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\chip\tqfp-48-ep.pad
-\t (00:00:00) 
-\d (00:00:03) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
-\d (00:00:11) QtSignal GuidedDesignLayersTab PadHeight editingFinished "0.2600"
-\d (00:00:11) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777220 0 false 1 "
"
-\d (00:00:13) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
-\d (00:00:14) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
-\d (00:00:18) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
-\d (00:00:28) QtSignal GuidedMaskLayersTab PadHeight editingFinished "0.2800"
-\d (00:00:28) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
-\d (00:00:30) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
-\d (00:00:32) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 "Regular Pad" 2 1
-\d (00:00:33) QtSignal GuidedMaskLayersTab PadHeight editingFinished "0.2600"
-\d (00:00:33) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
-\d (00:00:36) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
-\d (00:00:39) QtSignal MainWindow Save triggered
-\d (00:00:41) QtSignal MainWindow Exit triggered
-\t (00:00:41)     Journal end - Thu Apr 24 23:36:43 2025
+\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
+\t (00:00:00)     Journal start - Fri Apr 25 15:00:00 2025
+\t (00:00:00)         Host=XEROLYSKINNER User=Xeroly Pid=24896 CPUs=16
+\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\chip\tqfp-48-ep-gnd.pad
+\t (00:00:00) 
+\d (00:00:02) QtSignal GuidedTabsParent NewPads currentRowChanged 1
+\d (00:00:02) QtSignal GuidedTabsParent NewPads itemSelectionChanged Square
+\d (00:00:02) QtSignal GuidedTabsParent NewPads itemClicked Square
+\d (00:00:03) QtFillin Yes
+\d (00:00:05) QtSignal GuidedTabsParent GuidedStartTab keyPressEvent 16777251 134217728 false 1
+\d (00:00:07) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
+\d (00:00:08) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
+\d (00:00:08) QtSignal 1
+\d (00:00:22) QtSignal GuidedDesignLayersTab PadWidth editingFinished "5.0000"
+\d (00:00:26) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
+\d (00:00:27) QtSignal GuidedMaskLayersTab LayersTable cellClicked 0 "Regular Pad" 0 1
+\d (00:00:29) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0000"
+\d (00:00:36) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0600"
+\d (00:00:37) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
+\d (00:00:37) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 "Regular Pad" 2 1
+\d (00:00:40) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0000"
+\d (00:00:42) QtSignal MainWindow Save triggered
+\d (00:00:43) QtSignal MainWindow Exit triggered
+\t (00:00:43)     Journal end - Fri Apr 25 15:00:44 2025
diff --git a/chip/param_read.log b/chip/param_read.log
index 74f0fb8..99d925b 100644
--- a/chip/param_read.log
+++ b/chip/param_read.log
@@ -2,15 +2,15 @@
 (                                                                     )
 (    Parameter File READ                                              )
 (                                                                     )
-(    Drawing          : tqfp-48-ep.dra                                )
+(    Drawing          : wsoic-8.dra                                   )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Thu Apr 24 23:38:15 2025                      )
+(    Date/Time        : Sat May 10 04:32:23 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
 
-	Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
-	Layout Name   : D:/Workspace/GitHub/pcb_lib/chip/tqfp-48-ep.dra
+	Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
+	Layout Name   : D:/workspace/GitHub/pcb_lib/chip/wsoic-8.dra
 
 Reading...parameter_header:
 Reading...db_common_type:
diff --git a/chip/param_read.log,1 b/chip/param_read.log,1
index 0577457..f8ba257 100644
--- a/chip/param_read.log,1
+++ b/chip/param_read.log,1
@@ -2,15 +2,15 @@
 (                                                                     )
 (    Parameter File READ                                              )
 (                                                                     )
-(    Drawing          : ssop-4.dra                                    )
+(    Drawing          : htssop-56.dra                                 )
 (    Software Version : 17.4S035                                      )
-(    Date/Time        : Sat Aug  3 22:01:23 2024                      )
+(    Date/Time        : Wed Aug  7 01:10:16 2024                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
 
 	Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
-	Layout Name   : D:/workspace/GitHub/pcb_lib/chip/ssop-4.dra
+	Layout Name   : D:/workspace/GitHub/pcb_lib/chip/htssop-56.dra
 
 Reading...parameter_header:
 Reading...db_common_type:
diff --git a/chip/param_read.log,2 b/chip/param_read.log,2
index f8ba257..8b6c3e0 100644
--- a/chip/param_read.log,2
+++ b/chip/param_read.log,2
@@ -2,15 +2,15 @@
 (                                                                     )
 (    Parameter File READ                                              )
 (                                                                     )
-(    Drawing          : htssop-56.dra                                 )
-(    Software Version : 17.4S035                                      )
-(    Date/Time        : Wed Aug  7 01:10:16 2024                      )
+(    Drawing          : wsop-16.dra                                   )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Wed Apr 23 17:01:05 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
 
-	Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
-	Layout Name   : D:/workspace/GitHub/pcb_lib/chip/htssop-56.dra
+	Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
+	Layout Name   : D:/Workspace/GitHub/pcb_lib/chip/wsop-16.dra
 
 Reading...parameter_header:
 Reading...db_common_type:
diff --git a/chip/param_read.log,3 b/chip/param_read.log,3
index 8b6c3e0..74f0fb8 100644
--- a/chip/param_read.log,3
+++ b/chip/param_read.log,3
@@ -2,15 +2,15 @@
 (                                                                     )
 (    Parameter File READ                                              )
 (                                                                     )
-(    Drawing          : wsop-16.dra                                   )
+(    Drawing          : tqfp-48-ep.dra                                )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Wed Apr 23 17:01:05 2025                      )
+(    Date/Time        : Thu Apr 24 23:38:15 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
 
 	Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
-	Layout Name   : D:/Workspace/GitHub/pcb_lib/chip/wsop-16.dra
+	Layout Name   : D:/Workspace/GitHub/pcb_lib/chip/tqfp-48-ep.dra
 
 Reading...parameter_header:
 Reading...db_common_type:
diff --git a/chip/stepFacetFiles4Map/stepFileInfo.txt b/chip/stepFacetFiles4Map/stepFileInfo.txt
index 0ae35f8..29166e2 100644
--- a/chip/stepFacetFiles4Map/stepFileInfo.txt
+++ b/chip/stepFacetFiles4Map/stepFileInfo.txt
@@ -9,6 +9,7 @@ wsop_16.step ! 827104 ! 1745399292
 ssop-16.step ! 873879 ! 1745399033
 tqfp-48.STEP ! 166679 ! 1745422272
 D8-L.step ! 282667 ! 1568096060
+wsop-16.step ! 584105 ! 1746823035
 SOP-16.STEP ! 3778717 ! 1722501952
 DIP_2x5.step ! 720870 ! 1710578258
 SSOP-8.step ! 755497 ! 1712718221
diff --git a/chip/stepFacetFiles4Map/stepFileInfo.txt,1 b/chip/stepFacetFiles4Map/stepFileInfo.txt,1
index 8aa0b6c..df2ca29 100644
--- a/chip/stepFacetFiles4Map/stepFileInfo.txt,1
+++ b/chip/stepFacetFiles4Map/stepFileInfo.txt,1
@@ -9,6 +9,7 @@ wsop_16.step ! 827104 ! 1745399292
 ssop-16.step ! 873879 ! 1745399033
 tqfp-48.STEP ! 166679 ! 1745422272
 D8-L.step ! 282667 ! 1568096060
+wsop-16.step ! 584105 ! 1746823035
 SOP-16.STEP ! 3778717 ! 1722501952
 DIP_2x5.step ! 720870 ! 1710578258
 SSOP-8.step ! 755497 ! 1712718221
diff --git a/chip/stepFacetFiles4Map/wsop-16.xml b/chip/stepFacetFiles4Map/wsop-16.xml
new file mode 100644
index 0000000..b15e480
--- /dev/null
+++ b/chip/stepFacetFiles4Map/wsop-16.xml
@@ -0,0 +1,17160 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<step-assembly root="id1476">
+<product id="id1476" name="58CCD729-C65B-417F-A7FE-7FC15234B269" shape="id6283"/>
+<shape id="id6283" unit="mm 0.001000" shell="id3126 id5447 id3097 id2936 id167 id2821 id414 id2813 id2868"/>
+<shell id="id5447" color="cad1ee">
+    <verts>
+        <v p="-5.7499999999999947 -2.1549999999999998 -0.40000000000000024"/>
+        <v p="-5.7499999999999947 -1.655 -0.40000000000000024"/>
+        <v p="-5.0491925493908685 -1.6549999999999994 -0.40000000000000019"/>
+        <v p="-5.0491925493908703 -2.1549999999999989 -0.40000000000000008"/>
+        <v p="-5.7499999999999947 -2.1549999999999998 -0.14999999999999997"/>
+        <v p="-5.7499999999999947 -1.655 -0.14999999999999997"/>
+        <v p="-5.0491925493908703 -2.1549999999999989 -0.15000000000000008"/>
+        <v p="-5.0491925493908703 -1.6549999999999994 -0.15000000000000008"/>
+        <v p="-4.8879063587417075 -2.1549999999999989 -0.042909975010172796"/>
+        <v p="-4.8879063587417075 -1.6549999999999994 -0.042909975010172796"/>
+        <v p="-4.4167364639926268 -2.1549999999999985 1.0761185250188923"/>
+        <v p="-4.4167364639926268 -1.6549999999999987 1.0761185250188923"/>
+        <v p="-4.1172049670727535 -2.1549999999999985 1.2749999999999999"/>
+        <v p="-4.1172049670727535 -1.6549999999999987 1.2749999999999999"/>
+        <v p="-3.7499999999999942 -2.154999999999998 1.2750000000000001"/>
+        <v p="-3.7499999999999942 -1.6549999999999983 1.2750000000000001"/>
+        <v p="-3.7499999999999942 -2.154999999999998 1.0249999999999999"/>
+        <v p="-3.7499999999999942 -1.6549999999999983 1.0249999999999999"/>
+        <v p="-4.1172049670727553 -2.154999999999998 1.0249999999999999"/>
+        <v p="-4.1172049670727553 -1.6549999999999985 1.0249999999999999"/>
+        <v p="-4.186327620208111 -2.1549999999999985 0.97910427500435881"/>
+        <v p="-4.186327620208111 -1.6549999999999989 0.97910427500435881"/>
+        <v p="-4.6574975149571909 -2.1549999999999985 -0.13992422502470495"/>
+        <v p="-4.6574975149571909 -1.6549999999999985 -0.13992422502470492"/>
+        <v p="-5.574798137347714 -2.1549999999999998 -0.40000000000000019"/>
+        <v p="-5.3995962746954325 -2.1549999999999994 -0.40000000000000013"/>
+        <v p="-5.2243944120431518 -2.1549999999999989 -0.40000000000000013"/>
+        <v p="-5.7499999999999947 -1.7799999999999998 -0.40000000000000024"/>
+        <v p="-5.7499999999999947 -1.9049999999999998 -0.40000000000000024"/>
+        <v p="-5.7499999999999947 -2.0299999999999998 -0.40000000000000024"/>
+        <v p="-5.22439441204315 -1.6549999999999996 -0.40000000000000024"/>
+        <v p="-5.3995962746954316 -1.6549999999999998 -0.40000000000000024"/>
+        <v p="-5.5747981373477131 -1.6549999999999998 -0.40000000000000019"/>
+        <v p="-5.0491925493908685 -1.7799999999999994 -0.40000000000000019"/>
+        <v p="-5.0491925493908694 -1.9049999999999991 -0.40000000000000013"/>
+        <v p="-5.0491925493908703 -2.0299999999999989 -0.40000000000000008"/>
+        <v p="-5.7499999999999947 -2.1549999999999998 -0.21250000000000002"/>
+        <v p="-5.7499999999999947 -2.1549999999999998 -0.27500000000000013"/>
+        <v p="-5.7499999999999947 -2.1549999999999998 -0.33750000000000013"/>
+        <v p="-5.7499999999999947 -1.7799999999999998 -0.14999999999999997"/>
+        <v p="-5.7499999999999947 -1.9049999999999998 -0.14999999999999997"/>
+        <v p="-5.7499999999999947 -2.0299999999999998 -0.14999999999999997"/>
+        <v p="-5.7499999999999947 -1.655 -0.21250000000000002"/>
+        <v p="-5.7499999999999947 -1.655 -0.27500000000000013"/>
+        <v p="-5.7499999999999947 -1.655 -0.33750000000000013"/>
+        <v p="-5.2243944120431518 -2.1549999999999989 -0.15000000000000005"/>
+        <v p="-5.3995962746954325 -2.1549999999999994 -0.15000000000000002"/>
+        <v p="-5.574798137347714 -2.1549999999999998 -0.14999999999999999"/>
+        <v p="-5.0491925493908703 -1.7799999999999994 -0.15000000000000008"/>
+        <v p="-5.0491925493908703 -1.9049999999999991 -0.15000000000000008"/>
+        <v p="-5.0491925493908703 -2.0299999999999989 -0.15000000000000008"/>
+        <v p="-5.574798137347714 -1.6549999999999998 -0.14999999999999999"/>
+        <v p="-5.3995962746954325 -1.6549999999999998 -0.15000000000000002"/>
+        <v p="-5.2243944120431518 -1.6549999999999996 -0.15000000000000005"/>
+        <v p="-4.9122438652058484 -2.1549999999999994 -0.083949795318724305"/>
+        <v p="-4.9497540552611135 -2.1549999999999989 -0.11900342317183565"/>
+        <v p="-4.9974420607330305 -2.1549999999999994 -0.14217322430244378"/>
+        <v p="-4.8879063587417075 -1.7799999999999994 -0.042909975010172796"/>
+        <v p="-4.8879063587417075 -1.9049999999999991 -0.042909975010172796"/>
+        <v p="-4.8879063587417075 -2.0299999999999989 -0.042909975010172796"/>
+        <v p="-5.0019244594578298 -1.6549999999999991 -0.14349548265185677"/>
+        <v p="-4.9550617041770213 -1.6549999999999991 -0.12252757023460649"/>
+        <v p="-4.9152019314779496 -1.6549999999999989 -0.087567820940597632"/>
+        <v p="-4.5345289376798963 -2.1549999999999985 0.79636140001162592"/>
+        <v p="-4.6523214113671667 -2.1549999999999985 0.51660427500435979"/>
+        <v p="-4.7701138850544371 -2.1549999999999985 0.23684714999709347"/>
+        <v p="-4.4167364639926268 -1.7799999999999987 1.0761185250188923"/>
+        <v p="-4.4167364639926268 -1.9049999999999985 1.0761185250188923"/>
+        <v p="-4.4167364639926268 -2.0299999999999985 1.0761185250188923"/>
+        <v p="-4.7701138850544371 -1.6549999999999991 0.23684714999709347"/>
+        <v p="-4.6523214113671667 -1.6549999999999989 0.51660427500435979"/>
+        <v p="-4.5345289376798963 -1.6549999999999989 0.79636140001162592"/>
+        <v p="-4.2049885626623391 -2.1549999999999985 1.2629201820678304"/>
+        <v p="-4.2920193938978324 -2.154999999999998 1.2239797732932478"/>
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diff --git a/chip/wsoic-8.dra b/chip/wsoic-8.dra
new file mode 100644
index 0000000..37db56a
Binary files /dev/null and b/chip/wsoic-8.dra differ
diff --git a/machine/m3x0_5.log,1 b/chip/wsoic-8.log
similarity index 62%
rename from machine/m3x0_5.log,1
rename to chip/wsoic-8.log
index 1864e50..615efb1 100644
--- a/machine/m3x0_5.log,1
+++ b/chip/wsoic-8.log
@@ -2,18 +2,18 @@
 (                                                                     )
 (    CREATE SYMBOL                                                    )
 (                                                                     )
-(    Drawing          : m3x0_5.dra                                    )
-(    Software Version : 17.4S035                                      )
-(    Date/Time        : Fri Aug  2 05:25:21 2024                      )
+(    Drawing          : wsoic-8.dra                                   )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sat May 10 04:45:31 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
 
 Create Symbol of type: PACKAGE
-    Directory = D:/¹¤×÷¿â/GitHub/pcb_lib/machine
-    Name      = m3x0_5.psm
-    User      = XerolySkinner
-    Machine   = LAPTOP-XEROLYSK
+    Directory = D:/workspace/GitHub/pcb_lib/chip
+    Name      = wsoic-8.psm
+    User      = Xeroly
+    Machine   = XEROLYSKINNER
 
 
 Create symbol started.
diff --git a/machine/m3x0_5.log,2 b/chip/wsoic-8.log,1
similarity index 62%
rename from machine/m3x0_5.log,2
rename to chip/wsoic-8.log,1
index 2e147ec..355a3e8 100644
--- a/machine/m3x0_5.log,2
+++ b/chip/wsoic-8.log,1
@@ -2,18 +2,18 @@
 (                                                                     )
 (    CREATE SYMBOL                                                    )
 (                                                                     )
-(    Drawing          : m3x0_5.dra                                    )
-(    Software Version : 17.4S035                                      )
-(    Date/Time        : Fri Aug  2 06:03:48 2024                      )
+(    Drawing          : wsoic-8.dra                                   )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sat May 10 04:34:55 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
 
 Create Symbol of type: PACKAGE
-    Directory = D:/¹¤×÷¿â/GitHub/pcb_lib/machine
-    Name      = m3x0_5.psm
-    User      = XerolySkinner
-    Machine   = LAPTOP-XEROLYSK
+    Directory = D:/workspace/GitHub/pcb_lib/chip
+    Name      = wsoic-8.psm
+    User      = Xeroly
+    Machine   = XEROLYSKINNER
 
 
 Create symbol started.
diff --git a/machine/m3x0_5.log,3 b/chip/wsoic-8.log,2
similarity index 61%
rename from machine/m3x0_5.log,3
rename to chip/wsoic-8.log,2
index 20c0fb9..353fa70 100644
--- a/machine/m3x0_5.log,3
+++ b/chip/wsoic-8.log,2
@@ -2,18 +2,18 @@
 (                                                                     )
 (    CREATE SYMBOL                                                    )
 (                                                                     )
-(    Drawing          : m3x0_5.dra                                    )
-(    Software Version : 17.4S035                                      )
-(    Date/Time        : Fri Aug  2 06:19:52 2024                      )
+(    Drawing          : wsoic-8.dra                                   )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sat May 10 04:35:43 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
 
 Create Symbol of type: PACKAGE
-    Directory = D:/workspace/GitHub/pcb_lib/machine
-    Name      = m3x0_5.psm
-    User      = XerolySkinner
-    Machine   = LAPTOP-XEROLYSK
+    Directory = D:/workspace/GitHub/pcb_lib/chip
+    Name      = wsoic-8.psm
+    User      = Xeroly
+    Machine   = XEROLYSKINNER
 
 
 Create symbol started.
diff --git a/chip/wsoic-8.log,3 b/chip/wsoic-8.log,3
new file mode 100644
index 0000000..97a1f4f
--- /dev/null
+++ b/chip/wsoic-8.log,3
@@ -0,0 +1,23 @@
+(---------------------------------------------------------------------)
+(                                                                     )
+(    CREATE SYMBOL                                                    )
+(                                                                     )
+(    Drawing          : wsoic-8.dra                                   )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sat May 10 04:45:17 2025                      )
+(                                                                     )
+(---------------------------------------------------------------------)
+
+
+Create Symbol of type: PACKAGE
+    Directory = D:/workspace/GitHub/pcb_lib/chip
+    Name      = wsoic-8.psm
+    User      = Xeroly
+    Machine   = XEROLYSKINNER
+
+
+Create symbol started.
+ 
+
+Create symbol completed.
+
diff --git a/chip/wsoic-8.pad b/chip/wsoic-8.pad
new file mode 100644
index 0000000..6199580
Binary files /dev/null and b/chip/wsoic-8.pad differ
diff --git a/chip/wsoic-8.psm b/chip/wsoic-8.psm
new file mode 100644
index 0000000..d7fa2a0
Binary files /dev/null and b/chip/wsoic-8.psm differ
diff --git a/chip/wsop-16.dra b/chip/wsop-16.dra
index 0559a46..053b5de 100644
Binary files a/chip/wsop-16.dra and b/chip/wsop-16.dra differ
diff --git a/chip/wsop-16.log b/chip/wsop-16.log
index 7834002..be0cd4c 100644
--- a/chip/wsop-16.log
+++ b/chip/wsop-16.log
@@ -4,7 +4,7 @@
 (                                                                     )
 (    Drawing          : wsop-16.dra                                   )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Wed Apr 23 17:37:56 2025                      )
+(    Date/Time        : Sat May  3 00:59:54 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/chip/wsop-16.log,1 b/chip/wsop-16.log,1
index 8eff4f9..33e41ae 100644
--- a/chip/wsop-16.log,1
+++ b/chip/wsop-16.log,1
@@ -4,7 +4,7 @@
 (                                                                     )
 (    Drawing          : wsop-16.dra                                   )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Wed Apr 23 17:18:34 2025                      )
+(    Date/Time        : Wed Apr 23 17:18:43 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/chip/wsop-16.log,2 b/chip/wsop-16.log,2
index 33e41ae..a25ea4e 100644
--- a/chip/wsop-16.log,2
+++ b/chip/wsop-16.log,2
@@ -4,7 +4,7 @@
 (                                                                     )
 (    Drawing          : wsop-16.dra                                   )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Wed Apr 23 17:18:43 2025                      )
+(    Date/Time        : Wed Apr 23 17:37:39 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/chip/wsop-16.log,3 b/chip/wsop-16.log,3
index a25ea4e..7834002 100644
--- a/chip/wsop-16.log,3
+++ b/chip/wsop-16.log,3
@@ -4,7 +4,7 @@
 (                                                                     )
 (    Drawing          : wsop-16.dra                                   )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Wed Apr 23 17:37:39 2025                      )
+(    Date/Time        : Wed Apr 23 17:37:56 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/chip/wsop-16.psm b/chip/wsop-16.psm
index ee33b10..84368e2 100644
Binary files a/chip/wsop-16.psm and b/chip/wsop-16.psm differ
diff --git a/machine/allegro.jrl b/machine/allegro.jrl
index 995afe4..4fda5a7 100644
--- a/machine/allegro.jrl
+++ b/machine/allegro.jrl
@@ -1,29 +1,28 @@
-\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
-\t (00:00:03)     Journal start - Fri Aug  2 06:23:15 2024
-\t (00:00:03)         Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=25644 CPUs=12
-\t (00:00:03) CmdLine= D:\SOFTWARE\Cadence\SPB_17.4\tools\bin\allegro.exe
-\t (00:00:03) 
-   (00:00:03) Loading axlcore.cxt 
-\t (00:00:05) Opening existing design...
-\i (00:00:05) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "m3x0_5"
-\d (00:00:05) Design opened: D:/workspace/GitHub/pcb_lib/machine/m3x0_5.dra
-\i (00:00:06) trapsize 671
-\i (00:00:06) trapsize 688
-\i (00:00:06) trapsize 671
-\i (00:00:06) trapsize 588
-\i (00:00:06) trapsize 604
-\i (00:00:06) trapsize 621
-\i (00:00:06) trapsize 638
-\i (00:00:15) open 
-\i (00:00:25) fillin "D:/workspace/Cadence/cardrive/allegro/cardrive.brd"
-\i (00:00:25) cd "D:/workspace/Cadence/cardrive/allegro"
-\t (00:00:26) Opening existing design...
-\t (00:00:26) Grids are drawn 0.8000, 0.8000 apart for enhanced viewing.
-\i (00:00:26) trapsize 5428
-\i (00:00:26) trapsize 5562
-\t (00:00:26) Grids are drawn 409.6000, 409.6000 apart for enhanced viewing.
-\t (00:00:26) Grids are drawn 0.8000, 0.8000 apart for enhanced viewing.
-\i (00:00:26) trapsize 6033
-\i (00:00:26) trapsize 6033
-\t (00:00:26) > Sending response DoneOpenBoard
-\t (00:00:26)     Journal end - Fri Aug  2 06:23:39 2024
+\t (00:00:02) allegro 23.1 P001 Windows SPB 64-bit Edition
+\t (00:00:02)     Journal start - Sat May 10 12:52:41 2025
+\t (00:00:02)         Host=XEROLYSKINNER User=Xeroly Pid=35720 CPUs=16
+\t (00:00:02) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\machine\m3x0_5.dra
+\t (00:00:02) 
+   (00:00:02) Loading axlcore.cxt 
+\t (00:00:02) Opening existing design...
+\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "m3x0_5"
+\d (00:00:02) Design opened: D:/Workspace/GitHub/pcb_lib/machine/m3x0_5.dra
+\i (00:00:02) trapsize 722
+\i (00:00:02) trapsize 743
+\i (00:00:02) trapsize 722
+\i (00:00:02) trapsize 769
+\i (00:00:02) trapsize 816
+\i (00:00:02) trapsize 550
+\i (00:00:10) step pkg map 
+\i (00:00:11) fillin yes 
+\i (00:01:51) setwindow form.pkgmap3d
+\i (00:01:51) FORM pkgmap3d offset_z 10.0000 
+\i (00:01:55) FORM pkgmap3d offset_z 5.0000 
+\i (00:02:00) FORM pkgmap3d save_current  
+\i (00:02:02) FORM pkgmap3d done  
+\i (00:02:03) setwindow pcb
+\i (00:02:03) exit 
+\e (00:02:03) Do you want to save the changes you made to m3x0_5.dra?
+\i (00:02:03) fillin yes 
+\t (00:02:04) Symbol 'm3x0_5.psm' created.
+\t (00:02:04)     Journal end - Sat May 10 12:54:43 2025
diff --git a/machine/allegro.jrl,1 b/machine/allegro.jrl,1
index c13a9e7..e69de29 100644
--- a/machine/allegro.jrl,1
+++ b/machine/allegro.jrl,1
@@ -1,44 +0,0 @@
-\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
-\t (00:00:03)     Journal start - Fri Aug  2 06:19:47 2024
-\t (00:00:03)         Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=24944 CPUs=12
-\t (00:00:03) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\machine\m3x0_5.dra
-\t (00:00:03) 
-   (00:00:03) Loading axlcore.cxt 
-\t (00:00:05) Opening existing design...
-\i (00:00:06) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "m3x0_5"
-\d (00:00:06) Design opened: D:/workspace/GitHub/pcb_lib/machine/m3x0_5.dra
-\i (00:00:06) trapsize 653
-\i (00:00:06) trapsize 671
-\i (00:00:06) trapsize 653
-\i (00:00:06) trapsize 573
-\i (00:00:06) trapsize 589
-\i (00:00:06) trapsize 605
-\i (00:00:06) trapsize 621
-\i (00:00:07) save 
-\i (00:00:08) fillin yes 
-\t (00:00:08) Symbol 'm3x0_5.psm' created.
-\i (00:00:10) step pkg map 
-\i (00:00:11) fillin yes 
-\i (00:00:16) setwindow form.pkgmap3d
-\i (00:00:16) FORM pkgmap3d stplist M3x18.STEP 
-\i (00:02:49) setwindow pcb
-\i (00:02:49) step pkg map 
-\i (00:02:53) fillin no 
-\i (00:02:57) setwindow form.pkgmap3d
-\i (00:02:57) FORM pkgmap3d rotation_y 90 
-\i (00:02:59) FORM pkgmap3d rotation_y 0 
-\i (00:03:00) FORM pkgmap3d rotation_x 90 
-\i (00:03:02) FORM pkgmap3d hide_board YES 
-\i (00:03:06) FORM pkgmap3d view_orientation Top 
-\i (00:03:08) FORM pkgmap3d view_orientation Left 
-\i (00:03:12) FORM pkgmap3d offset_z 10 
-\i (00:03:14) FORM pkgmap3d offset_z 20 
-\i (00:03:17) FORM pkgmap3d offset_z 15 
-\i (00:03:21) FORM pkgmap3d save_current  
-\i (00:03:22) FORM pkgmap3d done  
-\i (00:03:23) setwindow pcb
-\i (00:03:23) save 
-\i (00:03:24) fillin yes 
-\t (00:03:24) Symbol 'm3x0_5.psm' created.
-\i (00:03:25) exit 
-\t (00:03:25)     Journal end - Fri Aug  2 06:23:09 2024
diff --git a/machine/downrev.log b/machine/downrev.log
index 44f3cc3..3c174e9 100644
--- a/machine/downrev.log
+++ b/machine/downrev.log
@@ -3,8 +3,8 @@
 (    Downrev Design                                                   )
 (                                                                     )
 (    Drawing          : m3x0_5.dra                                    )
-(    Software Version : 17.4S035                                      )
-(    Date/Time        : Fri Aug  2 06:23:08 2024                      )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sat May 10 12:54:43 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/machine/downrev.log,1 b/machine/downrev.log,1
index cb09f0c..3c174e9 100644
--- a/machine/downrev.log,1
+++ b/machine/downrev.log,1
@@ -3,8 +3,8 @@
 (    Downrev Design                                                   )
 (                                                                     )
 (    Drawing          : m3x0_5.dra                                    )
-(    Software Version : 17.4S035                                      )
-(    Date/Time        : Fri Aug  2 06:19:52 2024                      )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sat May 10 12:54:43 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/machine/downrev.log,2 b/machine/downrev.log,2
index 44f3cc3..3c174e9 100644
--- a/machine/downrev.log,2
+++ b/machine/downrev.log,2
@@ -3,8 +3,8 @@
 (    Downrev Design                                                   )
 (                                                                     )
 (    Drawing          : m3x0_5.dra                                    )
-(    Software Version : 17.4S035                                      )
-(    Date/Time        : Fri Aug  2 06:23:08 2024                      )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sat May 10 12:54:43 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/machine/downrev.log,3 b/machine/downrev.log,3
deleted file mode 100644
index 44f3cc3..0000000
--- a/machine/downrev.log,3
+++ /dev/null
@@ -1,14 +0,0 @@
-(---------------------------------------------------------------------)
-(                                                                     )
-(    Downrev Design                                                   )
-(                                                                     )
-(    Drawing          : m3x0_5.dra                                    )
-(    Software Version : 17.4S035                                      )
-(    Date/Time        : Fri Aug  2 06:23:08 2024                      )
-(                                                                     )
-(---------------------------------------------------------------------)
-
-
-
-Changes made to design for 17.2 compatibility.
-
diff --git a/machine/m3x0_5.dra b/machine/m3x0_5.dra
index 131a517..b65c0b6 100644
Binary files a/machine/m3x0_5.dra and b/machine/m3x0_5.dra differ
diff --git a/machine/m3x0_5.log b/machine/m3x0_5.log
index 9fefb5b..7df1a84 100644
--- a/machine/m3x0_5.log
+++ b/machine/m3x0_5.log
@@ -3,17 +3,17 @@
 (    CREATE SYMBOL                                                    )
 (                                                                     )
 (    Drawing          : m3x0_5.dra                                    )
-(    Software Version : 17.4S035                                      )
-(    Date/Time        : Fri Aug  2 06:23:08 2024                      )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sat May 10 12:54:43 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
 
 Create Symbol of type: PACKAGE
-    Directory = D:/workspace/GitHub/pcb_lib/machine
+    Directory = D:/Workspace/GitHub/pcb_lib/machine
     Name      = m3x0_5.psm
-    User      = XerolySkinner
-    Machine   = LAPTOP-XEROLYSK
+    User      = Xeroly
+    Machine   = XEROLYSKINNER
 
 
 Create symbol started.
diff --git a/machine/m3x0_5.psm b/machine/m3x0_5.psm
index e7e266a..5e4f2c9 100644
Binary files a/machine/m3x0_5.psm and b/machine/m3x0_5.psm differ
diff --git a/machine/stepFacetFiles4Map/stepFileInfo.txt b/machine/stepFacetFiles4Map/stepFileInfo.txt
index f973045..2a39ddc 100644
--- a/machine/stepFacetFiles4Map/stepFileInfo.txt
+++ b/machine/stepFacetFiles4Map/stepFileInfo.txt
@@ -1,6 +1,6 @@
 #STEP_FILE ! FILE_SIZE ! MOD_TIME
 
 P8.step ! 229628 ! 1568096060
-M3x18.STEP ! 717806 ! 1722547502
+M3x18.STEP ! 717806 ! 1724688650
 M3x8.step ! 440671 ! 1722533353
 LED_0603_G.STEP ! 178570 ! 1710578258
diff --git a/other/PCB1094M4.dra b/other/PCB1094M4.dra
index f94ad04..cb21ede 100644
Binary files a/other/PCB1094M4.dra and b/other/PCB1094M4.dra differ
diff --git a/other/USR-WIFI232-A2.dra b/other/USR-WIFI232-A2.dra
new file mode 100644
index 0000000..9dab833
Binary files /dev/null and b/other/USR-WIFI232-A2.dra differ
diff --git a/other/allegro.jrl b/other/allegro.jrl
index 12e90c3..e84e393 100644
--- a/other/allegro.jrl
+++ b/other/allegro.jrl
@@ -1,133 +1,29 @@
-\t (00:02:32) allegro 23.1 P001 Windows SPB 64-bit Edition
-\t (00:02:32)     Journal start - Sun Apr 27 22:55:41 2025
-\t (00:02:32)         Host=XEROLYSKINNER User=Xeroly Pid=2016 CPUs=16
-\t (00:02:32) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe -mpssession Xeroly -proj d:\workspace\cadence\cedarmotor\cedarmotor.opj d:/workspace/cadence/cedarmotor/allegro/cedarmotor.brd
-\t (00:02:32) 
-\t (00:02:32) Starting new design...
-\i (00:02:32) trapsize 14970
-\i (00:02:32) trapsize 15291
-\i (00:02:32) trapsize 14970
-\t (00:02:32) Grids are drawn 1300.4800, 1300.4800 apart for enhanced viewing.
-\i (00:02:32) trapsize 19763
-\i (00:02:32) trapsize 19763
-\i (00:02:32) trapsize 18903
-\i (00:02:35) param in 
-\i (00:02:37) setwindow form.parm_in
-\i (00:02:37) FORM parm_in browse  
-\i (00:02:39) fillin "D:/workspace/GitHub/pcb_lib/XerolySkinner.prm"
-\i (00:02:40) FORM parm_in execute  
-\t (00:02:40) Starting Importing parameter file...
-\w (00:02:40) WARNING(SPMHGE-269): param in had warnings, use Viewlog to review the log file.
-\t (00:02:40) Opening existing design...
-\t (00:02:40) Grids are drawn 2.5400, 2.5400 apart for enhanced viewing.
-\i (00:02:40) setwindow pcb
-\i (00:02:40) trapsize 18903
-\i (00:02:40) trapsize 19289
-\i (00:02:41) trapsize 18903
-\t (00:02:41) Grids are drawn 2.5400, 2.5400 apart for enhanced viewing.
-\i (00:02:41) trapsize 19477
-\i (00:02:42) setwindow text
-\i (00:02:42) close
-\i (00:02:43) setwindow form.parm_in
-\i (00:02:43) FORM parm_in cancel  
-\i (00:02:44) setwindow pcb
-\i (00:02:44) zoom in 1 
-\i (00:02:44) setwindow pcb
-\i (00:02:44) zoom in -9.2655 -6.9282
-\t (00:02:44) Grids are drawn 1.2700, 1.2700 apart for enhanced viewing.
-\i (00:02:44) trapsize 9738
-\i (00:02:45) zoom in 1 
-\i (00:02:45) setwindow pcb
-\i (00:02:45) zoom in 1.4468 -0.6956
-\i (00:02:45) trapsize 4869
-\i (00:02:47) add pin 
-\i (00:02:49) setwindow form.mini
-\i (00:02:49) FORM mini x_count 2 
-\i (00:02:55) FORM mini x_spacing 6.9000 
-\i (00:02:59) FORM mini next_pin_number 1 
-\i (00:02:59) FORM mini pad_browse  
-\i (00:03:21) fillin "Thr-2r3-3r0"
-\t (00:03:21) Using 'THR-2R3-3R0.pad'.
-\e (00:03:39) Command not found: X -3.45 0
-\i (00:03:46) setwindow pcb
-\i (00:03:46) pick -3.45 0 
-\t (00:03:46) last pick:  -3.4500 0.0000
-\t (00:03:46) Using 'THR-2R3-3R0.pad'.
-\i (00:03:48) prepopup -1.6694 6.2187
-\i (00:03:48) done 
-\t (00:03:48) Exiting from Add Pin.
-\i (00:03:49) zoom in 1 
-\i (00:03:49) setwindow pcb
-\i (00:03:49) zoom in -1.0851 1.2521
-\i (00:03:49) trapsize 2435
-\i (00:03:49) zoom in 1 
-\i (00:03:49) setwindow pcb
-\i (00:03:49) zoom in -1.0851 1.2522
-\i (00:03:49) trapsize 1217
-\i (00:04:00) shape add rect 
-\i (00:04:02) setwindow form.mini
-\i (00:04:02) FORM mini class 'PACKAGE GEOMETRY' 
-\i (00:04:04) FORM mini subclass PLACE_BOUND_TOP 
-\i (00:04:04) setwindow pcb
-\i (00:04:04) updateport CVPane
-\i (00:04:21) pick -3.95 3.95 
-\t (00:04:21) last pick:  -3.9500 3.9500
-\i (00:04:26) pick 3.95 -3.95 
-\t (00:04:26) last pick:  3.9500 -3.9500
-\i (00:04:27) prepopup -2.4485 7.5335
-\i (00:04:28) done 
-\i (00:04:29) add rect 
-\i (00:04:31) setwindow form.mini
-\i (00:04:31) FORM mini subclass ASSEMBLY_TOP 
-\i (00:04:31) setwindow pcb
-\i (00:04:31) updateport CVPane
-\i (00:04:35) pick -3.95 3.95 
-\t (00:04:35) last pick:  -3.9500 3.9500
-\i (00:04:39) pick 3.95 -3.95 
-\t (00:04:39) last pick:  3.9500 -3.9500
-\i (00:04:40) prepopup 8.8968 5.0989
-\i (00:04:41) done 
-\i (00:04:48) add rect 
-\i (00:04:51) shape add rect 
-\i (00:04:54) setwindow form.mini
-\i (00:04:54) FORM mini subclass SILKSCREEN_TOP 
-\i (00:04:54) setwindow pcb
-\i (00:04:54) updateport CVPane
-\i (00:05:00) pick -3.95 3.95 
-\t (00:05:00) last pick:  -3.9500 3.9500
-\i (00:05:05) pick 3.95 -3.95 
-\t (00:05:05) last pick:  3.9500 -3.9500
-\i (00:05:06) prepopup 6.1214 5.3423
-\i (00:05:07) done 
-\i (00:05:08) label refdes 
-\t (00:05:08) Pick text location.
-\i (00:05:11) setwindow form.mini
-\i (00:05:11) FORM mini text_name asm 
-\i (00:05:11) setwindow pcb
-\i (00:05:11) pick grid -0.2573 6.1457
-\t (00:05:11) last pick:  0.0000 5.0800
-\t (00:05:11) Enter text string.
-\i (00:05:14) setwindow pcb
-\i (00:05:14) pick 0.0000 5.0800
-\i (00:05:19) pick grid -2.5945 4.7337
-\t (00:05:19) last pick:  -2.5400 5.0800
-\t (00:05:19) Refdes of this subclass is already defined, change subclass.
-\i (00:05:23) setwindow form.mini
-\i (00:05:23) FORM mini subclass SILKSCREEN_TOP 
-\i (00:05:23) setwindow pcb
-\i (00:05:23) updateport CVPane
-\i (00:05:25) setwindow form.mini
-\i (00:05:25) FORM mini text_name ski 
-\i (00:05:26) setwindow pcb
-\i (00:05:26) pick grid -2.7406 4.9528
-\t (00:05:26) last pick:  -2.5400 5.0800
-\t (00:05:26) Enter text string.
-\i (00:05:28) setwindow pcb
-\i (00:05:28) pick -2.5400 5.0800
-\i (00:05:29) save 
-\t (00:05:29) Symbol 'pcb1094m4.psm' created.
-\i (00:05:31) save 
-\i (00:05:31) fillin yes 
-\t (00:05:32) Symbol 'pcb1094m4.psm' created.
-\i (00:05:33) exit 
-\t (00:05:33)     Journal end - Sun Apr 27 22:58:42 2025
+\t (00:00:02) allegro 23.1 P001 Windows SPB 64-bit Edition
+\t (00:00:02)     Journal start - Sat May 10 13:22:20 2025
+\t (00:00:02)         Host=XEROLYSKINNER User=Xeroly Pid=20404 CPUs=16
+\t (00:00:02) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe
+\t (00:00:02) 
+   (00:00:02) Loading axlcore.cxt 
+\t (00:00:04) Opening existing design...
+\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "rj45-8p8c"
+\d (00:00:04) Design opened: D:/Workspace/GitHub/pcb_lib/other/rj45-8p8c.dra
+\i (00:00:04) trapsize 2935
+\i (00:00:05) trapsize 3019
+\i (00:00:05) trapsize 2935
+\i (00:00:05) trapsize 3259
+\i (00:00:05) trapsize 3259
+\i (00:00:05) trapsize 2106
+\i (00:00:08) open 
+\i (00:00:17) fillin "D:/Workspace/Cadence/cedarmain/allegro/cedarmain.brd"
+\i (00:00:17) cd "D:/Workspace/Cadence/cedarmain/allegro"
+\t (00:00:17) Opening existing design...
+\t (00:00:18) Grids are drawn 0.0800, 0.0800 apart for enhanced viewing.
+\i (00:00:18) trapsize 951
+\i (00:00:18) trapsize 971
+\t (00:00:18) Grids are drawn 0.0800, 0.0800 apart for enhanced viewing.
+\i (00:00:18) trapsize 988
+\t (00:00:18) Grids are drawn 0.1600, 0.1600 apart for enhanced viewing.
+\i (00:00:18) trapsize 1013
+\i (00:00:18) trapsize 1013
+\t (00:00:18) > Sending response DoneOpenBoard
+\t (00:00:18)     Journal end - Sat May 10 13:22:37 2025
diff --git a/other/allegro.jrl,1 b/other/allegro.jrl,1
index ef3f0ea..b3bcdd3 100644
--- a/other/allegro.jrl,1
+++ b/other/allegro.jrl,1
@@ -1,193 +1,42 @@
-\t (00:02:25) allegro 23.1 P001 Windows SPB 64-bit Edition
-\t (00:02:25)     Journal start - Sun Apr 27 22:49:48 2025
-\t (00:02:25)         Host=XEROLYSKINNER User=Xeroly Pid=17144 CPUs=16
-\t (00:02:25) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe
-\t (00:02:25) 
-\t (00:02:25) Starting new design...
-\i (00:02:25) trapsize 14970
-\i (00:02:25) trapsize 15291
-\i (00:02:25) trapsize 14970
-\t (00:02:25) Grids are drawn 1300.4800, 1300.4800 apart for enhanced viewing.
-\i (00:02:25) trapsize 19763
-\i (00:02:25) trapsize 19763
-\i (00:02:26) trapsize 18903
-\i (00:02:29) param in 
-\i (00:02:31) setwindow form.parm_in
-\i (00:02:31) FORM parm_in browse  
-\i (00:02:34) fillin "D:/workspace/GitHub/pcb_lib/XerolySkinner.prm"
-\i (00:02:34) FORM parm_in execute  
-\t (00:02:34) Starting Importing parameter file...
-\w (00:02:35) WARNING(SPMHGE-269): param in had warnings, use Viewlog to review the log file.
-\t (00:02:35) Opening existing design...
-\t (00:02:35) Grids are drawn 2.5400, 2.5400 apart for enhanced viewing.
-\i (00:02:35) setwindow pcb
-\i (00:02:35) trapsize 18903
-\i (00:02:35) trapsize 19289
-\i (00:02:35) trapsize 18903
-\t (00:02:35) Grids are drawn 2.5400, 2.5400 apart for enhanced viewing.
-\i (00:02:35) trapsize 19477
-\i (00:02:36) setwindow text
-\i (00:02:36) close
-\i (00:02:37) setwindow form.parm_in
-\i (00:02:37) FORM parm_in cancel  
-\i (00:02:39) setwindow pcb
-\i (00:02:39) prmed 
-\i (00:02:44) setwindow form.prmedit
-\i (00:02:44) FORM prmedit design  
-\i (00:02:48) FORM prmedit done  
-\i (00:02:49) setwindow pcb
-\i (00:02:49) label refdes 
-\t (00:02:49) Pick text location.
-\i (00:02:51) add pin 
-\i (00:02:52) setwindow form.mini
-\i (00:02:52) FORM mini pad_name pcb-10b 
-\t (00:02:52) Using 'PCB-10B.pad'.
-\i (00:02:54) setwindow pcb
-\i (00:02:54) pick 0 0 
-\t (00:02:54) last pick:  0.0000 0.0000
-\t (00:02:54) Using 'PCB-10B.pad'.
-\i (00:02:55) prepopup 14.4964 -20.1725
-\i (00:02:55) done 
-\t (00:02:55) Exiting from Add Pin.
-\i (00:02:56) zoom in 1 
-\i (00:02:56) setwindow pcb
-\i (00:02:56) zoom in 1.2521 0.4730
-\i (00:02:56) trapsize 9738
-\i (00:02:56) zoom in 1 
-\i (00:02:56) setwindow pcb
-\i (00:02:56) zoom in 1.2521 0.4730
-\i (00:02:56) trapsize 4869
-\i (00:02:56) zoom in 1 
-\i (00:02:56) setwindow pcb
-\i (00:02:56) zoom in 1.2521 0.4730
-\i (00:02:56) trapsize 2435
-\i (00:02:58) undo 
-\i (00:02:58) trapsize 19477
-\i (00:02:59) add pin 
-\i (00:03:01) setwindow form.mini
-\i (00:03:01) FORM mini next_pin_number 1 
-\i (00:03:02) FORM mini pad_name pcb-10b 
-\t (00:03:02) Using 'PCB-10B.pad'.
-\e (00:03:04) Command not found: x0 0
-\i (00:03:06) setwindow pcb
-\i (00:03:06) pick 0 0 
-\t (00:03:06) last pick:  0.0000 0.0000
-\t (00:03:06) Using 'PCB-10B.pad'.
-\i (00:03:07) prepopup 16.4441 11.7696
-\i (00:03:08) done 
-\t (00:03:08) Exiting from Add Pin.
-\i (00:03:08) zoom in 1 
-\i (00:03:08) setwindow pcb
-\i (00:03:08) zoom in -2.6433 -4.2015
-\i (00:03:08) trapsize 9738
-\i (00:03:09) zoom in 1 
-\i (00:03:09) setwindow pcb
-\i (00:03:09) zoom in 1.0573 -2.2538
-\i (00:03:09) trapsize 4869
-\i (00:03:09) zoom in 1 
-\i (00:03:09) setwindow pcb
-\i (00:03:09) zoom in 1.0573 -2.2537
-\i (00:03:09) trapsize 2435
-\i (00:03:09) zoom in 1 
-\i (00:03:09) setwindow pcb
-\i (00:03:09) zoom in 1.0573 -2.2537
-\i (00:03:09) trapsize 1217
-\i (00:03:09) zoom in 1 
-\i (00:03:09) setwindow pcb
-\i (00:03:09) zoom in 1.0574 -2.2536
-\i (00:03:09) trapsize 609
-\i (00:03:10) zoom out 1 
-\i (00:03:10) setwindow pcb
-\i (00:03:10) zoom out 1.0574 -2.2536
-\i (00:03:10) trapsize 1217
-\i (00:03:10) zoom out 1 
-\i (00:03:10) setwindow pcb
-\i (00:03:10) zoom out 1.0574 -2.2535
-\i (00:03:10) trapsize 2435
-\i (00:03:10) zoom out 1 
-\i (00:03:10) setwindow pcb
-\i (00:03:10) zoom out 1.0572 -2.2536
-\i (00:03:10) trapsize 4869
-\i (00:03:10) zoom out 1 
-\i (00:03:10) setwindow pcb
-\i (00:03:10) zoom out 1.0573 -2.2535
-\i (00:03:10) trapsize 9738
-\i (00:03:11) zoom in 1 
-\i (00:03:11) setwindow pcb
-\i (00:03:11) zoom in 3.0050 1.0575
-\i (00:03:11) trapsize 4869
-\i (00:03:11) zoom in 1 
-\i (00:03:11) setwindow pcb
-\i (00:03:11) zoom in 3.0050 1.0575
-\i (00:03:11) trapsize 2435
-\i (00:03:13) label refdes 
-\t (00:03:13) Pick text location.
-\i (00:03:13) pick grid -2.6432 12.5976
-\t (00:03:13) last pick:  -2.5400 12.7000
-\t (00:03:13) Enter text string.
-\i (00:03:16) setwindow form.mini
-\i (00:03:16) FORM mini text_name asm 
-\i (00:03:19) setwindow pcb
-\i (00:03:19) pick -2.5400 12.7000
-\i (00:03:20) setwindow pcb
-\i (00:03:20) MOVE 
-\t (00:03:20) Select element(s) to move.
-\i (00:03:21) pick grid -1.5720 12.8897
-\t (00:03:21) last pick:  -2.5400 12.7000
-\t (00:03:21) last pick:  -2.5400 12.7000
-\t (00:03:21) Pick new location for the element(s).
-\i (00:03:22) pick grid 1.1061 8.7509
-\t (00:03:22) last pick:  0.0000 7.6200
-\i (00:03:24) label refdes 
-\t (00:03:24) Pick text location.
-\i (00:03:26) setwindow form.mini
-\i (00:03:26) FORM mini subclass SILKSCREEN_TOP 
-\i (00:03:26) setwindow pcb
-\i (00:03:26) updateport CVPane
-\i (00:03:27) setwindow form.mini
-\i (00:03:27) FORM mini text_name ski 
-\i (00:03:28) setwindow pcb
-\i (00:03:28) pick grid 3.3946 7.6310
-\t (00:03:28) last pick:  2.5400 7.6200
-\t (00:03:28) Enter text string.
-\i (00:03:31) setwindow pcb
-\i (00:03:31) pick 2.5400 7.6200
-\i (00:03:32) prepopup 7.6308 7.8744
-\i (00:03:33) done 
-\i (00:03:48) save 
-\t (00:03:49) Symbol 'pcb-10b.psm' created.
-\i (00:03:55) shape add rect 
-\i (00:03:58) setwindow form.mini
-\i (00:03:58) FORM mini subclass ASSEMBLY_TOP 
-\i (00:03:58) setwindow pcb
-\i (00:03:58) updateport CVPane
-\i (00:04:00) zoom in 1 
-\i (00:04:00) setwindow pcb
-\i (00:04:00) zoom in -6.1491 5.2937
-\i (00:04:00) trapsize 1217
-\i (00:04:02) define grid 
-\t (00:04:02) Spacing fields allow simple equations to aid calculations; prefix with =
-\i (00:04:03) setwindow form.grid
-\i (00:04:03) FORM grid non_etch non_etch_x_grids 0.1 
-\i (00:04:03) FORM grid non_etch non_etch_y_grids 0.1 
-\i (00:04:04) FORM grid done  
-\i (00:04:05) setwindow pcb
-\i (00:04:05) zoom in 1 
-\i (00:04:05) setwindow pcb
-\i (00:04:05) zoom in -5.4187 4.8555
-\i (00:04:05) trapsize 609
-\i (00:04:07) pick grid -5.4673 5.0746
-\t (00:04:07) last pick:  -5.5000 5.1000
-\i (00:04:08) zoom out 1 
-\i (00:04:08) setwindow pcb
-\i (00:04:08) zoom out -4.2866 5.0016
-\i (00:04:08) trapsize 1217
-\i (00:04:12) pick grid 5.5493 -5.1021
-\t (00:04:12) last pick:  5.5000 -5.1000
-\i (00:04:12) prepopup 7.2779 -0.4763
-\i (00:04:13) done 
-\i (00:04:13) save 
-\i (00:04:14) fillin yes 
-\t (00:04:14) Symbol 'pcb-10b.psm' created.
-\i (00:04:15) exit 
-\t (00:04:15)     Journal end - Sun Apr 27 22:51:38 2025
+\t (00:00:02) allegro 23.1 P001 Windows SPB 64-bit Edition
+\t (00:00:02)     Journal start - Sat May 10 13:21:47 2025
+\t (00:00:02)         Host=XEROLYSKINNER User=Xeroly Pid=45400 CPUs=16
+\t (00:00:02) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\other\rj45-8p8c.dra
+\t (00:00:02) 
+   (00:00:02) Loading axlcore.cxt 
+\t (00:00:02) Opening existing design...
+\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "rj45-8p8c"
+\d (00:00:02) Design opened: D:/Workspace/GitHub/pcb_lib/other/rj45-8p8c.dra
+\i (00:00:02) trapsize 2935
+\i (00:00:02) trapsize 3019
+\i (00:00:02) trapsize 2935
+\i (00:00:02) trapsize 3259
+\i (00:00:02) trapsize 3259
+\i (00:00:02) trapsize 2106
+\i (00:00:04) color192 
+\i (00:00:06) QtSignal CVDLayerContainer CVDVisibilityOff clicked
+\i (00:00:07) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Bottom" 1
+\i (00:00:07) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 3 0
+\i (00:00:10) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 1
+\i (00:00:10) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
+\i (00:00:11) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 0
+\i (00:00:11) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
+\i (00:00:12) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Bottom" 0
+\i (00:00:12) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 3 0
+\i (00:00:13) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 1
+\i (00:00:13) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
+\i (00:00:13) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 0
+\i (00:00:13) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
+\i (00:00:14) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Bottom" 1
+\i (00:00:14) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 3 0
+\i (00:00:15) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 1
+\i (00:00:15) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
+\i (00:00:16) QtSignal ColorVisibilityDialog CVDOkButton clicked
+\i (00:00:17) color192 
+\i (00:00:19) QtSignal CVDLayerContainer CVDVisibilityOn clicked
+\i (00:00:20) QtSignal ColorVisibilityDialog CVDOkButton clicked
+\i (00:00:24) save 
+\i (00:00:24) fillin yes 
+\t (00:00:25) Symbol 'rj45-8p8c.psm' created.
+\i (00:00:29) exit 
+\t (00:00:29)     Journal end - Sat May 10 13:22:14 2025
diff --git a/other/batch_drc.log b/other/batch_drc.log
index a29bd0b..7c46f0c 100644
--- a/other/batch_drc.log
+++ b/other/batch_drc.log
@@ -2,9 +2,9 @@
 (                                                                     )
 (    DRC Update                                                       )
 (                                                                     )
-(    Drawing          : B0505S_1WR3.dra                               )
+(    Drawing          : rj45-8p8c.dra                                 )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Tue Apr 22 23:31:49 2025                      )
+(    Date/Time        : Sat May 10 09:38:41 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/other/batch_drc.log,1 b/other/batch_drc.log,1
new file mode 100644
index 0000000..a29bd0b
--- /dev/null
+++ b/other/batch_drc.log,1
@@ -0,0 +1,27 @@
+(---------------------------------------------------------------------)
+(                                                                     )
+(    DRC Update                                                       )
+(                                                                     )
+(    Drawing          : B0505S_1WR3.dra                               )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Tue Apr 22 23:31:49 2025                      )
+(                                                                     )
+(---------------------------------------------------------------------)
+
+
+ ========= check shapes                       0:00:00
+ ========= check standalone pins              0:00:00
+ ========= check symbols (pins,lines,text)    0:00:00
+ ========= check xnets                        0:00:00
+ ========= check nets                         0:00:00
+ ========= check standalone branches          0:00:00
+ ========= check standalone filled rectangles 0:00:00
+ ========= check standalone lines             0:00:00
+ ========= check standalone text              0:00:00
+ ========= check standalone rectangles        0:00:00
+
+ ..... Total number of DRC errors  0
+
+ ..... DRC update completed, total CPU time   0:00:00
+ *************************************************************************
+
diff --git a/other/downrev.log b/other/downrev.log
index e64cdc0..0cf5b37 100644
--- a/other/downrev.log
+++ b/other/downrev.log
@@ -2,9 +2,9 @@
 (                                                                     )
 (    Downrev Design                                                   )
 (                                                                     )
-(    Drawing          : PCB1094M4.dra                                 )
+(    Drawing          : rj45-8p8c.dra                                 )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Sun Apr 27 22:58:41 2025                      )
+(    Date/Time        : Sat May 10 13:22:10 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/other/downrev.log,1 b/other/downrev.log,1
index d84eed2..3563507 100644
--- a/other/downrev.log,1
+++ b/other/downrev.log,1
@@ -2,9 +2,9 @@
 (                                                                     )
 (    Downrev Design                                                   )
 (                                                                     )
-(    Drawing          : PCB1094M4.dra                                 )
+(    Drawing          : rj45-8p8c.dra                                 )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Sun Apr 27 22:58:38 2025                      )
+(    Date/Time        : Sat May 10 09:38:41 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/other/downrev.log,2 b/other/downrev.log,2
index e64cdc0..0cf5b37 100644
--- a/other/downrev.log,2
+++ b/other/downrev.log,2
@@ -2,9 +2,9 @@
 (                                                                     )
 (    Downrev Design                                                   )
 (                                                                     )
-(    Drawing          : PCB1094M4.dra                                 )
+(    Drawing          : rj45-8p8c.dra                                 )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Sun Apr 27 22:58:41 2025                      )
+(    Date/Time        : Sat May 10 13:22:10 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/other/downrev.log,3 b/other/downrev.log,3
index e64cdc0..0cf5b37 100644
--- a/other/downrev.log,3
+++ b/other/downrev.log,3
@@ -2,9 +2,9 @@
 (                                                                     )
 (    Downrev Design                                                   )
 (                                                                     )
-(    Drawing          : PCB1094M4.dra                                 )
+(    Drawing          : rj45-8p8c.dra                                 )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Sun Apr 27 22:58:41 2025                      )
+(    Date/Time        : Sat May 10 13:22:10 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/other/master.tag b/other/master.tag
index d1d1eac..5e4e40b 100644
--- a/other/master.tag
+++ b/other/master.tag
@@ -1 +1 @@
-PCB1094M4.dra
+rj45-8p8c.dra
diff --git a/other/padstack_editor.jrl b/other/padstack_editor.jrl
index eb85060..210e1e5 100644
--- a/other/padstack_editor.jrl
+++ b/other/padstack_editor.jrl
@@ -1,7 +1,9 @@
 \t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
-\t (00:00:00)     Journal start - Sun Apr 27 22:51:05 2025
-\t (00:00:00)         Host=XEROLYSKINNER User=Xeroly Pid=28608 CPUs=16
-\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\other\pcb-10b.pad
+\t (00:00:00)     Journal start - Sat May 10 13:14:47 2025
+\t (00:00:00)         Host=XEROLYSKINNER User=Xeroly Pid=47704 CPUs=16
+\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\other\rj45-8p8c-4.pad
 \t (00:00:00) 
-\d (00:00:03) QtSignal MainWindow Exit triggered
-\t (00:00:03)     Journal end - Sun Apr 27 22:51:08 2025
+\d (00:00:01) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
+\d (00:00:02) QtSignal GuidedTabsParent GuidedTabs currentChanged "Drill Offset"
+\d (00:00:05) QtSignal MainWindow Exit triggered
+\t (00:00:05)     Journal end - Sat May 10 13:14:52 2025
diff --git a/other/padstack_editor.jrl,1 b/other/padstack_editor.jrl,1
index cd1ff0f..730afe0 100644
--- a/other/padstack_editor.jrl,1
+++ b/other/padstack_editor.jrl,1
@@ -1,34 +1,9 @@
-\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
-\t (00:00:00)     Journal start - Sun Apr 27 22:48:26 2025
-\t (00:00:00)         Host=XEROLYSKINNER User=Xeroly Pid=1428 CPUs=16
-\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\other\pcb-10b.pad
-\t (00:00:00) 
-\d (00:00:02) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
-\d (00:00:19) QtSignal GuidedDesignLayersTab PadWidth editingFinished "10.0000"
-\d (00:00:21) QtSignal GuidedDesignLayersTab PadOffsetX editingFinished "10.8000"
-\d (00:00:23) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
-\d (00:00:26) QtSignal GuidedMaskLayersTab PadWidth editingFinished "10.0000"
-\d (00:00:32) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
-\d (00:00:34) QtSignal GuidedTabsParent GuidedTabs currentChanged Start
-\d (00:00:36) QtSignal GuidedTabsParent NewPads currentRowChanged 3
-\d (00:00:36) QtSignal GuidedTabsParent NewPads itemSelectionChanged Rectangle
-\d (00:00:36) QtSignal GuidedTabsParent NewPads itemClicked Rectangle
-\d (00:00:37) QtFillin Yes
-\d (00:00:38) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
-\d (00:00:41) QtSignal GuidedDesignLayersTab PadWidth editingFinished "10.0000"
-\d (00:00:43) QtSignal GuidedDesignLayersTab PadHeight editingFinished "10.8000"
-\d (00:00:44) QtSignal GuidedDesignLayersTab PadOffsetX editingFinished "0.0000"
-\d (00:00:45) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
-\d (00:00:47) QtSignal GuidedMaskLayersTab PadWidth editingFinished "10.0000"
-\d (00:00:50) QtSignal GuidedMaskLayersTab PadHeight editingFinished "10.8600"
-\d (00:00:50) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
-\d (00:00:52) QtSignal GuidedMaskLayersTab PadWidth editingFinished "10.0600"
-\d (00:00:52) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
-\d (00:00:53) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
-\d (00:00:53) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 "Regular Pad" 2 1
-\d (00:00:55) QtSignal GuidedMaskLayersTab PadWidth editingFinished "10.0000"
-\d (00:00:57) QtSignal GuidedMaskLayersTab PadHeight editingFinished "10.8000"
-\d (00:00:57) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
-\d (00:00:58) QtSignal MainWindow Save triggered
-\d (00:01:00) QtSignal MainWindow Exit triggered
-\t (00:01:00)     Journal end - Sun Apr 27 22:49:26 2025
+\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
+\t (00:00:00)     Journal start - Sat May 10 13:14:41 2025
+\t (00:00:00)         Host=XEROLYSKINNER User=Xeroly Pid=1216 CPUs=16
+\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\other\rj45-8p8c-3.pad
+\t (00:00:00) 
+\d (00:00:02) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
+\d (00:00:03) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
+\d (00:00:05) QtSignal MainWindow Exit triggered
+\t (00:00:05)     Journal end - Sat May 10 13:14:46 2025
diff --git a/other/param_read.log b/other/param_read.log
index aae29dc..ac85182 100644
--- a/other/param_read.log
+++ b/other/param_read.log
@@ -2,15 +2,15 @@
 (                                                                     )
 (    Parameter File READ                                              )
 (                                                                     )
-(    Drawing          : PCB1094M4.dra                                 )
+(    Drawing          : USR-WIFI232-A2.dra                            )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Sun Apr 27 22:55:50 2025                      )
+(    Date/Time        : Fri May  2 19:49:43 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
 
 	Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
-	Layout Name   : PCB1094M4.dra
+	Layout Name   : USR-WIFI232-A2.dra
 
 Reading...parameter_header:
 Reading...db_common_type:
diff --git a/other/param_read.log,1 b/other/param_read.log,1
index 56b3f10..7a09735 100644
--- a/other/param_read.log,1
+++ b/other/param_read.log,1
@@ -2,15 +2,15 @@
 (                                                                     )
 (    Parameter File READ                                              )
 (                                                                     )
-(    Drawing          : fnwx_r1.dra                                   )
+(    Drawing          : WH-LTE-7S1.dra                                )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Sun Apr 27 20:29:06 2025                      )
+(    Date/Time        : Sun Apr 27 20:57:13 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
 
-	Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
-	Layout Name   : fnwx_r1.dra
+	Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
+	Layout Name   : WH-LTE-7S1.dra
 
 Reading...parameter_header:
 Reading...db_common_type:
diff --git a/other/param_read.log,2 b/other/param_read.log,2
index 7a09735..84683e1 100644
--- a/other/param_read.log,2
+++ b/other/param_read.log,2
@@ -2,15 +2,15 @@
 (                                                                     )
 (    Parameter File READ                                              )
 (                                                                     )
-(    Drawing          : WH-LTE-7S1.dra                                )
+(    Drawing          : pcb-10b.dra                                   )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Sun Apr 27 20:57:13 2025                      )
+(    Date/Time        : Sun Apr 27 22:49:58 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
 
-	Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
-	Layout Name   : WH-LTE-7S1.dra
+	Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
+	Layout Name   : pcb-10b.dra
 
 Reading...parameter_header:
 Reading...db_common_type:
diff --git a/other/param_read.log,3 b/other/param_read.log,3
index 84683e1..aae29dc 100644
--- a/other/param_read.log,3
+++ b/other/param_read.log,3
@@ -2,15 +2,15 @@
 (                                                                     )
 (    Parameter File READ                                              )
 (                                                                     )
-(    Drawing          : pcb-10b.dra                                   )
+(    Drawing          : PCB1094M4.dra                                 )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Sun Apr 27 22:49:58 2025                      )
+(    Date/Time        : Sun Apr 27 22:55:50 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
 
 	Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
-	Layout Name   : pcb-10b.dra
+	Layout Name   : PCB1094M4.dra
 
 Reading...parameter_header:
 Reading...db_common_type:
diff --git a/other/pcb1094m4.log b/other/pcb1094m4.log
index bff7806..d2448fe 100644
--- a/other/pcb1094m4.log
+++ b/other/pcb1094m4.log
@@ -4,13 +4,13 @@
 (                                                                     )
 (    Drawing          : PCB1094M4.dra                                 )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Sun Apr 27 22:58:41 2025                      )
+(    Date/Time        : Fri May  2 01:53:20 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
 
 Create Symbol of type: PACKAGE
-    Directory = D:/workspace/GitHub/pcb_lib/other
+    Directory = D:/Workspace/GitHub/pcb_lib/other
     Name      = pcb1094m4.psm
     User      = Xeroly
     Machine   = XEROLYSKINNER
diff --git a/other/pcb1094m4.log,2 b/other/pcb1094m4.log,2
new file mode 100644
index 0000000..bff7806
--- /dev/null
+++ b/other/pcb1094m4.log,2
@@ -0,0 +1,23 @@
+(---------------------------------------------------------------------)
+(                                                                     )
+(    CREATE SYMBOL                                                    )
+(                                                                     )
+(    Drawing          : PCB1094M4.dra                                 )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sun Apr 27 22:58:41 2025                      )
+(                                                                     )
+(---------------------------------------------------------------------)
+
+
+Create Symbol of type: PACKAGE
+    Directory = D:/workspace/GitHub/pcb_lib/other
+    Name      = pcb1094m4.psm
+    User      = Xeroly
+    Machine   = XEROLYSKINNER
+
+
+Create symbol started.
+ 
+
+Create symbol completed.
+
diff --git a/other/pcb1094m4.psm b/other/pcb1094m4.psm
index 7d31d1e..e159cec 100644
Binary files a/other/pcb1094m4.psm and b/other/pcb1094m4.psm differ
diff --git a/other/rj45-8p8c-1.pad b/other/rj45-8p8c-1.pad
index 7f179aa..977f83f 100644
Binary files a/other/rj45-8p8c-1.pad and b/other/rj45-8p8c-1.pad differ
diff --git a/other/rj45-8p8c-2.pad b/other/rj45-8p8c-2.pad
index 022eacd..5f493c0 100644
Binary files a/other/rj45-8p8c-2.pad and b/other/rj45-8p8c-2.pad differ
diff --git a/other/rj45-8p8c-3.pad b/other/rj45-8p8c-3.pad
index af3577a..aa81512 100644
Binary files a/other/rj45-8p8c-3.pad and b/other/rj45-8p8c-3.pad differ
diff --git a/other/rj45-8p8c-4.pad b/other/rj45-8p8c-4.pad
index 63768b7..fe147ec 100644
Binary files a/other/rj45-8p8c-4.pad and b/other/rj45-8p8c-4.pad differ
diff --git a/other/rj45-8p8c.dra b/other/rj45-8p8c.dra
index 8632cfd..6a07d50 100644
Binary files a/other/rj45-8p8c.dra and b/other/rj45-8p8c.dra differ
diff --git a/other/rj45-8p8c.log b/other/rj45-8p8c.log
new file mode 100644
index 0000000..ab4ffa1
--- /dev/null
+++ b/other/rj45-8p8c.log
@@ -0,0 +1,23 @@
+(---------------------------------------------------------------------)
+(                                                                     )
+(    CREATE SYMBOL                                                    )
+(                                                                     )
+(    Drawing          : rj45-8p8c.dra                                 )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sat May 10 13:22:10 2025                      )
+(                                                                     )
+(---------------------------------------------------------------------)
+
+
+Create Symbol of type: PACKAGE
+    Directory = D:/Workspace/GitHub/pcb_lib/other
+    Name      = rj45-8p8c.psm
+    User      = Xeroly
+    Machine   = XEROLYSKINNER
+
+
+Create symbol started.
+ 
+
+Create symbol completed.
+
diff --git a/other/rj45-8p8c.log,1 b/other/rj45-8p8c.log,1
new file mode 100644
index 0000000..bc5da63
--- /dev/null
+++ b/other/rj45-8p8c.log,1
@@ -0,0 +1,23 @@
+(---------------------------------------------------------------------)
+(                                                                     )
+(    CREATE SYMBOL                                                    )
+(                                                                     )
+(    Drawing          : rj45-8p8c.dra                                 )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sat May 10 06:04:54 2025                      )
+(                                                                     )
+(---------------------------------------------------------------------)
+
+
+Create Symbol of type: PACKAGE
+    Directory = D:/Workspace/GitHub/pcb_lib/other
+    Name      = rj45-8p8c.psm
+    User      = Xeroly
+    Machine   = XEROLYSKINNER
+
+
+Create symbol started.
+ 
+
+Create symbol completed.
+
diff --git a/other/rj45-8p8c.log,2 b/other/rj45-8p8c.log,2
new file mode 100644
index 0000000..52a847d
--- /dev/null
+++ b/other/rj45-8p8c.log,2
@@ -0,0 +1,23 @@
+(---------------------------------------------------------------------)
+(                                                                     )
+(    CREATE SYMBOL                                                    )
+(                                                                     )
+(    Drawing          : rj45-8p8c.dra                                 )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sat May 10 09:38:41 2025                      )
+(                                                                     )
+(---------------------------------------------------------------------)
+
+
+Create Symbol of type: PACKAGE
+    Directory = D:/Workspace/GitHub/pcb_lib/other
+    Name      = rj45-8p8c.psm
+    User      = Xeroly
+    Machine   = XEROLYSKINNER
+
+
+Create symbol started.
+ 
+
+Create symbol completed.
+
diff --git a/other/rj45-8p8c.psm b/other/rj45-8p8c.psm
index c33d2a3..f14ae71 100644
Binary files a/other/rj45-8p8c.psm and b/other/rj45-8p8c.psm differ
diff --git a/other/stepFacetFiles4Map/PCB-1094M4.xml b/other/stepFacetFiles4Map/PCB-1094M4.xml
new file mode 100644
index 0000000..9df4775
--- /dev/null
+++ b/other/stepFacetFiles4Map/PCB-1094M4.xml
@@ -0,0 +1,5851 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<step-assembly root="id524">
+<product id="id524" name="PCB-1094M4" shape="id577"/>
+<shape id="id577" unit="mm 0.001000" shell="id607"/>
+<shell id="id607" color="cad1ee">
+    <verts>
+        <v p="2.9749999999999988 -1.5079383622383153e-11 0.00031254884338974818"/>
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+        <v p="2.4802120268776435 3.0373837199224754e-16 3"/>
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+    </facets>
+</shell>
+</step-assembly>
diff --git a/other/stepFacetFiles4Map/stepFileInfo.txt b/other/stepFacetFiles4Map/stepFileInfo.txt
index 98125b3..0978262 100644
--- a/other/stepFacetFiles4Map/stepFileInfo.txt
+++ b/other/stepFacetFiles4Map/stepFileInfo.txt
@@ -4,12 +4,13 @@ XH2_54-W2P.step ! 183892 ! 1745749128
 link_3.5_2x1.STEP ! 435783 ! 1723144412
 TYPE-C.stp ! 1362496 ! 1710578258
 KF7.62-2P.STEP ! 217264 ! 1722981445
-EC11.STEP ! 1541194 ! 1712715932
 rtl8189-board.STEP ! 1900144 ! 1712473643
+EC11.STEP ! 1541194 ! 1712715932
 link_3.5_2x5.STEP ! 467005 ! 1723144633
 XH2_54-W3P.step ! 213594 ! 1745749034
 KF7.62-3P.STEP ! 218099 ! 1722981496
 rj45-8p8c.step ! 2080205 ! 1712409758
+PCB-1094M4.STEP ! 66472 ! 1746121909
 XH2_54-W5P.step ! 305916 ! 1745749057
 link_3.5_2x4.STEP ! 466145 ! 1723146123
 fpc0_5-40p.stp ! 9221743 ! 1584132940
diff --git a/other/stepFacetFiles4Map/stepFileInfo.txt,1 b/other/stepFacetFiles4Map/stepFileInfo.txt,1
index e1d207b..98125b3 100644
--- a/other/stepFacetFiles4Map/stepFileInfo.txt,1
+++ b/other/stepFacetFiles4Map/stepFileInfo.txt,1
@@ -4,8 +4,8 @@ XH2_54-W2P.step ! 183892 ! 1745749128
 link_3.5_2x1.STEP ! 435783 ! 1723144412
 TYPE-C.stp ! 1362496 ! 1710578258
 KF7.62-2P.STEP ! 217264 ! 1722981445
-rtl8189-board.STEP ! 1900144 ! 1712473643
 EC11.STEP ! 1541194 ! 1712715932
+rtl8189-board.STEP ! 1900144 ! 1712473643
 link_3.5_2x5.STEP ! 467005 ! 1723144633
 XH2_54-W3P.step ! 213594 ! 1745749034
 KF7.62-3P.STEP ! 218099 ! 1722981496
@@ -15,6 +15,6 @@ link_3.5_2x4.STEP ! 466145 ! 1723146123
 fpc0_5-40p.stp ! 9221743 ! 1584132940
 fpc0_5-6p.stp ! 1966209 ! 1584132963
 fpc0_5-50p.stp ! 11408226 ! 1584132947
-B05051WR3.STEP ! 65139 ! 1745402887
+B05051WR3.STEP ! 65128 ! 1745749519
 wh-gm5.STEP ! 888098 ! 1712839932
 oled-0_96.step ! 601137 ! 1712757601
diff --git a/other/usr-wifi232-a2.log b/other/usr-wifi232-a2.log
new file mode 100644
index 0000000..e82c6d0
--- /dev/null
+++ b/other/usr-wifi232-a2.log
@@ -0,0 +1,23 @@
+(---------------------------------------------------------------------)
+(                                                                     )
+(    CREATE SYMBOL                                                    )
+(                                                                     )
+(    Drawing          : USR-WIFI232-A2.dra                            )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Fri May  2 19:56:28 2025                      )
+(                                                                     )
+(---------------------------------------------------------------------)
+
+
+Create Symbol of type: PACKAGE
+    Directory = D:/workspace/GitHub/pcb_lib/other
+    Name      = usr-wifi232-a2.psm
+    User      = Xeroly
+    Machine   = XEROLYSKINNER
+
+
+Create symbol started.
+ 
+
+Create symbol completed.
+
diff --git a/other/usr-wifi232-a2.log,1 b/other/usr-wifi232-a2.log,1
new file mode 100644
index 0000000..77d6744
--- /dev/null
+++ b/other/usr-wifi232-a2.log,1
@@ -0,0 +1,24 @@
+(---------------------------------------------------------------------)
+(                                                                     )
+(    CREATE SYMBOL                                                    )
+(                                                                     )
+(    Drawing          : USR-WIFI232-A2.dra                            )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Fri May  2 19:56:08 2025                      )
+(                                                                     )
+(---------------------------------------------------------------------)
+
+
+Create Symbol of type: PACKAGE
+    Directory = D:/workspace/GitHub/pcb_lib/other
+    Name      = usr-wifi232-a2.psm
+    User      = Xeroly
+    Machine   = XEROLYSKINNER
+
+
+Create symbol started.
+ 
+ ERROR(SPMHCS-1): Symbol is missing a refdes. 
+
+ERROR(SPMHA1-291): Create symbol has been aborted.
+
diff --git a/other/usr-wifi232-a2.psm b/other/usr-wifi232-a2.psm
new file mode 100644
index 0000000..6e26eca
Binary files /dev/null and b/other/usr-wifi232-a2.psm differ
diff --git a/smc/allegro.jrl b/smc/allegro.jrl
index e681c70..14d5c3c 100644
--- a/smc/allegro.jrl
+++ b/smc/allegro.jrl
@@ -1,33 +1,440 @@
-\t (00:00:01) allegro 23.1 P001 Windows SPB 64-bit Edition
-\t (00:00:01)     Journal start - Fri Apr 25 17:19:42 2025
-\t (00:00:01)         Host=XEROLYSKINNER User=Xeroly Pid=23772 CPUs=16
-\t (00:00:01) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\smc\sod-323.dra
-\t (00:00:01) 
-   (00:00:01) Loading axlcore.cxt 
-\t (00:00:01) Opening existing design...
-\i (00:00:01) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sod-323"
-\d (00:00:01) Design opened: D:/Workspace/GitHub/pcb_lib/smc/sod-323.dra
-\i (00:00:02) trapsize 370
-\i (00:00:02) trapsize 381
-\i (00:00:02) trapsize 370
-\i (00:00:02) trapsize 418
-\i (00:00:02) trapsize 288
-\i (00:00:04) delete 
-\i (00:00:05) pick grid -1.7374 2.9915
-\t (00:00:05) last pick:  -1.7000 3.0000
-\t (00:00:05) Text "Last Edit:2024-3-28"
-\i (00:00:06) pick grid -2.1403 1.4894
-\t (00:00:06) last pick:  -2.1000 1.5000
-\t (00:00:06) Text "Approved[1]"
-\i (00:00:07) pick grid -2.1403 -1.6759
-\t (00:00:07) last pick:  -2.1000 -1.7000
-\t (00:00:07) Text "*Untested*"
-\i (00:00:14) pick grid 1.6409 -1.4054
-\t (00:00:14) last pick:  1.6000 -1.4000
-\i (00:00:17) prepopup 1.4222 -1.6816
-\i (00:00:18) done 
-\i (00:00:19) save 
-\i (00:00:19) fillin yes 
-\t (00:00:20) Symbol 'sod-323.psm' created.
-\i (00:00:20) exit 
-\t (00:00:20)     Journal end - Fri Apr 25 17:20:01 2025
+\t (00:00:37) allegro 23.1 P001 Windows SPB 64-bit Edition
+\t (00:00:37)     Journal start - Sat May 10 04:58:28 2025
+\t (00:00:37)         Host=XEROLYSKINNER User=Xeroly Pid=35792 CPUs=16
+\t (00:00:37) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe
+\t (00:00:37) 
+\t (00:00:37) Starting new design...
+\i (00:00:37) trapsize 101
+\i (00:00:37) trapsize 103
+\i (00:00:37) trapsize 101
+\t (00:00:37) Grids are drawn 40.640, 40.640 apart for enhanced viewing.
+\i (00:00:37) trapsize 101
+\i (00:00:37) trapsize 101
+\i (00:00:37) package symbol wizard 
+   (00:00:39) Loading cmds.cxt 
+\i (00:00:39) setwindow form.sym_wizard
+\i (00:00:39) FORM sym_wizard soic YES 
+\i (00:00:40) FORM sym_wizard wiz_next  
+\i (00:00:41) FORM sym_wizard load_template  
+\t (00:00:41) Opening existing design...
+\t (00:00:41) Grids are drawn 200, 200 apart for enhanced viewing.
+\i (00:00:41) setwindow pcb
+\i (00:00:41) trapsize 126
+\i (00:00:41) trapsize 129
+\i (00:00:41) trapsize 126
+\t (00:00:41) Grids are drawn 200, 200 apart for enhanced viewing.
+\i (00:00:41) trapsize 148
+\d (00:00:41) Design opened: D:/software/Cadence/SPB_23.1/share/pcb/pcb_lib/symbols/template/sym_template.dra
+\i (00:00:41) trapsize 143
+\i (00:00:42) setwindow form.sym_wizard
+\i (00:00:42) FORM sym_wizard wiz_next  
+\i (00:00:44) FORM sym_wizard pack_units Millimeter 
+\i (00:00:46) FORM sym_wizard pack_units_create Millimeter 
+\i (00:00:47) FORM sym_wizard wiz_next  
+\i (00:00:58) FORM sym_wizard sop_pin_count 1 
+\i (00:00:58) FORM sym_wizard sop_pin_count 4 
+\i (00:01:04) FORM sym_wizard sop_e 2.540 
+\i (00:01:31) FORM sym_wizard sop_e1 9.160 
+\i (00:01:34) FORM sym_wizard sop_width 6.450 
+\i (00:02:05) FORM sym_wizard sop_len 4.500 
+\i (00:02:05) FORM sym_wizard wiz_next  
+\i (00:02:08) FORM sym_wizard default_padstack smd_4 
+\i (00:02:09) FORM sym_wizard wiz_next  
+\i (00:02:10) FORM sym_wizard wiz_next  
+\i (00:02:11) FORM sym_wizard wiz_finish  
+\w (00:02:11) WARNING(SPMHUT-48): Scaled value has been rounded off.
+\t (00:02:11) Grids are drawn 5.080, 5.080 apart for enhanced viewing.
+\i (00:02:11) setwindow pcb
+\i (00:02:11) trapsize 3638
+\t (00:02:11) Performing DRC...
+\t (00:02:11) No DRC errors detected.
+\w (00:02:11) WARNING(SPMHUT-48): Scaled value has been rounded off.
+\i (00:02:11) trapsize 3638
+\i (00:02:11) trapsize 44
+\i (00:02:11) trapsize 44
+\i (00:02:11) trapsize 44
+\i (00:02:11) trapsize 44
+\t (00:02:11) Performing DRC...
+\t (00:02:11) No DRC errors detected.
+\t (00:02:11) Creating package symbol 'D:/workspace/GitHub/pcb_lib/smc/smd_4.psm'.
+\t (00:02:11) Starting Create symbol...
+\i (00:02:15) param in 
+\i (00:02:16) setwindow form.parm_in
+\i (00:02:16) FORM parm_in browse  
+\i (00:02:20) fillin "D:/workspace/GitHub/pcb_lib/XerolySkinner.prm"
+\i (00:02:21) FORM parm_in execute  
+\t (00:02:21) Starting Importing parameter file...
+\w (00:02:21) WARNING(SPMHGE-269): param in had warnings, use Viewlog to review the log file.
+\t (00:02:21) Opening existing design...
+\t (00:02:22) Grids are drawn 40.640, 40.640 apart for enhanced viewing.
+\i (00:02:22) setwindow pcb
+\i (00:02:22) trapsize 44
+\i (00:02:23) setwindow text
+\i (00:02:23) close
+\i (00:02:25) setwindow form.parm_in
+\i (00:02:25) FORM parm_in cancel  
+\i (00:02:30) setwindow pcb
+\i (00:02:30) define grid 
+\t (00:02:30) Spacing fields allow simple equations to aid calculations; prefix with =
+\i (00:02:33) setwindow form.grid
+\i (00:02:33) FORM grid non_etch non_etch_x_grids 0.01 
+\i (00:02:34) FORM grid non_etch non_etch_y_grids 0.01 
+\i (00:02:36) FORM grid all_etch all_etch_x_grids 0.01 
+\i (00:02:36) FORM grid all_etch all_etch_y_grids 0.01 
+\i (00:02:37) FORM grid all_etch all_etch_x_offset 0.000 
+\i (00:02:37) FORM grid all_etch all_etch_y_offset 0.000 
+\i (00:02:38) FORM grid top subclass_x_grids 0.010 
+\i (00:02:38) FORM grid top subclass_x_grids 0.010 
+\i (00:02:38) FORM grid done  
+\t (00:02:38) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
+\i (00:02:39) setwindow pcb
+\i (00:02:39) zoom out 1 
+\i (00:02:39) setwindow pcb
+\i (00:02:39) zoom out -0.775 -4.376
+\t (00:02:39) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
+\i (00:02:39) trapsize 87
+\i (00:02:41) zoom in 1 
+\i (00:02:41) setwindow pcb
+\i (00:02:41) zoom in 0.658 1.234
+\t (00:02:41) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
+\i (00:02:41) trapsize 44
+\i (00:02:41) zoom in 1 
+\i (00:02:41) setwindow pcb
+\i (00:02:41) zoom in 0.658 1.234
+\t (00:02:41) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
+\i (00:02:41) trapsize 22
+\i (00:02:42) zoom out 1 
+\i (00:02:42) setwindow pcb
+\i (00:02:42) zoom out 0.659 1.234
+\t (00:02:42) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
+\i (00:02:42) trapsize 44
+\i (00:02:42) zoom out 1 
+\i (00:02:42) setwindow pcb
+\i (00:02:42) zoom out 0.658 1.235
+\t (00:02:42) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
+\i (00:02:42) trapsize 87
+\i (00:02:43) add line 
+\i (00:02:46) setwindow form.mini
+\i (00:02:46) FORM mini class 'PACKAGE GEOMETRY' 
+\i (00:02:48) FORM mini subclass SILKSCREEN_TOP 
+\i (00:02:48) setwindow pcb
+\i (00:02:48) updateport CVPane
+\i (00:02:50) setwindow form.mini
+\i (00:02:50) FORM mini line_width 0.150 
+\i (00:02:52) setwindow pcb
+\i (00:02:52) zoom in 1 
+\i (00:02:52) setwindow pcb
+\i (00:02:52) zoom in -3.147 2.316
+\t (00:02:52) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
+\i (00:02:52) trapsize 44
+\i (00:02:52) zoom in 1 
+\i (00:02:52) setwindow pcb
+\i (00:02:52) zoom in -3.147 2.316
+\t (00:02:52) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
+\i (00:02:52) trapsize 22
+\i (00:02:52) zoom in 1 
+\i (00:02:52) setwindow pcb
+\i (00:02:52) zoom in -3.147 2.316
+\i (00:02:52) trapsize 11
+\i (00:02:53) zoom out 1 
+\i (00:02:53) setwindow pcb
+\i (00:02:53) zoom out -3.146 2.316
+\i (00:02:53) trapsize 22
+\i (00:02:53) zoom out 1 
+\i (00:02:53) setwindow pcb
+\i (00:02:53) zoom out -3.147 2.316
+\t (00:02:53) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
+\i (00:02:53) trapsize 44
+\i (00:02:54) color192 
+\i (00:02:55) QtSignal CVDLayerContainer CVDVisibilityOff clicked
+\i (00:02:59) QtSignal CVDLayerContainer CVDFilterLayerEntry editingFinished silk
+\i (00:02:59) QtSignal CVDLayerTable VertHeader clickedCheckBox "Silkscreen_Top" 1
+\i (00:02:59) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 1 0
+\i (00:03:00) QtSignal ColorVisibilityDialog CVDOkButton clicked
+\i (00:03:01) delete 
+\i (00:03:04) setwindow form.find
+\i (00:03:04) FORM find all_on  
+\i (00:03:05) setwindow pcb
+\i (00:03:05) pick grid 2.832 2.228
+\t (00:03:05) last pick:  2.830 2.230
+\t (00:03:05) Line "Package Geometry/Silkscreen_Top"
+\i (00:03:05) prepopup 3.016 2.534
+\i (00:03:06) done 
+\i (00:03:07) color192 
+\i (00:03:08) QtSignal CVDLayerContainer CVDVisibilityOn clicked
+\i (00:03:09) QtSignal ColorVisibilityDialog CVDOkButton clicked
+\i (00:03:10) add line 
+\i (00:03:13) zoom in 1 
+\i (00:03:13) setwindow pcb
+\i (00:03:13) zoom in -3.173 2.220
+\t (00:03:13) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
+\i (00:03:13) trapsize 22
+\i (00:03:13) zoom in 1 
+\i (00:03:13) setwindow pcb
+\i (00:03:13) zoom in -3.173 2.220
+\i (00:03:13) trapsize 11
+\i (00:03:13) zoom in 1 
+\i (00:03:13) setwindow pcb
+\i (00:03:13) zoom in -3.173 2.220
+\i (00:03:13) trapsize 5
+\i (00:03:14) zoom in 1 
+\i (00:03:14) setwindow pcb
+\i (00:03:14) zoom in -3.208 2.254
+\i (00:03:14) trapsize 3
+\i (00:03:14) zoom in 1 
+\i (00:03:14) setwindow pcb
+\i (00:03:14) zoom in -3.208 2.254
+\i (00:03:14) trapsize 1
+\i (00:03:17) define grid 
+\t (00:03:17) Spacing fields allow simple equations to aid calculations; prefix with =
+\i (00:03:18) setwindow form.grid
+\i (00:03:18) FORM grid non_etch non_etch_x_grids 0.1 
+\i (00:03:19) FORM grid non_etch non_etch_y_grids 0.1 
+\i (00:03:20) FORM grid all_etch all_etch_x_grids 0.1 
+\i (00:03:20) FORM grid all_etch all_etch_y_grids 0.1 
+\i (00:03:20) FORM grid all_etch all_etch_x_offset 0.000 
+\i (00:03:21) FORM grid all_etch all_etch_y_offset 0.000 
+\i (00:03:21) FORM grid top subclass_x_grids 0.100 
+\i (00:03:21) FORM grid top subclass_x_grids 0.100 
+\i (00:03:21) FORM grid done  
+\i (00:03:22) setwindow pcb
+\i (00:03:22) zoom out 1 
+\i (00:03:22) setwindow pcb
+\i (00:03:22) zoom out -3.218 2.264
+\i (00:03:22) trapsize 3
+\i (00:03:23) zoom out 1 
+\i (00:03:23) setwindow pcb
+\i (00:03:23) zoom out -3.214 2.243
+\i (00:03:23) trapsize 5
+\i (00:03:23) zoom out 1 
+\i (00:03:23) setwindow pcb
+\i (00:03:23) zoom out -3.215 2.243
+\i (00:03:23) trapsize 11
+\i (00:03:23) zoom out 1 
+\i (00:03:23) setwindow pcb
+\i (00:03:23) zoom out -3.214 2.243
+\i (00:03:23) trapsize 22
+\i (00:03:26) pick grid -3.197 2.300
+\t (00:03:26) last pick:  -3.200 2.300
+\i (00:03:26) pick grid -3.351 1.815
+\t (00:03:26) last pick:  -3.400 1.800
+\i (00:03:26) zoom in 1 
+\i (00:03:26) setwindow pcb
+\i (00:03:26) zoom in -3.429 1.780
+\i (00:03:26) trapsize 11
+\i (00:03:26) zoom in 1 
+\i (00:03:26) setwindow pcb
+\i (00:03:26) zoom in -3.429 1.780
+\i (00:03:26) trapsize 5
+\i (00:03:27) prepopup -3.428 1.780
+\i (00:03:28) oops 
+\t (00:03:28) last pick:  -3.200 2.300
+\i (00:03:28) zoom out 1 
+\i (00:03:28) setwindow pcb
+\i (00:03:28) zoom out -3.428 1.780
+\i (00:03:28) trapsize 11
+\i (00:03:28) zoom out 1 
+\i (00:03:28) setwindow pcb
+\i (00:03:28) zoom out -3.429 1.780
+\i (00:03:28) trapsize 22
+\i (00:03:28) zoom out 1 
+\i (00:03:28) setwindow pcb
+\i (00:03:28) zoom out -3.428 1.781
+\i (00:03:28) trapsize 44
+\i (00:03:28) zoom out 1 
+\i (00:03:28) setwindow pcb
+\i (00:03:28) zoom out -3.429 1.780
+\i (00:03:28) trapsize 88
+\i (00:03:29) zoom out 1 
+\i (00:03:29) setwindow pcb
+\i (00:03:29) zoom out 2.978 1.954
+\i (00:03:29) trapsize 125
+\i (00:03:29) zoom out 1 
+\i (00:03:29) setwindow pcb
+\i (00:03:29) zoom out -2.036 -0.089
+\i (00:03:29) trapsize 125
+\i (00:03:29) zoom out 1 
+\i (00:03:29) setwindow pcb
+\i (00:03:29) zoom out -2.036 -0.089
+\i (00:03:29) trapsize 125
+\i (00:03:30) zoom in 1 
+\i (00:03:30) setwindow pcb
+\i (00:03:30) zoom in 3.755 2.831
+\i (00:03:30) trapsize 62
+\i (00:03:30) zoom in 1 
+\i (00:03:30) setwindow pcb
+\i (00:03:30) zoom in 3.755 4.790
+\i (00:03:30) trapsize 31
+\i (00:03:30) zoom in 1 
+\i (00:03:30) setwindow pcb
+\i (00:03:30) zoom in 3.755 4.790
+\i (00:03:30) trapsize 16
+\i (00:03:30) zoom in 1 
+\i (00:03:30) setwindow pcb
+\i (00:03:30) zoom in 3.755 4.790
+\i (00:03:30) trapsize 8
+\i (00:03:31) zoom out 1 
+\i (00:03:31) setwindow pcb
+\i (00:03:31) zoom out 3.496 4.337
+\i (00:03:31) trapsize 16
+\i (00:03:33) pick grid 3.216 2.346
+\t (00:03:33) last pick:  3.200 2.300
+\i (00:03:34) zoom out 1 
+\i (00:03:34) setwindow pcb
+\i (00:03:34) zoom out 3.337 3.653
+\i (00:03:34) trapsize 31
+\i (00:03:34) zoom out 1 
+\i (00:03:34) setwindow pcb
+\i (00:03:34) zoom out 3.338 2.589
+\i (00:03:34) trapsize 62
+\i (00:03:34) zoom out 1 
+\i (00:03:34) setwindow pcb
+\i (00:03:34) zoom out 3.338 -1.572
+\i (00:03:34) trapsize 125
+\i (00:03:34) zoom out 1 
+\i (00:03:34) setwindow pcb
+\i (00:03:34) zoom out -1.662 -9.899
+\i (00:03:34) trapsize 125
+\i (00:03:35) zoom in 1 
+\i (00:03:35) setwindow pcb
+\i (00:03:35) zoom in 3.106 -2.136
+\i (00:03:35) trapsize 62
+\i (00:03:35) zoom in 1 
+\i (00:03:35) setwindow pcb
+\i (00:03:35) zoom in 3.106 2.307
+\i (00:03:35) trapsize 31
+\i (00:03:38) pick grid 3.249 -2.323
+\t (00:03:38) last pick:  3.200 -2.300
+\i (00:03:39) zoom out 1 
+\i (00:03:39) setwindow pcb
+\i (00:03:39) zoom out 3.149 -0.981
+\i (00:03:39) trapsize 62
+\i (00:03:39) zoom out 1 
+\i (00:03:39) setwindow pcb
+\i (00:03:39) zoom out 3.150 -4.270
+\i (00:03:39) trapsize 125
+\i (00:03:40) zoom in 1 
+\i (00:03:40) setwindow pcb
+\i (00:03:40) zoom in -2.311 -2.036
+\i (00:03:40) trapsize 62
+\i (00:03:42) zoom in 1 
+\i (00:03:42) setwindow pcb
+\i (00:03:42) zoom in -3.147 -2.298
+\i (00:03:42) trapsize 31
+\i (00:03:44) pick grid -3.246 -2.298
+\t (00:03:44) last pick:  -3.200 -2.300
+\i (00:03:44) zoom out 1 
+\i (00:03:44) setwindow pcb
+\i (00:03:44) zoom out -3.315 -2.704
+\i (00:03:44) trapsize 62
+\i (00:03:46) zoom out 1 
+\i (00:03:46) setwindow pcb
+\i (00:03:46) zoom out -3.040 2.394
+\i (00:03:46) trapsize 125
+\i (00:03:46) zoom out 1 
+\i (00:03:46) setwindow pcb
+\i (00:03:46) zoom out -4.108 -1.961
+\i (00:03:46) trapsize 125
+\i (00:03:46) zoom out 1 
+\i (00:03:46) setwindow pcb
+\i (00:03:46) zoom out -4.108 -1.961
+\i (00:03:46) trapsize 125
+\i (00:03:47) zoom in 1 
+\i (00:03:47) setwindow pcb
+\i (00:03:47) zoom in -2.935 2.956
+\i (00:03:47) trapsize 62
+\i (00:03:48) zoom in 1 
+\i (00:03:48) setwindow pcb
+\i (00:03:48) zoom in -2.760 2.619
+\i (00:03:48) trapsize 31
+\i (00:03:50) pick grid -3.153 2.282
+\t (00:03:50) last pick:  -3.200 2.300
+\i (00:03:50) prepopup -3.228 2.282
+\i (00:03:50) done 
+\i (00:03:53) shape add rect 
+\i (00:03:56) pick grid -3.203 2.301
+\t (00:03:56) last pick:  -3.200 2.300
+\i (00:03:59) pick 0 0 
+\t (00:03:59) last pick:  0.000 0.000
+\i (00:04:00) prepopup -2.885 3.518
+\i (00:04:00) done 
+\i (00:04:01) zoom out 1 
+\i (00:04:01) setwindow pcb
+\i (00:04:01) zoom out -3.871 3.412
+\i (00:04:01) trapsize 62
+\i (00:04:04) change 
+\i (00:04:07) setwindow form.mini
+\i (00:04:07) FORM mini change_class 'PACKAGE GEOMETRY' 
+\i (00:04:08) FORM mini change_subclass PIN_NUMBER 
+\i (00:04:10) FORM mini text_name pin 
+\i (00:04:11) setwindow pcb
+\i (00:04:11) pick grid 4.691 1.957
+\t (00:04:11) last pick:  4.700 2.000
+\t (00:04:11) No DRC errors detected.
+\t (00:04:11) Changed 1 items out of 1 items found.
+\i (00:04:12) pick grid 4.654 -0.876
+\t (00:04:12) last pick:  4.700 -0.900
+\t (00:04:12) No DRC errors detected.
+\t (00:04:12) Changed 1 items out of 1 items found.
+\i (00:04:13) pick grid -4.619 2.082
+\t (00:04:13) last pick:  -4.600 2.100
+\t (00:04:13) No DRC errors detected.
+\t (00:04:13) Changed 1 items out of 1 items found.
+\i (00:04:14) pick grid -4.444 -0.426
+\t (00:04:14) last pick:  -4.400 -0.400
+\t (00:04:14) No DRC errors detected.
+\t (00:04:14) Changed 1 items out of 1 items found.
+\i (00:04:14) prepopup -2.784 3.530
+\i (00:04:15) done 
+\i (00:04:16) change 
+\i (00:04:19) setwindow form.mini
+\i (00:04:19) FORM mini change_class 'REF DES' 
+\i (00:04:20) FORM mini change_subclass ASSEMBLY_TOP 
+\i (00:04:24) FORM mini text_name asm 
+\i (00:04:25) setwindow pcb
+\i (00:04:25) pick grid 0.348 0.535
+\t (00:04:25) last pick:  0.300 0.500
+\t (00:04:25) No DRC errors detected.
+\t (00:04:25) Changed 1 items out of 1 items found.
+\i (00:04:26) prepopup 1.072 3.592
+\i (00:04:26) done 
+\i (00:04:30) move 
+\t (00:04:30) Select element(s) to move.
+\i (00:04:31) pick grid 7.499 0.435
+\t (00:04:31) last pick:  7.500 0.400
+\t (00:04:31) last pick:  6.412 0.000
+\t (00:04:31) Pick new location for the element(s).
+\i (00:04:33) pick grid 1.571 -1.762
+\t (00:04:33) last pick:  1.600 -1.800
+\i (00:04:33) prepopup 1.559 6.163
+\i (00:04:34) done 
+\i (00:04:36) step pkg map 
+\i (00:04:37) fillin yes 
+\i (00:04:47) setwindow form.pkgmap3d
+\i (00:04:47) FORM pkgmap3d namefilter_stp PC817.STEP 
+\i (00:04:48) FORM pkgmap3d stplist PC817.STEP 
+\i (00:04:51) FORM pkgmap3d rotation_z 90 
+\i (00:04:52) FORM pkgmap3d rotation_z 0 
+\i (00:04:52) FORM pkgmap3d rotation_y 90 
+\i (00:04:54) FORM pkgmap3d rotation_y 0 
+\i (00:04:54) FORM pkgmap3d rotation_x 90 
+\i (00:04:56) FORM pkgmap3d hide_board YES 
+\i (00:04:57) FORM pkgmap3d overlay YES 
+\i (00:04:59) FORM pkgmap3d rotation_z 90 
+\i (00:05:02) FORM pkgmap3d view_orientation Top 
+\i (00:05:05) FORM pkgmap3d rotation_z -90 
+\i (00:05:07) FORM pkgmap3d view_orientation Right 
+\i (00:05:10) FORM pkgmap3d offset_z 10 
+\i (00:05:11) FORM pkgmap3d offset_z 5 
+\i (00:05:13) FORM pkgmap3d offset_z 2 
+\i (00:05:16) FORM pkgmap3d offset_z 2.5 
+\i (00:05:18) FORM pkgmap3d offset_z 2.1 
+\i (00:05:21) FORM pkgmap3d view_orientation Top 
+\i (00:05:25) FORM pkgmap3d save_current  
+\i (00:05:27) FORM pkgmap3d done  
+\i (00:05:27) setwindow pcb
+\i (00:05:27) save 
+\i (00:05:28) fillin yes 
+\t (00:05:28) Symbol 'smd_4.psm' created.
+\i (00:05:29) exit 
+\t (00:05:29)     Journal end - Sat May 10 05:03:21 2025
diff --git a/smc/allegro.jrl,1 b/smc/allegro.jrl,1
index 575e227..7fcdee4 100644
--- a/smc/allegro.jrl,1
+++ b/smc/allegro.jrl,1
@@ -1,31 +1,32 @@
-\t (00:00:01) allegro 23.1 P001 Windows SPB 64-bit Edition
-\t (00:00:01)     Journal start - Fri Apr 25 17:19:11 2025
-\t (00:00:01)         Host=XEROLYSKINNER User=Xeroly Pid=10760 CPUs=16
-\t (00:00:01) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\smc\sot-23-6p.dra
-\t (00:00:01) 
-   (00:00:01) Loading axlcore.cxt 
-\t (00:00:01) Opening existing design...
-\i (00:00:01) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sot-23-6p"
-\d (00:00:01) Design opened: D:/Workspace/GitHub/pcb_lib/smc/sot-23-6p.dra
-\i (00:00:02) trapsize 328
-\i (00:00:02) trapsize 337
-\i (00:00:02) trapsize 328
-\i (00:00:02) trapsize 370
-\i (00:00:02) trapsize 255
-\i (00:00:03) delete 
-\i (00:00:05) pick grid 1.2217 3.1662
-\t (00:00:05) last pick:  1.2000 3.2000
-\t (00:00:05) Text "Last Edit:2024-4-6"
-\i (00:00:05) pick grid 2.7610 1.7798
-\t (00:00:05) last pick:  2.8000 1.8000
-\t (00:00:05) Text "Approved[1]"
-\i (00:00:06) pick grid 3.0464 0.1793
-\t (00:00:06) last pick:  3.0000 0.2000
-\t (00:00:06) Text "*Untested*"
-\i (00:00:06) prepopup 3.0464 0.1793
-\i (00:00:07) done 
-\i (00:00:07) save 
-\i (00:00:08) fillin yes 
-\t (00:00:08) Symbol 'sot-23-6p.psm' created.
-\i (00:00:09) exit 
-\t (00:00:09)     Journal end - Fri Apr 25 17:19:19 2025
+\t (00:00:02) allegro 23.1 P001 Windows SPB 64-bit Edition
+\t (00:00:02)     Journal start - Sat May  3 00:58:28 2025
+\t (00:00:02)         Host=XEROLYSKINNER User=Xeroly Pid=14560 CPUs=16
+\t (00:00:02) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\smc\led0603.dra
+\t (00:00:02) 
+   (00:00:02) Loading axlcore.cxt 
+\t (00:00:02) Opening existing design...
+\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged led0603
+\d (00:00:02) Design opened: D:/Workspace/GitHub/pcb_lib/smc/led0603.dra
+\i (00:00:02) trapsize 639
+\i (00:00:02) trapsize 657
+\i (00:00:02) trapsize 639
+\i (00:00:02) trapsize 679
+\i (00:00:02) trapsize 721
+\i (00:00:02) trapsize 486
+\i (00:00:06) delete 
+\i (00:00:08) pick grid 3.3549 1.6525
+\t (00:00:08) last pick:  3.4000 1.7000
+\t (00:00:08) Text "Last Edit:2024-03-17"
+\i (00:00:08) pick grid 2.2263 -1.7332
+\t (00:00:08) last pick:  2.2000 -1.7000
+\t (00:00:08) Text "Approved[1]"
+\i (00:00:09) pick grid 1.4480 -3.0953
+\t (00:00:09) last pick:  1.4000 -3.1000
+\t (00:00:09) Text "*Untested*"
+\i (00:00:09) prepopup 1.4480 -3.0953
+\i (00:00:10) done 
+\i (00:00:10) exit 
+\e (00:00:10) Do you want to save the changes you made to led0603.dra?
+\i (00:00:11) fillin yes 
+\t (00:00:11) Symbol 'led0603.psm' created.
+\t (00:00:11)     Journal end - Sat May  3 00:58:37 2025
diff --git a/smc/batch_drc.log b/smc/batch_drc.log
index 9b3c55e..2752f66 100644
--- a/smc/batch_drc.log
+++ b/smc/batch_drc.log
@@ -2,9 +2,9 @@
 (                                                                     )
 (    DRC Update                                                       )
 (                                                                     )
-(    Drawing          : ll34.dra                                      )
-(    Software Version : 17.4S035                                      )
-(    Date/Time        : Sat Aug  3 21:11:16 2024                      )
+(    Drawing          : sym_template.dra                              )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sat May 10 05:00:03 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/smc/batch_drc.log,1 b/smc/batch_drc.log,1
new file mode 100644
index 0000000..9b3c55e
--- /dev/null
+++ b/smc/batch_drc.log,1
@@ -0,0 +1,27 @@
+(---------------------------------------------------------------------)
+(                                                                     )
+(    DRC Update                                                       )
+(                                                                     )
+(    Drawing          : ll34.dra                                      )
+(    Software Version : 17.4S035                                      )
+(    Date/Time        : Sat Aug  3 21:11:16 2024                      )
+(                                                                     )
+(---------------------------------------------------------------------)
+
+
+ ========= check shapes                       0:00:00
+ ========= check standalone pins              0:00:00
+ ========= check symbols (pins,lines,text)    0:00:00
+ ========= check xnets                        0:00:00
+ ========= check nets                         0:00:00
+ ========= check standalone branches          0:00:00
+ ========= check standalone filled rectangles 0:00:00
+ ========= check standalone lines             0:00:00
+ ========= check standalone text              0:00:00
+ ========= check standalone rectangles        0:00:00
+
+ ..... Total number of DRC errors  0
+
+ ..... DRC update completed, total CPU time   0:00:00
+ *************************************************************************
+
diff --git a/smc/batch_drc.log,2 b/smc/batch_drc.log,2
new file mode 100644
index 0000000..2752f66
--- /dev/null
+++ b/smc/batch_drc.log,2
@@ -0,0 +1,27 @@
+(---------------------------------------------------------------------)
+(                                                                     )
+(    DRC Update                                                       )
+(                                                                     )
+(    Drawing          : sym_template.dra                              )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sat May 10 05:00:03 2025                      )
+(                                                                     )
+(---------------------------------------------------------------------)
+
+
+ ========= check shapes                       0:00:00
+ ========= check standalone pins              0:00:00
+ ========= check symbols (pins,lines,text)    0:00:00
+ ========= check xnets                        0:00:00
+ ========= check nets                         0:00:00
+ ========= check standalone branches          0:00:00
+ ========= check standalone filled rectangles 0:00:00
+ ========= check standalone lines             0:00:00
+ ========= check standalone text              0:00:00
+ ========= check standalone rectangles        0:00:00
+
+ ..... Total number of DRC errors  0
+
+ ..... DRC update completed, total CPU time   0:00:00
+ *************************************************************************
+
diff --git a/smc/downrev.log b/smc/downrev.log
index 1c083fc..bd8b9f2 100644
--- a/smc/downrev.log
+++ b/smc/downrev.log
@@ -2,9 +2,9 @@
 (                                                                     )
 (    Downrev Design                                                   )
 (                                                                     )
-(    Drawing          : sod-323.dra                                   )
+(    Drawing          : smd_4.dra                                     )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Fri Apr 25 17:20:00 2025                      )
+(    Date/Time        : Sat May 10 05:03:20 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/smc/downrev.log,1 b/smc/downrev.log,1
index 87ac460..5f49fa6 100644
--- a/smc/downrev.log,1
+++ b/smc/downrev.log,1
@@ -2,9 +2,9 @@
 (                                                                     )
 (    Downrev Design                                                   )
 (                                                                     )
-(    Drawing          : sot-23-6p.dra                                 )
+(    Drawing          : smd_4.dra                                     )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Fri Apr 25 17:19:18 2025                      )
+(    Date/Time        : Sat May 10 05:00:13 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/smc/downrev.log,2 b/smc/downrev.log,2
index 1c083fc..1678a77 100644
--- a/smc/downrev.log,2
+++ b/smc/downrev.log,2
@@ -2,9 +2,9 @@
 (                                                                     )
 (    Downrev Design                                                   )
 (                                                                     )
-(    Drawing          : sod-323.dra                                   )
+(    Drawing          : smd_4.dra                                     )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Fri Apr 25 17:20:00 2025                      )
+(    Date/Time        : Sat May 10 05:03:19 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/smc/downrev.log,3 b/smc/downrev.log,3
index 1c083fc..1678a77 100644
--- a/smc/downrev.log,3
+++ b/smc/downrev.log,3
@@ -2,9 +2,9 @@
 (                                                                     )
 (    Downrev Design                                                   )
 (                                                                     )
-(    Drawing          : sod-323.dra                                   )
+(    Drawing          : smd_4.dra                                     )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Fri Apr 25 17:20:00 2025                      )
+(    Date/Time        : Sat May 10 05:03:19 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
diff --git a/smc/led0603.dra b/smc/led0603.dra
index 87f57b3..4edc384 100644
Binary files a/smc/led0603.dra and b/smc/led0603.dra differ
diff --git a/smc/led0603.log b/smc/led0603.log
new file mode 100644
index 0000000..2e05dde
--- /dev/null
+++ b/smc/led0603.log
@@ -0,0 +1,23 @@
+(---------------------------------------------------------------------)
+(                                                                     )
+(    CREATE SYMBOL                                                    )
+(                                                                     )
+(    Drawing          : led0603.dra                                   )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sat May  3 00:58:37 2025                      )
+(                                                                     )
+(---------------------------------------------------------------------)
+
+
+Create Symbol of type: PACKAGE
+    Directory = D:/Workspace/GitHub/pcb_lib/smc
+    Name      = led0603.psm
+    User      = Xeroly
+    Machine   = XEROLYSKINNER
+
+
+Create symbol started.
+ 
+
+Create symbol completed.
+
diff --git a/smc/led0603.psm b/smc/led0603.psm
index bc47c3d..92fea37 100644
Binary files a/smc/led0603.psm and b/smc/led0603.psm differ
diff --git a/smc/master.tag b/smc/master.tag
index 7bbe3dc..e3d4887 100644
--- a/smc/master.tag
+++ b/smc/master.tag
@@ -1 +1 @@
-sod-323.dra
+smd_4.dra
diff --git a/smc/padstack_editor.jrl b/smc/padstack_editor.jrl
index 88da3fe..b3b19c0 100644
--- a/smc/padstack_editor.jrl
+++ b/smc/padstack_editor.jrl
@@ -1,7 +1,46 @@
-\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
-\t (00:00:00)     Journal start - Fri Apr 25 17:19:26 2025
-\t (00:00:00)         Host=XEROLYSKINNER User=Xeroly Pid=32596 CPUs=16
-\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\smc\sod-323.pad
-\t (00:00:00) 
-\d (00:00:02) QtSignal MainWindow Exit triggered
-\t (00:00:02)     Journal end - Fri Apr 25 17:19:28 2025
+\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
+\t (00:00:00)     Journal start - Sat May 10 04:54:55 2025
+\t (00:00:00)         Host=XEROLYSKINNER User=Xeroly Pid=28848 CPUs=16
+\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\smc\smd_4.pad
+\t (00:00:00) 
+\d (00:00:02) QtSignal GuidedTabsParent NewPads currentRowChanged 2
+\d (00:00:02) QtSignal GuidedTabsParent NewPads itemSelectionChanged Oblong
+\d (00:00:02) QtSignal GuidedTabsParent NewPads itemClicked Oblong
+\d (00:00:02) QtFillin Yes
+\d (00:00:05) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
+\d (00:00:06) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
+\d (00:00:06) QtSignal 1
+\d (00:00:07) QtSignal GuidedTabsParent GuidedTabs currentChanged Start
+\d (00:00:08) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
+\d (00:00:08) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
+\d (00:00:08) QtSignal 1
+\d (00:00:09) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
+\d (00:00:09) QtSignal 1
+\d (00:00:54) QtSignal GuidedDesignLayersTab PadWidth editingFinished "1.0000"
+\d (00:00:58) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
+\d (00:00:58) QtSignal 1
+\d (00:01:04) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
+\d (00:01:04) QtSignal 1
+\d (00:01:30) QtSignal GuidedDesignLayersTab PadHeight editingFinished "1.2500"
+\d (00:01:36) QtSignal GuidedDesignLayersTab PadWidth editingFinished "2.0000"
+\d (00:01:39) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
+\d (00:01:44) QtSignal GuidedMaskLayersTab PadWidth editingFinished "2.0000"
+\d (00:01:45) QtSignal GuidedMaskLayersTab PadHeight editingFinished "1.2500"
+\d (00:01:46) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
+\d (00:01:46) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 "Regular Pad" 2 1
+\d (00:01:50) QtSignal GuidedMaskLayersTab PadWidth editingFinished "2.0000"
+\d (00:01:51) QtSignal GuidedMaskLayersTab PadHeight editingFinished "1.2500"
+\d (00:01:54) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 0 "Regular Pad"
+\d (00:01:54) QtSignal GuidedMaskLayersTab LayersTable cellClicked 0 "Regular Pad" 0 1
+\d (00:02:30) QtSignal GuidedMaskLayersTab PadWidth editingFinished "2.0500"
+\d (00:02:32) QtSignal GuidedMaskLayersTab PadHeight editingFinished "1.3000"
+\d (00:02:32) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
+\d (00:02:39) QtSignal GuidedMaskLayersTab PadWidth editingFinished "2.5500"
+\d (00:02:42) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
+\d (00:02:42) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 "Regular Pad" 2 1
+\d (00:02:44) QtSignal GuidedMaskLayersTab PadWidth editingFinished "2.5000"
+\d (00:02:45) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
+\d (00:02:47) QtSignal GuidedDesignLayersTab PadWidth editingFinished "2.5000"
+\d (00:02:49) QtSignal MainWindow Save triggered
+\d (00:02:51) QtSignal MainWindow Exit triggered
+\t (00:02:51)     Journal end - Sat May 10 04:57:46 2025
diff --git a/smc/padstack_editor.jrl,1 b/smc/padstack_editor.jrl,1
index 49a296a..88da3fe 100644
--- a/smc/padstack_editor.jrl,1
+++ b/smc/padstack_editor.jrl,1
@@ -1,7 +1,7 @@
 \t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
-\t (00:00:00)     Journal start - Fri Apr 25 14:34:41 2025
-\t (00:00:00)         Host=XEROLYSKINNER User=Xeroly Pid=22968 CPUs=16
-\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\smc\1206.pad
+\t (00:00:00)     Journal start - Fri Apr 25 17:19:26 2025
+\t (00:00:00)         Host=XEROLYSKINNER User=Xeroly Pid=32596 CPUs=16
+\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\smc\sod-323.pad
 \t (00:00:00) 
 \d (00:00:02) QtSignal MainWindow Exit triggered
-\t (00:00:02)     Journal end - Fri Apr 25 14:34:42 2025
+\t (00:00:02)     Journal end - Fri Apr 25 17:19:28 2025
diff --git a/smc/param_read.log b/smc/param_read.log
index 804f299..25fa631 100644
--- a/smc/param_read.log
+++ b/smc/param_read.log
@@ -2,15 +2,15 @@
 (                                                                     )
 (    Parameter File READ                                              )
 (                                                                     )
-(    Drawing          : 3215.dra                                      )
+(    Drawing          : smd_4.dra                                     )
 (    Software Version : 23.1P001                                      )
-(    Date/Time        : Wed Apr 23 21:26:35 2025                      )
+(    Date/Time        : Sat May 10 05:00:13 2025                      )
 (                                                                     )
 (---------------------------------------------------------------------)
 
 
-	Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
-	Layout Name   : 3215.dra
+	Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
+	Layout Name   : D:/workspace/GitHub/pcb_lib/smc/smd_4.dra
 
 Reading...parameter_header:
 Reading...db_common_type:
diff --git a/smc/param_read.log,2 b/smc/param_read.log,2
new file mode 100644
index 0000000..804f299
--- /dev/null
+++ b/smc/param_read.log,2
@@ -0,0 +1,128 @@
+(---------------------------------------------------------------------)
+(                                                                     )
+(    Parameter File READ                                              )
+(                                                                     )
+(    Drawing          : 3215.dra                                      )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Wed Apr 23 21:26:35 2025                      )
+(                                                                     )
+(---------------------------------------------------------------------)
+
+
+	Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
+	Layout Name   : 3215.dra
+
+Reading...parameter_header:
+Reading...db_common_type:
+Reading...grid_parms_type:
+	WARNING: The value of element <etchcount> is not equal to the number of 
+		   user defined subclass under ETCH class. 
+
+Reading...UnusedPadsSuppressionSettings:
+Reading...artwork_film:
+	Reading...art_film_type:
+	Reading...art_film_block_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+Reading...artwork_film:
+	Reading...art_film_type:
+	Reading...art_film_block_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+Reading...artwork_film:
+	Reading...art_film_type:
+	Reading...art_film_block_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+Reading...artwork_film:
+	Reading...art_film_type:
+	Reading...art_film_block_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+Reading...artwork_film:
+	Reading...art_film_type:
+	Reading...art_film_block_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+Reading...artwork_film:
+	Reading...art_film_type:
+	Reading...art_film_block_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+Reading...artwork_film:
+	Reading...art_film_type:
+	Reading...art_film_block_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+Reading...artwork_film:
+	Reading...art_film_type:
+	Reading...art_film_block_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+Reading...artwork_film:
+	Reading...art_film_type:
+	Reading...art_film_block_type:
+	Reading...art_class_type:
+Reading...artwork_film:
+	Reading...art_film_type:
+	Reading...art_film_block_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+Reading...artwork_film:
+	Reading...art_film_type:
+	Reading...art_film_block_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+	Reading...art_class_type:
+Reading...artwork_film:
+	Reading...art_film_type:
+	Reading...art_film_block_type:
+	Reading...art_class_type:
+	WARNING: Unmatched Data - Field Name: subclass , Value: "SIGNEDTOP"
+	Reading...art_class_type:
+	Reading...art_class_type:
+Reading...artwork_film:
+	Reading...art_film_type:
+	Reading...art_film_block_type:
+	Reading...art_class_type:
+	WARNING: Unmatched Data - Field Name: subclass , Value: "SIGNEDBOTTOM"
+	Reading...art_class_type:
+	Reading...art_class_type:
+Reading...color_table_table:
+Reading...ColorParmType:
+Reading...profileCustomColors:
+Reading...text_size_table:
+Reading...drf_parm_type:
+Reading...av_parm_type:
+Reading...dynfill_parm_type:
+Reading...probe_parm_type:
+Reading...ifp_parm_type:
+Reading...ministat_parm_type:
+	WARNING: Unmatched Data - Field Name: acon_active_sc , Value: "SIGNEDTOP"
+Reading...ats_parm_type:
+Reading...placement_parameter_type:
+Reading...backdrill_parm_type:
+Reading...backdrill_parm_type:
+Reading...backdrill_parm_type:
+Reading...backdrill_parm_type:
+
+
+..... Total number of errors: 0.
+..... Total number of warnings: 4.
diff --git a/smc/smd_4.dra b/smc/smd_4.dra
new file mode 100644
index 0000000..b5c93d6
Binary files /dev/null and b/smc/smd_4.dra differ
diff --git a/smc/smd_4.log b/smc/smd_4.log
new file mode 100644
index 0000000..a0d39d3
--- /dev/null
+++ b/smc/smd_4.log
@@ -0,0 +1,23 @@
+(---------------------------------------------------------------------)
+(                                                                     )
+(    CREATE SYMBOL                                                    )
+(                                                                     )
+(    Drawing          : smd_4.dra                                     )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sat May 10 05:03:20 2025                      )
+(                                                                     )
+(---------------------------------------------------------------------)
+
+
+Create Symbol of type: PACKAGE
+    Directory = D:/workspace/GitHub/pcb_lib/smc
+    Name      = smd_4.psm
+    User      = Xeroly
+    Machine   = XEROLYSKINNER
+
+
+Create symbol started.
+ 
+
+Create symbol completed.
+
diff --git a/smc/smd_4.log,1 b/smc/smd_4.log,1
new file mode 100644
index 0000000..0a07eef
--- /dev/null
+++ b/smc/smd_4.log,1
@@ -0,0 +1,23 @@
+(---------------------------------------------------------------------)
+(                                                                     )
+(    CREATE SYMBOL                                                    )
+(                                                                     )
+(    Drawing          : smd_4.dra                                     )
+(    Software Version : 23.1P001                                      )
+(    Date/Time        : Sat May 10 05:00:03 2025                      )
+(                                                                     )
+(---------------------------------------------------------------------)
+
+
+Create Symbol of type: PACKAGE
+    Directory = D:/workspace/GitHub/pcb_lib/smc
+    Name      = smd_4.psm
+    User      = Xeroly
+    Machine   = XEROLYSKINNER
+
+
+Create symbol started.
+ 
+
+Create symbol completed.
+
diff --git a/smc/smd_4.pad b/smc/smd_4.pad
new file mode 100644
index 0000000..5b71dd2
Binary files /dev/null and b/smc/smd_4.pad differ
diff --git a/smc/smd_4.psm b/smc/smd_4.psm
new file mode 100644
index 0000000..1946aea
Binary files /dev/null and b/smc/smd_4.psm differ
diff --git a/smc/stepFacetFiles4Map/PC817.xml b/smc/stepFacetFiles4Map/PC817.xml
new file mode 100644
index 0000000..502308f
--- /dev/null
+++ b/smc/stepFacetFiles4Map/PC817.xml
@@ -0,0 +1,11930 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<step-assembly root="id3947">
+<product id="id3947" name="User Library-PC817_Gullwing" shape="id4463" children="id1112 id1766 id333 id4097 id3578"/>
+<product id="id1112" name="Gullwing Pin" shape="id3614"/>
+<product id="id1766" name="Gullwing Pin_MIR" shape="id4685"/>
+<product id="id333" name="Gullwing Pin_MIR1" shape="id4176"/>
+<product id="id4097" name="Gullwing Pin_MIR_MIR" shape="id802"/>
+<product id="id3578" name="PC817 Body" shape="id3665"/>
+<shape id="id4463" unit="mm 0.001000">
+    <child ref="id3665" xform="1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1"/>
+    <child ref="id3614" xform="1 0 0 0 0 1 0 0 0 0 1 0 -13.5652 -2.10147 -0.272215 1"/>
+    <child ref="id4685" xform="-1 0 0 0 0 1 2.35594e-29 0 0 2.35594e-29 -1 0 13.5652 -2.10147 -0.272215 1"/>
+    <child ref="id4176" xform="1 0 0 0 0 1 0 0 0 0 1 0 -13.5652 -2.10147 0.272215 1"/>
+    <child ref="id802" xform="-1 0 0 0 0 1 0 0 0 0 -1 0 13.5652 -2.10147 0.272215 1"/>
+</shape>
+<shape id="id3665" unit="mm 0.001000">
+    <child ref="id2320" xform="1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1"/>
+</shape>
+<shape id="id2320" unit="mm 0.001000" shell="id704"/>
+<shape id="id3614" unit="mm 0.001000">
+    <child ref="id4497" xform="1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1"/>
+</shape>
+<shape id="id4497" unit="mm 0.001000" shell="id2510"/>
+<shape id="id4685" unit="mm 0.001000">
+    <child ref="id3854" xform="1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1"/>
+</shape>
+<shape id="id3854" unit="mm 0.001000" shell="id2351"/>
+<shape id="id4176" unit="mm 0.001000">
+    <child ref="id712" xform="1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1"/>
+</shape>
+<shape id="id712" unit="mm 0.001000" shell="id693"/>
+<shape id="id802" unit="mm 0.001000">
+    <child ref="id4797" xform="1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1"/>
+</shape>
+<shape id="id4797" unit="mm 0.001000" shell="id730"/>
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+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+        </f>
+        <f v="97 201 200" fn="-2.96059473233378e-15 1 -5.11367645965126e-15">
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+        </f>
+        <f v="97 200 17" fn="0 1 0">
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+        </f>
+        <f v="96 201 97" fn="-1.48029736616689e-15 1 -3.0279047178605e-29">
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+        </f>
+        <f v="96 139 201" fn="-1.48029736616687e-15 1 0">
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+        </f>
+        <f v="205 96 95" fn="0 1 0">
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+        </f>
+        <f v="205 95 16" fn="0 1 0">
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+        </f>
+        <f v="204 96 205" fn="-2.96059473233374e-15 1 2.55683822982559e-15">
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+        </f>
+        <f v="203 139 204" fn="-2.96059473233374e-15 1 -2.55683822982559e-15">
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+        </f>
+        <f v="140 203 27" fn="0 1 -0">
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+        </f>
+        <f v="139 203 140" fn="0 1 -0">
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+        </f>
+        <f v="138 202 139" fn="0 1 -0">
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+            <n d="0 1 0"/>
+        </f>
+    </facets>
+</shell>
+</step-assembly>
diff --git a/smc/stepFacetFiles4Map/stepFileInfo.txt b/smc/stepFacetFiles4Map/stepFileInfo.txt
index fcd1f77..4fed22e 100644
--- a/smc/stepFacetFiles4Map/stepFileInfo.txt
+++ b/smc/stepFacetFiles4Map/stepFileInfo.txt
@@ -29,6 +29,7 @@ ll41.STEP ! 101103 ! 1722691967
 f0603.step ! 196072 ! 1712591701
 R0603.step ! 652348 ! 1710578258
 STL90N10F7.STEP ! 62745 ! 1711513016
+PC817.STEP ! 371619 ! 1746758364
 R0805.step ! 87675 ! 1722551163
 C0805.stp ! 348325 ! 1600360029
 0603.step ! 57899 ! 1568096060
diff --git a/smc/stepFacetFiles4Map/stepFileInfo.txt,1 b/smc/stepFacetFiles4Map/stepFileInfo.txt,1
index dcc3004..fcd1f77 100644
--- a/smc/stepFacetFiles4Map/stepFileInfo.txt,1
+++ b/smc/stepFacetFiles4Map/stepFileInfo.txt,1
@@ -7,6 +7,7 @@ rp0603.step ! 814212 ! 1711676791
 CONN-2P.STEP ! 360048 ! 1712416291
 C0603.stp ! 74996 ! 1710578258
 ltv-8x7.STEP ! 395538 ! 1712545177
+sod123w.step ! 446479 ! 1745413979
 SMA-DO-214AC.step ! 213070 ! 1710578258
 SMC.step ! 207133 ! 1710578258
 TS-POINT.STEP ! 23849 ! 1710578258