更加标准化,修改了一下颜色
每一张封装加入三个参数: LAST EDIT:最后修改时间 Approved:审核次数,最少是1(画完的时候简单审核一下) *UNTESTED*:如果该封装没有被实际打出来测试过,就会有这个标识
This commit is contained in:
29
other/dangling_lines.rpt
Normal file
29
other/dangling_lines.rpt
Normal file
@@ -0,0 +1,29 @@
|
||||
(---------------------------------------------------------------------)
|
||||
( )
|
||||
( Dangling Line, Via and Antenna Report )
|
||||
( )
|
||||
( Drawing : type-c.dra )
|
||||
( Software Version : 17.4S035 )
|
||||
( Date/Time : Sat Mar 16 19:19:00 2024 )
|
||||
( )
|
||||
(---------------------------------------------------------------------)
|
||||
|
||||
|
||||
Report methodology:
|
||||
- Dangling lines have at least one end not connected.
|
||||
- Dangling vias have one or no connection
|
||||
- Plus are not a test, thieving or netshort property via.
|
||||
- Antenna vias do not have connections on their start and end layers.
|
||||
- Plus they are not a thieving vias.
|
||||
- Optionally, VOLTAGE nets, testvias and through vias can be suppressed with
|
||||
the environment variable report_antennavia.
|
||||
- Section may be suppressed by variable report_noantennavia.
|
||||
- Not part of the current partition.
|
||||
- To suppress items in dangle report add the OK_DANGLE property to the via
|
||||
or connect line.
|
||||
|
||||
|
||||
<< Summary >>
|
||||
Total dangling lines: 0
|
||||
Total dangling vias: 0
|
||||
Total antenna vias: 0
|
||||
29
other/dangling_lines.rpt,1
Normal file
29
other/dangling_lines.rpt,1
Normal file
@@ -0,0 +1,29 @@
|
||||
(---------------------------------------------------------------------)
|
||||
( )
|
||||
( Dangling Line, Via and Antenna Report )
|
||||
( )
|
||||
( Drawing : type-c.dra )
|
||||
( Software Version : 17.4S035 )
|
||||
( Date/Time : Sat Mar 16 19:17:19 2024 )
|
||||
( )
|
||||
(---------------------------------------------------------------------)
|
||||
|
||||
|
||||
Report methodology:
|
||||
- Dangling lines have at least one end not connected.
|
||||
- Dangling vias have one or no connection
|
||||
- Plus are not a test, thieving or netshort property via.
|
||||
- Antenna vias do not have connections on their start and end layers.
|
||||
- Plus they are not a thieving vias.
|
||||
- Optionally, VOLTAGE nets, testvias and through vias can be suppressed with
|
||||
the environment variable report_antennavia.
|
||||
- Section may be suppressed by variable report_noantennavia.
|
||||
- Not part of the current partition.
|
||||
- To suppress items in dangle report add the OK_DANGLE property to the via
|
||||
or connect line.
|
||||
|
||||
|
||||
<< Summary >>
|
||||
Total dangling lines: 0
|
||||
Total dangling vias: 0
|
||||
Total antenna vias: 0
|
||||
80912
other/stepFacetFiles4Map/TYPE-C.xml
Normal file
80912
other/stepFacetFiles4Map/TYPE-C.xml
Normal file
File diff suppressed because it is too large
Load Diff
3
other/stepFacetFiles4Map/stepFileInfo.txt
Normal file
3
other/stepFacetFiles4Map/stepFileInfo.txt
Normal file
@@ -0,0 +1,3 @@
|
||||
#STEP_FILE ! FILE_SIZE ! MOD_TIME
|
||||
|
||||
TYPE-C.stp ! 1362496 ! 1710578258
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
other/type-c.dra
BIN
other/type-c.dra
Binary file not shown.
BIN
other/type-c.psm
BIN
other/type-c.psm
Binary file not shown.
Reference in New Issue
Block a user