更加标准化，修改了一下颜色

每一张封装加入三个参数： LAST EDIT：最后修改时间 Approved：审核次数，最少是1（画完的时候简单审核一下） *UNTESTED*:如果该封装没有被实际打出来测试过，就会有这个标识
2024-03-16 22:21:25 +08:00
parent caf38e1e9f
commit d1a2e95934
73 changed files with 873088 additions and 723 deletions
--- a/3D/CAP-SMD-SVP-10_0x12_6.STEP
+++ b/3D/CAP-SMD-SVP-10_0x12_6.STEP
--- a/3D/CAP-SMD-SVP-4_0x5_4.STEP
+++ b/3D/CAP-SMD-SVP-4_0x5_4.STEP
--- a/3D/CAP-SMD-SVP-5_0x5_9.STEP
+++ b/3D/CAP-SMD-SVP-5_0x5_9.STEP
--- a/3D/CAP-SMD-SVP-6_3x5_9.STEP
+++ b/3D/CAP-SMD-SVP-6_3x5_9.STEP
--- a/3D/CAP-SMD-SVP-8_0x6_9.STEP
+++ b/3D/CAP-SMD-SVP-8_0x6_9.STEP
--- a/3D/SOIC-14.step
+++ b/3D/SOIC-14.step
--- a/3D/sop-8.STEP
+++ b/3D/sop-8.STEP
--- a/XerolySkinner.prm
+++ b/XerolySkinner.prm
--- a/basic_lib/BASIC_OBJ.OLB
+++ b/basic_lib/BASIC_OBJ.OLB
--- a/basic_lib/BASIC_OBJ_0.OBK
+++ b/basic_lib/BASIC_OBJ_0.OBK
--- a/cap_smd/cap-smd-4x5_4.dra
+++ b/cap_smd/cap-smd-4x5_4.dra
--- a/cap_smd/cap-smd-4x5_4.psm
+++ b/cap_smd/cap-smd-4x5_4.psm
--- a/cap_smd/cap-smd-5x5_4.dra
+++ b/cap_smd/cap-smd-5x5_4.dra
--- a/cap_smd/cap-smd-5x5_4.psm
+++ b/cap_smd/cap-smd-5x5_4.psm
--- a/cap_smd/cap-smd-6_3x5_4.dra
+++ b/cap_smd/cap-smd-6_3x5_4.dra
--- a/cap_smd/cap-smd-6_3x5_4.psm
+++ b/cap_smd/cap-smd-6_3x5_4.psm
--- a/cap_smd/cap-smd-N5.pad
+++ b/cap_smd/cap-smd-N5.pad
--- a/cap_smd/stepFacetFiles4Map/CONN-2P-P5.xml
+++ b/cap_smd/stepFacetFiles4Map/CONN-2P-P5.xml
--- a/cap_smd/stepFacetFiles4Map/D8-L.xml
+++ b/cap_smd/stepFacetFiles4Map/D8-L.xml
--- a/cap_smd/stepFacetFiles4Map/cap-smd-4x5_4.xml
+++ b/cap_smd/stepFacetFiles4Map/cap-smd-4x5_4.xml
--- a/cap_smd/stepFacetFiles4Map/cap-smd-5x5_4.xml
+++ b/cap_smd/stepFacetFiles4Map/cap-smd-5x5_4.xml
--- a/cap_smd/stepFacetFiles4Map/stepFileInfo.txt
+++ b/cap_smd/stepFacetFiles4Map/stepFileInfo.txt
@@ -0,0 +1,6 @@
+#STEP_FILE ! FILE_SIZE ! MOD_TIME
+
+cap-smd-4x5_4.STEP ! 253153 ! 1710578258
+D8-L.step ! 282667 ! 1568096060
+cap-smd-5x5_4.STEP ! 236170 ! 1710578258
+CONN-2P-P5.step ! 1193777 ! 1710578258
--- a/cap_smd/stepFacetFiles4Map/stepFileInfo.txt,1
+++ b/cap_smd/stepFacetFiles4Map/stepFileInfo.txt,1
@@ -0,0 +1,6 @@
+#STEP_FILE ! FILE_SIZE ! MOD_TIME
+
+cap-smd-4x5_4.STEP ! 253153 ! 1710578258
+D8-L.step ! 282667 ! 1568096060
+cap-smd-5x5_4.STEP ! 236170 ! 1710578258
+CONN-2P-P5.step ! 1193777 ! 1710578258
--- a/chip/lqfp100.dra
+++ b/chip/lqfp100.dra
--- a/chip/lqfp100.pad
+++ b/chip/lqfp100.pad
--- a/chip/lqfp100.psm
+++ b/chip/lqfp100.psm
--- a/chip/lqfp64.dra
+++ b/chip/lqfp64.dra
--- a/chip/lqfp64.pad
+++ b/chip/lqfp64.pad
--- a/chip/lqfp64.psm
+++ b/chip/lqfp64.psm
--- a/chip/sop-14.dra
+++ b/chip/sop-14.dra
--- a/chip/sop-14.pad
+++ b/chip/sop-14.pad
--- a/chip/sop-14.psm
+++ b/chip/sop-14.psm
--- a/chip/sop-8-gnd.dra
+++ b/chip/sop-8-gnd.dra
--- a/chip/sop-8-gnd.psm
+++ b/chip/sop-8-gnd.psm
--- a/chip/sop-8.dra
+++ b/chip/sop-8.dra
--- a/chip/sop-8.pad
+++ b/chip/sop-8.pad
--- a/chip/sop-8.psm
+++ b/chip/sop-8.psm
--- a/chip/sop-8_gnd.pad
+++ b/chip/sop-8_gnd.pad
--- a/chip/stepFacetFiles4Map/D8-L.xml
+++ b/chip/stepFacetFiles4Map/D8-L.xml
--- a/chip/stepFacetFiles4Map/D8-M.xml
+++ b/chip/stepFacetFiles4Map/D8-M.xml
--- a/chip/stepFacetFiles4Map/DIP_2x5.xml
+++ b/chip/stepFacetFiles4Map/DIP_2x5.xml
--- a/chip/stepFacetFiles4Map/ESP-01.xml
+++ b/chip/stepFacetFiles4Map/ESP-01.xml
--- a/chip/stepFacetFiles4Map/KEY_SOT_P2.xml
+++ b/chip/stepFacetFiles4Map/KEY_SOT_P2.xml
--- a/chip/stepFacetFiles4Map/LED_0603_G.xml
+++ b/chip/stepFacetFiles4Map/LED_0603_G.xml
--- a/chip/stepFacetFiles4Map/LQFP64.xml
+++ b/chip/stepFacetFiles4Map/LQFP64.xml
--- a/chip/stepFacetFiles4Map/sop-14.xml
+++ b/chip/stepFacetFiles4Map/sop-14.xml
--- a/chip/stepFacetFiles4Map/sop-8.xml
+++ b/chip/stepFacetFiles4Map/sop-8.xml
--- a/chip/stepFacetFiles4Map/stepFileInfo.txt
+++ b/chip/stepFacetFiles4Map/stepFileInfo.txt
@@ -0,0 +1,11 @@
+#STEP_FILE ! FILE_SIZE ! MOD_TIME
+
+D8-M.step ! 282667 ! 1568096060
+D8-L.step ! 282667 ! 1568096060
+DIP_2x5.step ! 720870 ! 1710578258
+ESP-01.step ! 2352878 ! 1710578258
+LQFP64.step ! 14347354 ! 1710578258
+sop-8.STEP ! 273188 ! 1710578258
+LED_0603_G.STEP ! 178570 ! 1710578258
+KEY_SOT_P2.step ! 151224 ! 1710578258
+sop-14.step ! 521672 ! 1710578258
--- a/chip/stepFacetFiles4Map/stepFileInfo.txt,1
+++ b/chip/stepFacetFiles4Map/stepFileInfo.txt,1
@@ -0,0 +1,11 @@
+#STEP_FILE ! FILE_SIZE ! MOD_TIME
+
+D8-M.step ! 282667 ! 1568096060
+D8-L.step ! 282667 ! 1568096060
+DIP_2x5.step ! 720870 ! 1710578258
+ESP-01.step ! 2352878 ! 1710578258
+LQFP64.step ! 14347354 ! 1710578258
+sop-8.STEP ! 273188 ! 1710578258
+LED_0603_G.STEP ! 178570 ! 1710578258
+KEY_SOT_P2.step ! 151224 ! 1710578258
+sop-14.step ! 521672 ! 1710578258
--- a/hold/.html
+++ b/hold/.html
@@ -0,0 +1,21 @@
+<body>
+<large>
+<br><b>Padstack:</b> thr-0r65-none<body>
+<large>
+<br><b>Software Version:</b>
+17.4<body>
+<large>
+<br><b>Date/Time</b>: 2024/03/16 17:58:42<br>
+<hr style=border-top: dashed 2px; />
+<blockquote>
+<br><table border=1>
+<tr>
+<th>Severity</th>
+<th>Message</th>
+</tr>
+<tr>
+<td width=200>Warning</td>
+<td width=200>Drill hole size is equal to or larger than smallest pad size.  Pad will be drilled away.</td>
+</tr>
+</table></br>
+</blockquote>
--- a/hold/thr-0r65-none.pad
+++ b/hold/thr-0r65-none.pad
--- a/hold/thr-1r02_1r8.dra
+++ b/hold/thr-1r02_1r8.dra
--- a/hold/thr-1r02_1r8.pad
+++ b/hold/thr-1r02_1r8.pad
--- a/hold/via_0_2-f.pad
+++ b/hold/via_0_2-f.pad
--- a/hold/via_0_2.pad
+++ b/hold/via_0_2.pad
--- a/hold/via_0_25-f.pad
+++ b/hold/via_0_25-f.pad
--- a/hold/via_0_25.pad
+++ b/hold/via_0_25.pad
--- a/other/dangling_lines.rpt
+++ b/other/dangling_lines.rpt
@@ -0,0 +1,29 @@
+(---------------------------------------------------------------------)
+(                                                                     )
+(    Dangling Line, Via and Antenna Report                            )
+(                                                                     )
+(    Drawing          : type-c.dra                                    )
+(    Software Version : 17.4S035                                      )
+(    Date/Time        : Sat Mar 16 19:19:00 2024                      )
+(                                                                     )
+(---------------------------------------------------------------------)
+
+
+Report methodology:
+  - Dangling lines have at least one end not connected.
+  - Dangling vias have one or no connection
+      - Plus are not a test, thieving or netshort property via.
+  - Antenna vias do not have connections on their start and end layers.
+      - Plus they are not a thieving vias.
+      - Optionally, VOLTAGE nets, testvias and through vias can be suppressed with
+        the environment variable report_antennavia.
+      - Section may be suppressed by variable report_noantennavia.
+  - Not part of the current partition.
+  - To suppress items in dangle report add the OK_DANGLE property to the via
+    or connect line.
+
+
+<< Summary >>
+  Total dangling lines:       0
+  Total dangling vias:        0
+  Total antenna vias:         0
--- a/other/dangling_lines.rpt,1
+++ b/other/dangling_lines.rpt,1
@@ -0,0 +1,29 @@
+(---------------------------------------------------------------------)
+(                                                                     )
+(    Dangling Line, Via and Antenna Report                            )
+(                                                                     )
+(    Drawing          : type-c.dra                                    )
+(    Software Version : 17.4S035                                      )
+(    Date/Time        : Sat Mar 16 19:17:19 2024                      )
+(                                                                     )
+(---------------------------------------------------------------------)
+
+
+Report methodology:
+  - Dangling lines have at least one end not connected.
+  - Dangling vias have one or no connection
+      - Plus are not a test, thieving or netshort property via.
+  - Antenna vias do not have connections on their start and end layers.
+      - Plus they are not a thieving vias.
+      - Optionally, VOLTAGE nets, testvias and through vias can be suppressed with
+        the environment variable report_antennavia.
+      - Section may be suppressed by variable report_noantennavia.
+  - Not part of the current partition.
+  - To suppress items in dangle report add the OK_DANGLE property to the via
+    or connect line.
+
+
+<< Summary >>
+  Total dangling lines:       0
+  Total dangling vias:        0
+  Total antenna vias:         0
--- a/other/stepFacetFiles4Map/TYPE-C.xml
+++ b/other/stepFacetFiles4Map/TYPE-C.xml
--- a/other/stepFacetFiles4Map/stepFileInfo.txt
+++ b/other/stepFacetFiles4Map/stepFileInfo.txt
@@ -0,0 +1,3 @@
+#STEP_FILE ! FILE_SIZE ! MOD_TIME
+
+TYPE-C.stp ! 1362496 ! 1710578258
--- a/other/type-c-1.pad
+++ b/other/type-c-1.pad
--- a/other/type-c-2.pad
+++ b/other/type-c-2.pad
--- a/other/type-c-3.pad
+++ b/other/type-c-3.pad
--- a/other/type-c-4.pad
+++ b/other/type-c-4.pad
--- a/other/type-c.dra
+++ b/other/type-c.dra
--- a/other/type-c.psm
+++ b/other/type-c.psm
--- a/smc/sop-14.psm
+++ b/smc/sop-14.psm
--- a/smc/sop-8-gnd.dra
+++ b/smc/sop-8-gnd.dra
--- a/thr/thr_dip_2x5.dra
+++ b/thr/thr_dip_2x5.dra
--- a/thr/thr_dip_2x5.psm
+++ b/thr/thr_dip_2x5.psm
--- a/thr/thr_dip_2x6.dra
+++ b/thr/thr_dip_2x6.dra
--- a/thr/thr_dip_2x6.psm
+++ b/thr/thr_dip_2x6.psm