\t (00:00:01) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:01)     Journal start - Sun Apr 27 22:01:59 2025
\t (00:00:01)         Host=XEROLYSKINNER User=Xeroly Pid=40776 CPUs=16
\t (00:00:01) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\thr\thr_wh-lte-7s1.dra
\t (00:00:01) 
   (00:00:01) Loading axlcore.cxt 
\t (00:00:01) Opening existing design...
\i (00:00:01) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "thr_wh-lte-7s1"
\d (00:00:01) Design opened: D:/Workspace/GitHub/pcb_lib/thr/thr_wh-lte-7s1.dra
\t (00:00:02) Grids are drawn 0.4000, 0.4000 apart for enhanced viewing.
\i (00:00:02) trapsize 2935
\i (00:00:02) trapsize 3019
\i (00:00:02) trapsize 2935
\i (00:00:02) trapsize 3259
\t (00:00:02) Grids are drawn 0.4000, 0.4000 apart for enhanced viewing.
\i (00:00:02) trapsize 3259
\t (00:00:02) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:02) trapsize 2106
\i (00:00:05) save 
\i (00:00:06) fillin yes 
\t (00:00:07) Symbol 'thr_wh-lte-7s1.psm' created.
\i (00:00:09) exit 
\t (00:00:09)     Journal end - Sun Apr 27 22:02:07 2025