\t (00:00:01) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:01)     Journal start - Fri Apr 25 17:20:39 2025
\t (00:00:01)         Host=XEROLYSKINNER User=Xeroly Pid=23996 CPUs=16
\t (00:00:01) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\cap_smd\cap-smd-6_3x5_4.dra
\t (00:00:01) 
   (00:00:01) Loading axlcore.cxt 
\t (00:00:01) Opening existing design...
\i (00:00:01) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "cap-smd-6_3x5_4"
\d (00:00:01) Design opened: D:/Workspace/GitHub/pcb_lib/cap_smd/cap-smd-6_3x5_4.dra
\i (00:00:02) trapsize 586
\i (00:00:02) trapsize 603
\i (00:00:02) trapsize 586
\i (00:00:02) trapsize 828
\i (00:00:02) trapsize 570
\i (00:00:03) delete 
\i (00:00:04) pick grid 5.9783 5.8787
\t (00:00:04) last pick:  6.0000 5.9000
\t (00:00:04) Text "Last Edit:2024-3-16"
\i (00:00:05) pick grid 5.7505 4.0670
\t (00:00:05) last pick:  5.8000 4.1000
\t (00:00:05) Text "Approved[1]"
\i (00:00:05) pick grid 5.7618 2.6655
\t (00:00:05) last pick:  5.8000 2.7000
\t (00:00:05) Text "*Untested*"
\i (00:00:05) prepopup 5.7618 2.6655
\i (00:00:06) done 
\i (00:00:06) save 
\i (00:00:07) fillin yes 
\t (00:00:07) Symbol 'cap-smd-6_3x5_4.psm' created.
\i (00:00:08) exit 
\t (00:00:08)     Journal end - Fri Apr 25 17:20:45 2025