\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02)     Journal start - Fri Aug  2 06:02:52 2024
\t (00:00:02)         Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=12676 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\chip\sop-16.dra
\t (00:00:02) 
   (00:00:02) Loading axlcore.cxt 
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sop-16"
\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/chip/sop-16.dra
\t (00:00:02) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
\i (00:00:02) trapsize 43
\i (00:00:02) trapsize 44
\i (00:00:03) trapsize 43
\i (00:00:03) trapsize 38
\i (00:00:03) trapsize 39
\i (00:00:03) trapsize 40
\t (00:00:03) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
\i (00:00:03) trapsize 41
\i (00:00:06) step pkg map 
\i (00:00:06) fillin yes 
\i (00:00:12) setwindow form.pkgmap3d
\i (00:00:12) FORM pkgmap3d stplist SOP-16.STEP 
\i (00:00:15) FORM pkgmap3d overlay YES 
\i (00:00:16) FORM pkgmap3d hide_board YES 
\i (00:00:17) FORM pkgmap3d hide_board NO 
\i (00:00:20) FORM pkgmap3d view_orientation Top 
\i (00:00:23) FORM pkgmap3d save_current  
\i (00:00:24) FORM pkgmap3d done  
\i (00:00:27) setwindow pcb
\i (00:00:27) save 
\i (00:00:27) fillin yes 
\t (00:00:27) Symbol 'sop-16.psm' created.
\i (00:00:28) exit 
\t (00:00:28)     Journal end - Fri Aug  2 06:03:18 2024