Files
pcb_lib/chip/allegro.jrl
2025-09-27 11:01:31 +08:00

21 lines
950 B
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\t (00:00:02) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Sat May 10 04:57:54 2025
\t (00:00:02) Host=XEROLYSKINNER User=Xeroly Pid=35792 CPUs=16
\t (00:00:02) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:05) Opening existing design...
\i (00:00:05) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "wsoic-8"
\d (00:00:05) Design opened: D:/workspace/GitHub/pcb_lib/chip/wsoic-8.dra
\t (00:00:05) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
\i (00:00:05) trapsize 71
\i (00:00:05) trapsize 73
\i (00:00:06) trapsize 71
\i (00:00:06) trapsize 76
\t (00:00:06) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
\i (00:00:06) trapsize 79
\i (00:00:06) trapsize 53
\i (00:00:20) new
\i (00:00:37) newdrawfillin "smd_4.dra" "Package Symbol (Wizard)"
\t (00:00:37) Journal end - Sat May 10 04:58:28 2025