75 lines
2.2 KiB
Plaintext
75 lines
2.2 KiB
Plaintext
(ExpressProject "template"
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(ProjectVersion "19981106")
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(SoftwareVersion "23.1 P001 (4147275) [9/30/2023]-[04/10/24]")
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(ProjectType "PCB")
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(Folder "Design Resources"
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(Folder "Library")
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("Allegro Netlist Directory" "allegro")
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(DOCKED "TRUE")
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(DOCKING_POSITION "59420")
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(NoModify)
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(File ".\template.dsn"
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(Type "Schematic Design"))
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(BuildFileAddedOrDeleted "x")
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(CompileFileAddedOrDeleted "x"))
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(Folder "Layout")
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(Folder "Outputs")
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(Folder "Referenced Projects")
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(Folder "PSpice Resources"
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(Folder "Simulation Profiles")
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(Folder "Model Libraries"
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(Sort User))
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(Folder "Stimulus Files"
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(Sort User))
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(Folder "Include Files"
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(Sort User)))
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(Folder "Logs")
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(PartMRUSelector)
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(GlobalState
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(FileView
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(Path "Design Resources")
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(Path "Design Resources"
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"d:\workspace\github\pcb_lib\orcad_template\template.dsn")
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(Path "Design Resources"
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"d:\workspace\github\pcb_lib\orcad_template\template.dsn" "TEMPLATE")
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(Select "Design Resources"
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"d:\workspace\github\pcb_lib\orcad_template\template.dsn" "TEMPLATE"
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"2:USB-CNT"))
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(HierarchyView)
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(Doc
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(Type "COrCapturePMDoc")
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(Frame
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(Placement "44 0 1 -1 -1 -1 -1 0 200 0 774"))
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(Tab 0))
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(Doc
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(Type "COrSchematicDoc")
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(Frame
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(Placement "44 0 1 -1 -1 -1 -1 5 1413 28 796")
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(Scroll "-203 -8")
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(Zoom "100")
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(Occurrence "/"))
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(Path "D:\WORKSPACE\GITHUB\PCB_LIB\ORCAD_TEMPLATE\TEMPLATE.DSN")
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(Schematic "TEMPLATE")
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(Page "3:485"))
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(Doc
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(Type "COrSchematicDoc")
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(Frame
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(Placement "44 0 1 -1 -1 -1 -1 5 1413 28 796")
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(Scroll "0 0")
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(Zoom "100")
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(Occurrence "/"))
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(Path "D:\WORKSPACE\GITHUB\PCB_LIB\ORCAD_TEMPLATE\TEMPLATE.DSN")
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(Schematic "TEMPLATE")
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(Page "1:POWER"))
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(Doc
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(Type "COrSchematicDoc")
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(Frame
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(Placement "44 0 1 -1 -1 -1 -1 5 1413 28 796")
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(Scroll "-203 -8")
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(Zoom "100")
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(Occurrence "/"))
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(Path "D:\WORKSPACE\GITHUB\PCB_LIB\ORCAD_TEMPLATE\TEMPLATE.DSN")
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(Schematic "TEMPLATE")
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(Page "2:USB-CNT")))
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(MPSSessionName "Xeroly"))
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