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pcb_lib/other/dangling_lines.rpt
XerolySkinner d1a2e95934 更加标准化,修改了一下颜色
每一张封装加入三个参数:
LAST EDIT:最后修改时间
Approved:审核次数,最少是1(画完的时候简单审核一下)
*UNTESTED*:如果该封装没有被实际打出来测试过,就会有这个标识
2024-03-16 22:21:25 +08:00

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(---------------------------------------------------------------------)
( )
( Dangling Line, Via and Antenna Report )
( )
( Drawing : type-c.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 16 19:19:00 2024 )
( )
(---------------------------------------------------------------------)
Report methodology:
- Dangling lines have at least one end not connected.
- Dangling vias have one or no connection
- Plus are not a test, thieving or netshort property via.
- Antenna vias do not have connections on their start and end layers.
- Plus they are not a thieving vias.
- Optionally, VOLTAGE nets, testvias and through vias can be suppressed with
the environment variable report_antennavia.
- Section may be suppressed by variable report_noantennavia.
- Not part of the current partition.
- To suppress items in dangle report add the OK_DANGLE property to the via
or connect line.
<< Summary >>
Total dangling lines: 0
Total dangling vias: 0
Total antenna vias: 0