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XerolySkinner
2025-04-27 23:08:41 +08:00
parent 77b70e883e
commit 7394f89550
236 changed files with 152674 additions and 2443 deletions
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chip/allegro.jrl
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@@ -1,670 +1,45 @@
\t (00:03:41) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:03:41) Journal start - Wed Aug 7 01:04:42 2024
\t (00:03:41) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=24076 CPUs=12
\t (00:03:41) CmdLine= D:\SOFTWARE\Cadence\SPB_17.4\tools\bin\allegro.exe
\t (00:03:41)
\t (00:03:41) Starting new design...
\i (00:03:41) trapsize 9535
\i (00:03:41) trapsize 9796
\i (00:03:41) trapsize 9535
\t (00:03:42) Grids are drawn 650.2400, 650.2400 apart for enhanced viewing.
\i (00:03:42) trapsize 12488
\i (00:03:42) trapsize 12488
\i (00:03:42) trapsize 10638
\i (00:03:42) trapsize 10929
\i (00:03:42) trapsize 11236
\i (00:03:42) package symbol wizard
(00:04:59) Loading cmds.cxt
\i (00:04:59) setwindow form.sym_wizard
\i (00:04:59) FORM sym_wizard soic YES
\i (00:05:00) FORM sym_wizard wiz_next
\i (00:05:01) FORM sym_wizard load_template
\t (00:05:01) Opening existing design...
\t (00:05:02) Grids are drawn 200, 200 apart for enhanced viewing.
\i (00:05:02) setwindow pcb
\i (00:05:02) trapsize 151
\i (00:05:02) trapsize 155
\i (00:05:02) trapsize 151
\t (00:05:02) Grids are drawn 200, 200 apart for enhanced viewing.
\i (00:05:02) trapsize 175
\d (00:05:02) Design opened: D:/SOFTWARE/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols/template/sym_template.dra
\i (00:05:02) trapsize 169
\i (00:05:03) setwindow form.sym_wizard
\i (00:05:03) FORM sym_wizard wiz_next
\i (00:05:05) FORM sym_wizard pack_units Millimeter
\i (00:05:07) FORM sym_wizard pack_units_create Millimeter
\i (00:05:18) FORM sym_wizard wiz_next
\i (00:05:22) FORM sym_wizard sop_pin_count 5
\i (00:05:22) FORM sym_wizard sop_pin_count 56
\i (00:05:34) FORM sym_wizard sop_e 0.550
\i (00:05:37) FORM sym_wizard sop_e 0.500
\i (00:05:44) FORM sym_wizard sop_e1 7.500
\i (00:06:20) FORM sym_wizard sop_width 5.100
\i (00:06:23) FORM sym_wizard sop_len 14.000
\i (00:06:24) FORM sym_wizard wiz_next
\i (00:06:26) FORM sym_wizard default_pad_browse
\i (00:06:33) fillin "Htssop-56"
\i (00:06:35) FORM sym_wizard wiz_next
\i (00:07:40) FORM sym_wizard wiz_next
\i (00:07:41) FORM sym_wizard wiz_finish
\w (00:07:41) WARNING(SPMHUT-48): Scaled value has been rounded off.
\t (00:07:41) Grids are drawn 5.080, 5.080 apart for enhanced viewing.
\i (00:07:41) setwindow pcb
\i (00:07:41) trapsize 4288
\t (00:07:41) Performing DRC...
\t (00:07:41) No DRC errors detected.
\w (00:07:41) WARNING(SPMHUT-48): Scaled value has been rounded off.
\i (00:07:41) trapsize 4288
\i (00:07:42) trapsize 114
\i (00:07:42) trapsize 83
\i (00:07:42) trapsize 83
\i (00:07:42) trapsize 83
\t (00:07:42) Performing DRC...
\t (00:07:42) DRC done; 156 errors detected.
\t (00:07:42) Creating package symbol 'D:/workspace/GitHub/pcb_lib/chip/htssop-56.psm'.
\t (00:07:42) Starting Create symbol...
\i (00:07:44) zoom out 1
\i (00:07:44) setwindow pcb
\i (00:07:44) zoom out 8.717 -2.946
\i (00:07:44) trapsize 166
\i (00:07:45) zoom in 1
\i (00:07:45) setwindow pcb
\i (00:07:45) zoom in 2.566 -0.549
\i (00:07:45) trapsize 83
\i (00:07:45) zoom in 1
\i (00:07:45) setwindow pcb
\i (00:07:45) zoom in 2.566 -0.549
\i (00:07:45) trapsize 42
\i (00:07:45) zoom out 1
\i (00:07:45) setwindow pcb
\i (00:07:45) zoom out 3.498 0.042
\i (00:07:45) trapsize 83
\i (00:07:45) zoom out 1
\i (00:07:45) setwindow pcb
\i (00:07:45) zoom out 3.499 0.043
\i (00:07:45) trapsize 166
\i (00:07:46) zoom in 1
\i (00:07:46) setwindow pcb
\i (00:07:46) zoom in 0.003 -0.157
\i (00:07:46) trapsize 83
\i (00:07:47) zoom out 1
\i (00:07:47) setwindow pcb
\i (00:07:47) zoom out 2.434 0.542
\i (00:07:47) trapsize 166
\i (00:07:48) zoom in 1
\i (00:07:48) setwindow pcb
\i (00:07:48) zoom in -1.129 0.642
\i (00:07:48) trapsize 83
\i (00:07:59) spin
\t (00:07:59) Select element(s) to spin.
\i (00:08:00) drag_start grid 3.400 8.134
\i (00:08:03) drag_stop 4.382 -7.765
\t (00:08:03) Pick reference point for controlling the spin angle.
\i (00:08:04) prepopup 7.012 -4.436
\i (00:08:06) oops
\t (00:08:06) Select element(s) to spin.
\i (00:08:07) pick grid 8.178 -3.770
\t (00:08:07) last pick: 7.620 -2.540
\i (00:08:09) setwindow form.find
\i (00:08:09) FORM find all_off
\i (00:08:12) FORM find pins YES
\i (00:08:13) setwindow pcb
\i (00:08:13) drag_start grid 3.033 7.934
\i (00:08:14) roam y 32
\i (00:08:14) roam y 32
\i (00:08:14) roam y 16
\i (00:08:14) roam y 32
\i (00:08:14) roam y 16
\i (00:08:14) roam y 16
\i (00:08:14) roam y 16
\i (00:08:14) drag_stop 5.031 -8.982
\t (00:08:14) Pick reference point for controlling the spin angle.
\i (00:08:17) spin
\t (00:08:17) Select element(s) to spin.
\i (00:08:18) pick grid 5.514 -7.900
\t (00:08:18) last pick: 5.080 -7.620
\i (00:08:20) pick grid 4.815 -8.133
\t (00:08:20) last pick: 5.080 -7.620
\i (00:08:20) zoom out 1
\i (00:08:20) setwindow pcb
\i (00:08:20) zoom out 4.815 -8.133
\i (00:08:20) trapsize 166
\i (00:08:21) drag_start grid -5.824 8.349
\i (00:08:22) roam y 64
\i (00:08:22) roam y 16
\i (00:08:22) roam y 32
\i (00:08:23) drag_stop 9.392 -12.129
\t (00:08:23) Pick reference point for controlling the spin angle.
\i (00:08:24) pick grid 10.325 -4.038
\t (00:08:24) last pick: 10.160 -5.080
\i (00:08:26) iangle -90.000
\t (00:08:26) last angle: +270.000 Degrees
\t (00:08:26) Select element(s) to spin.
\i (00:08:27) zoom in 1
\i (00:08:27) setwindow pcb
\i (00:08:27) zoom in 0.170 4.353
\i (00:08:27) trapsize 83
\i (00:08:27) zoom in 1
\i (00:08:27) setwindow pcb
\i (00:08:27) zoom in 0.170 4.353
\i (00:08:27) trapsize 42
\i (00:08:27) zoom in 1
\i (00:08:27) setwindow pcb
\i (00:08:27) zoom in 0.170 4.353
\i (00:08:27) trapsize 21
\i (00:08:27) zoom out 1
\i (00:08:27) setwindow pcb
\i (00:08:27) zoom out 0.786 3.829
\i (00:08:28) trapsize 42
\i (00:08:28) zoom out 1
\i (00:08:28) setwindow pcb
\i (00:08:28) zoom out 0.786 3.829
\i (00:08:28) trapsize 83
\i (00:08:28) prepopup 4.931 5.044
\i (00:08:29) done
\i (00:08:31) zoom out 1
\i (00:08:31) setwindow pcb
\i (00:08:31) zoom out 6.263 4.612
\i (00:08:31) trapsize 166
\i (00:08:32) zoom in 1
\i (00:08:32) setwindow pcb
\i (00:08:32) zoom in -0.596 -2.214
\i (00:08:32) trapsize 83
\i (00:08:36) add pin
\i (00:08:38) add pin
\t (00:08:38) Exiting from Add Pin.
\i (00:08:42) setwindow form.mini
\i (00:08:42) FORM mini pad_browse
\t (00:08:48) No valid name selected.
\i (00:08:50) fillin "Htssop-56-1"
\w (00:08:50) WARNING(SPMHUT-48): Scaled value has been rounded off.
\t (00:08:50) Using 'HTSSOP-56-1.pad'.
\i (00:08:53) setwindow pcb
\i (00:08:53) pick 0 0
\t (00:08:53) last pick: 0.000 0.000
\t (00:08:53) Using 'HTSSOP-56-1.pad'.
\i (00:08:54) prepopup 10.558 2.813
\i (00:08:55) done
\t (00:08:55) Exiting from Add Pin.
\i (00:08:58) text edit
\i (00:09:00) pick grid -1.429 0.116
\t (00:09:00) last pick: -2.540 0.000
\i (00:09:02) setwindow pcb
\i (00:09:02) pick -1.429 0.116
\t (00:09:02) Pick text to edit.
\i (00:09:03) prepopup 1.302 -2.148
\i (00:09:04) done
\i (00:09:08) param in
\i (00:09:10) setwindow form.parm_in
\i (00:09:10) FORM parm_in browse
\i (00:09:13) fillin "D:/workspace/GitHub/pcb_lib/XerolySkinner.prm"
\i (00:09:14) FORM parm_in execute
\t (00:09:14) Starting Importing parameter file...
\w (00:09:15) WARNING(SPMHGE-269): param in had warnings, use Viewlog to review the log file.
\t (00:09:15) Opening existing design...
\t (00:09:15) Grids are drawn 40.640, 40.640 apart for enhanced viewing.
\i (00:09:15) setwindow pcb
\i (00:09:15) trapsize 83
\i (00:09:17) setwindow text
\i (00:09:17) close
\i (00:09:18) setwindow form.parm_in
\i (00:09:18) FORM parm_in cancel
\i (00:09:23) setwindow pcb
\i (00:09:23) text edit
\i (00:09:33) pick grid -1.745 0.782
\t (00:09:33) last pick: -1.905 0.635
\i (00:09:35) setwindow pcb
\i (00:09:35) prepopup 2.967 4.994
\i (00:09:36) done
\i (00:09:36) setwindow pcb
\i (00:09:36) pick -1.745 0.782
\i (00:09:37) setwindow pcb
\i (00:09:37) move
\t (00:09:37) Select element(s) to move.
\i (00:09:39) pick grid -2.128 0.633
\t (00:09:39) last pick: -1.905 0.635
\t (00:09:39) last pick: 0.000 0.000
\t (00:09:39) Pick new location for the element(s).
\i (00:09:40) prepopup -1.828 0.766
\i (00:09:41) oops
\t (00:09:41) last pick: -1.905 0.635
\i (00:09:43) setwindow form.find
\i (00:09:43) FORM find all_off
\i (00:09:46) FORM find text YES
\i (00:09:47) setwindow pcb
\i (00:09:47) pick grid -1.961 0.866
\t (00:09:47) last pick: -1.905 0.635
\t (00:09:47) last pick: -1.270 0.000
\t (00:09:47) Pick new location for the element(s).
\i (00:09:49) pick grid 0.519 -1.598
\t (00:09:49) last pick: 0.635 -1.905
\i (00:09:50) prepopup 7.445 1.015
\i (00:09:50) done
\i (00:09:53) define grid
\t (00:09:53) Spacing fields allow simple equations to aid calculations; prefix with =
\i (00:09:55) setwindow form.grid
\i (00:09:55) FORM grid non_etch non_etch_x_grids 0.1
\i (00:09:55) FORM grid non_etch non_etch_y_grids 0.1
\i (00:09:56) FORM grid all_etch all_etch_x_grids 0.1
\i (00:09:56) FORM grid all_etch all_etch_y_grids 0.1
\i (00:09:57) FORM grid done
\i (00:10:37) setwindow pcb
\i (00:10:37) change
\i (00:10:43) setwindow form.mini
\i (00:10:43) FORM mini change_class 'PACKAGE GEOMETRY'
\i (00:10:46) FORM mini change_subclass PIN_NUMBER
\i (00:10:51) FORM mini text_name pin
\i (00:10:55) setwindow form.find
\i (00:10:55) FORM find all_off
\i (00:10:56) FORM find text YES
\i (00:11:00) setwindow pcb
\i (00:11:00) drag_start grid 3.316 7.874
\i (00:11:01) roam y 16
\i (00:11:01) roam y 48
\i (00:11:02) drag_stop 4.598 -7.783
\t (00:11:02) No DRC errors detected.
\t (00:11:02) Changed 28 items out of 28 items found.
\i (00:11:04) drag_start grid -4.958 7.017
\i (00:11:05) drag_stop -3.243 -7.800
\t (00:11:05) No DRC errors detected.
\t (00:11:05) Changed 28 items out of 28 items found.
\i (00:11:06) pick grid 0.469 -1.024
\t (00:11:06) last pick: 0.500 -1.000
\t (00:11:06) No DRC errors detected.
\t (00:11:06) Changed 1 items out of 1 items found.
\i (00:11:09) prepopup 12.140 1.456
\i (00:11:10) next
\i (00:11:16) setwindow form.mini
\i (00:11:16) FORM mini change_class 'REF DES'
\i (00:11:19) FORM mini change_subclass ASSEMBLY_TOP
\i (00:11:23) FORM mini text_name asm
\i (00:11:25) setwindow pcb
\i (00:11:25) pick grid -0.396 0.857
\t (00:11:25) last pick: -0.400 0.900
\t (00:11:25) No DRC errors detected.
\t (00:11:25) Changed 1 items out of 1 items found.
\i (00:11:28) setwindow form.mini
\i (00:11:28) FORM mini change_subclass SILKSCREEN_TOP
\i (00:11:33) FORM mini text_name ski
\i (00:11:34) setwindow pcb
\i (00:11:34) pick grid 5.813 0.291
\t (00:11:34) last pick: 5.800 0.300
\t (00:11:34) No DRC errors detected.
\t (00:11:34) Changed 1 items out of 1 items found.
\i (00:11:36) prepopup 7.978 0.607
\i (00:11:37) done
\i (00:11:38) move
\t (00:11:38) Select element(s) to move.
\i (00:11:40) pick grid 5.680 0.274
\t (00:11:40) last pick: 5.700 0.300
\t (00:11:40) last pick: 5.250 0.000
\t (00:11:40) Pick new location for the element(s).
\i (00:11:46) pick grid -0.513 4.137
\t (00:11:46) last pick: -0.500 4.100
\i (00:11:46) zoom in 1
\i (00:11:46) setwindow pcb
\i (00:11:46) zoom in 7.095 1.873
\i (00:11:46) trapsize 42
\i (00:11:47) zoom out 1
\i (00:11:47) setwindow pcb
\i (00:11:47) zoom out 7.228 0.625
\i (00:11:47) trapsize 83
\i (00:11:47) zoom out 1
\i (00:11:47) setwindow pcb
\i (00:11:47) zoom out 7.229 0.624
\t (00:11:47) Grids are drawn 0.200, 0.200 apart for enhanced viewing.
\i (00:11:47) trapsize 166
\i (00:11:47) zoom in 1
\i (00:11:47) setwindow pcb
\i (00:11:47) zoom in -1.762 2.789
\i (00:11:47) trapsize 83
\i (00:11:47) zoom in 1
\i (00:11:47) setwindow pcb
\i (00:11:47) zoom in -1.762 2.790
\i (00:11:47) trapsize 42
\i (00:11:48) zoom out 1
\i (00:11:48) setwindow pcb
\i (00:11:48) zoom out 0.269 2.482
\i (00:11:48) trapsize 83
\i (00:11:48) zoom out 1
\i (00:11:48) setwindow pcb
\i (00:11:48) zoom out 0.269 2.482
\i (00:11:48) trapsize 166
\i (00:11:49) prepopup 12.156 4.679
\i (00:11:49) done
\i (00:11:50) zoom in 1
\i (00:11:50) setwindow pcb
\i (00:11:50) zoom in 0.170 0.683
\i (00:11:50) trapsize 83
\i (00:11:52) zoom in 1
\i (00:11:52) setwindow pcb
\i (00:11:52) zoom in -2.610 6.527
\i (00:11:52) trapsize 42
\i (00:11:53) zoom out 1
\i (00:11:53) setwindow pcb
\i (00:11:53) zoom out -1.428 5.720
\i (00:11:53) trapsize 83
\i (00:11:56) color192
\i (00:11:59) QtSignal CVDLayerContainer CVDVisibilityOff clicked
\i (00:12:01) QtSignal CVDTabs CVDLayerContainer keyPressEvent 16777248 33554432 false 1
\i (00:12:03) QtSignal CVDLayerContainer CVDFilterLayerEntry editingFinished silk
\i (00:12:03) QtSignal CVDLayerTable VertHeader clickedCheckBox "Silkscreen_Top" 1
\i (00:12:03) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 1 0
\i (00:12:04) QtSignal ColorVisibilityDialog CVDOkButton clicked
\i (00:12:07) delete
\i (00:12:11) setwindow form.find
\i (00:12:11) FORM find all_on
\i (00:12:13) setwindow pcb
\i (00:12:13) pick grid 2.517 4.188
\t (00:12:13) last pick: 2.500 4.200
\t (00:12:13) Line "Package Geometry/Silkscreen_Top"
\i (00:12:13) prepopup 5.614 5.286
\i (00:12:14) done
\i (00:12:15) color192
\i (00:12:17) QtSignal CVDLayerContainer CVDVisibilityOn clicked
\i (00:12:18) QtSignal ColorVisibilityDialog CVDOkButton clicked
\i (00:12:22) add line
\i (00:12:25) setwindow form.mini
\i (00:12:25) FORM mini class 'PACKAGE GEOMETRY'
\i (00:12:28) FORM mini subclass SILKSCREEN_TOP
\i (00:12:28) setwindow pcb
\i (00:12:28) updateport CVPane
\i (00:12:30) setwindow form.mini
\i (00:12:30) FORM mini line_width 0.150
\i (00:12:32) setwindow pcb
\i (00:12:32) zoom in 1
\i (00:12:32) setwindow pcb
\i (00:12:32) zoom in 2.434 6.851
\i (00:12:32) trapsize 42
\i (00:12:32) zoom in 1
\i (00:12:32) setwindow pcb
\i (00:12:32) zoom in 2.434 6.852
\i (00:12:32) trapsize 21
\i (00:12:33) zoom in 1
\i (00:12:33) setwindow pcb
\i (00:12:33) zoom in 2.551 7.060
\i (00:12:33) trapsize 10
\i (00:12:33) zoom in 1
\i (00:12:33) setwindow pcb
\i (00:12:33) zoom in 2.551 7.061
\i (00:12:33) trapsize 5
\i (00:12:33) zoom in 1
\i (00:12:33) setwindow pcb
\i (00:12:33) zoom in 2.551 7.061
\i (00:12:33) trapsize 3
\i (00:12:34) pick grid 2.550 7.002
\t (00:12:34) last pick: 2.600 7.000
\i (00:12:37) zoom out 1
\i (00:12:37) setwindow pcb
\i (00:12:37) zoom out 2.572 6.998
\i (00:12:37) trapsize 5
\i (00:12:37) zoom out 1
\i (00:12:37) setwindow pcb
\i (00:12:37) zoom out 2.572 6.997
\i (00:12:37) trapsize 10
\i (00:12:37) zoom out 1
\i (00:12:37) setwindow pcb
\i (00:12:37) zoom out 2.573 6.998
\i (00:12:37) trapsize 21
\i (00:12:37) zoom out 1
\i (00:12:37) setwindow pcb
\i (00:12:37) zoom out 2.574 6.999
\i (00:12:37) trapsize 42
\i (00:12:37) zoom out 1
\i (00:12:37) setwindow pcb
\i (00:12:37) zoom out 2.573 6.998
\i (00:12:37) trapsize 83
\i (00:12:38) zoom in 1
\i (00:12:38) setwindow pcb
\i (00:12:38) zoom in -2.390 7.032
\i (00:12:38) trapsize 42
\i (00:12:38) zoom in 1
\i (00:12:38) setwindow pcb
\i (00:12:38) zoom in -2.389 7.032
\i (00:12:38) trapsize 21
\i (00:12:38) zoom in 1
\i (00:12:38) setwindow pcb
\i (00:12:38) zoom in -2.389 7.032
\i (00:12:38) trapsize 10
\i (00:12:43) prepopup -2.335 7.137
\i (00:12:44) oops
\i (00:12:45) pick grid -2.597 7.105
\t (00:12:45) last pick: -2.600 7.100
\i (00:12:46) zoom out 1
\i (00:12:46) setwindow pcb
\i (00:12:46) zoom out -2.383 6.943
\i (00:12:46) trapsize 21
\i (00:12:46) zoom out 1
\i (00:12:46) setwindow pcb
\i (00:12:46) zoom out -2.383 6.943
\i (00:12:46) trapsize 42
\i (00:12:47) zoom in 1
\i (00:12:47) setwindow pcb
\i (00:12:47) zoom in 2.805 7.284
\i (00:12:47) trapsize 21
\i (00:12:48) zoom in 1
\i (00:12:48) setwindow pcb
\i (00:12:48) zoom in 2.726 7.380
\i (00:12:48) trapsize 10
\i (00:12:48) zoom in 1
\i (00:12:48) setwindow pcb
\i (00:12:48) zoom in 2.726 7.380
\i (00:12:48) trapsize 5
\i (00:12:50) pick grid 2.661 7.149
\t (00:12:50) last pick: 2.700 7.100
\i (00:12:51) zoom out 1
\i (00:12:51) setwindow pcb
\i (00:12:51) zoom out 2.694 7.164
\i (00:12:51) trapsize 10
\i (00:12:51) zoom out 1
\i (00:12:51) setwindow pcb
\i (00:12:51) zoom out 2.694 7.164
\i (00:12:51) trapsize 21
\i (00:12:51) zoom out 1
\i (00:12:51) setwindow pcb
\i (00:12:51) zoom out 2.694 7.164
\i (00:12:51) trapsize 42
\i (00:12:51) zoom out 1
\i (00:12:51) setwindow pcb
\i (00:12:51) zoom out 2.694 7.165
\i (00:12:51) trapsize 83
\i (00:12:51) zoom out 1
\i (00:12:51) setwindow pcb
\i (00:12:51) zoom out 2.694 7.165
\i (00:12:51) trapsize 167
\i (00:12:53) zoom in 1
\i (00:12:53) setwindow pcb
\i (00:12:53) zoom in 2.639 -6.824
\i (00:12:53) trapsize 83
\i (00:12:54) zoom in 1
\i (00:12:54) setwindow pcb
\i (00:12:54) zoom in 2.506 -7.540
\i (00:12:54) trapsize 42
\i (00:12:54) zoom in 1
\i (00:12:54) setwindow pcb
\i (00:12:54) zoom in 2.507 -7.539
\i (00:12:54) trapsize 21
\i (00:12:54) zoom in 1
\i (00:12:54) setwindow pcb
\i (00:12:54) zoom in 2.507 -7.539
\i (00:12:54) trapsize 10
\i (00:12:56) pick grid 2.659 -7.149
\t (00:12:56) last pick: 2.700 -7.100
\i (00:12:57) zoom out 1
\i (00:12:57) setwindow pcb
\i (00:12:57) zoom out 2.726 -7.114
\i (00:12:57) trapsize 21
\i (00:12:57) zoom out 1
\i (00:12:57) setwindow pcb
\i (00:12:57) zoom out 2.726 -7.114
\i (00:12:57) trapsize 42
\i (00:12:58) zoom out 1
\i (00:12:58) setwindow pcb
\i (00:12:58) zoom out 2.042 -6.980
\i (00:12:58) trapsize 83
\i (00:12:58) zoom out 1
\i (00:12:58) setwindow pcb
\i (00:12:58) zoom out 2.043 -6.981
\i (00:12:58) trapsize 167
\i (00:12:59) zoom in 1
\i (00:12:59) setwindow pcb
\i (00:12:59) zoom in -3.489 -6.481
\i (00:12:59) trapsize 83
\i (00:12:59) zoom in 1
\i (00:12:59) setwindow pcb
\i (00:12:59) zoom in -3.489 -6.481
\i (00:12:59) trapsize 42
\i (00:12:59) zoom in 1
\i (00:12:59) setwindow pcb
\i (00:12:59) zoom in -3.489 -6.481
\i (00:12:59) trapsize 21
\i (00:12:59) zoom in 1
\i (00:12:59) setwindow pcb
\i (00:12:59) zoom in -3.488 -6.481
\i (00:12:59) trapsize 10
\i (00:13:01) pick grid -2.743 -7.051
\t (00:13:01) last pick: -2.700 -7.100
\i (00:13:02) zoom out 1
\i (00:13:02) setwindow pcb
\i (00:13:02) zoom out -2.639 -6.845
\i (00:13:02) trapsize 21
\i (00:13:02) zoom out 1
\i (00:13:02) setwindow pcb
\i (00:13:02) zoom out -2.639 -6.844
\i (00:13:02) trapsize 42
\i (00:13:02) zoom out 1
\i (00:13:02) setwindow pcb
\i (00:13:02) zoom out -2.638 -6.845
\i (00:13:02) trapsize 83
\i (00:13:04) zoom in 1
\i (00:13:04) setwindow pcb
\i (00:13:04) zoom in -2.606 7.161
\i (00:13:04) trapsize 42
\i (00:13:04) zoom in 1
\i (00:13:04) setwindow pcb
\i (00:13:04) zoom in -2.606 7.161
\i (00:13:04) trapsize 21
\i (00:13:04) zoom in 1
\i (00:13:04) setwindow pcb
\i (00:13:04) zoom in -2.605 7.161
\i (00:13:04) trapsize 10
\i (00:13:04) zoom in 1
\i (00:13:04) setwindow pcb
\i (00:13:04) zoom in -2.605 7.161
\i (00:13:04) trapsize 5
\i (00:13:07) pick grid -2.651 6.989
\t (00:13:07) last pick: -2.700 7.000
\i (00:13:08) pick grid -2.686 7.059
\t (00:13:08) last pick: -2.700 7.100
\i (00:13:08) pick grid -2.538 7.130
\t (00:13:08) last pick: -2.500 7.100
\t (00:13:08) last pick: -2.600 7.100
\i (00:13:09) prepopup -2.587 7.085
\i (00:13:10) done
\i (00:13:10) zoom out 1
\i (00:13:10) setwindow pcb
\i (00:13:10) zoom out -2.621 6.887
\i (00:13:10) trapsize 10
\i (00:13:10) zoom out 1
\i (00:13:10) setwindow pcb
\i (00:13:10) zoom out -2.621 6.888
\i (00:13:10) trapsize 21
\i (00:13:10) zoom out 1
\i (00:13:10) setwindow pcb
\i (00:13:10) zoom out -2.621 6.887
\i (00:13:10) trapsize 42
\i (00:13:10) zoom out 1
\i (00:13:10) setwindow pcb
\i (00:13:10) zoom out -2.621 6.887
\i (00:13:10) trapsize 83
\i (00:13:11) zoom in 1
\i (00:13:11) setwindow pcb
\i (00:13:11) zoom in 2.492 6.288
\i (00:13:11) trapsize 42
\i (00:13:11) zoom in 1
\i (00:13:11) setwindow pcb
\i (00:13:11) zoom in 2.492 6.288
\i (00:13:11) trapsize 21
\i (00:13:11) zoom in 1
\i (00:13:11) setwindow pcb
\i (00:13:11) zoom in 2.492 6.288
\i (00:13:11) trapsize 10
\i (00:13:11) zoom in 1
\i (00:13:11) setwindow pcb
\i (00:13:11) zoom in 2.492 6.289
\i (00:13:11) trapsize 5
\i (00:13:12) zoom out 1
\i (00:13:12) setwindow pcb
\i (00:13:12) zoom out 2.492 6.289
\i (00:13:12) trapsize 10
\i (00:13:12) zoom out 1
\i (00:13:12) setwindow pcb
\i (00:13:12) zoom out 2.493 6.289
\i (00:13:12) trapsize 21
\i (00:13:12) zoom out 1
\i (00:13:12) setwindow pcb
\i (00:13:12) zoom out 2.493 6.288
\i (00:13:12) trapsize 42
\i (00:13:13) zoom in 1
\i (00:13:13) setwindow pcb
\i (00:13:13) zoom in -2.253 5.905
\i (00:13:13) trapsize 21
\i (00:13:13) zoom in 1
\i (00:13:13) setwindow pcb
\i (00:13:13) zoom in -2.253 5.906
\i (00:13:13) trapsize 10
\i (00:13:13) zoom in 1
\i (00:13:13) setwindow pcb
\i (00:13:13) zoom in -2.252 5.906
\i (00:13:13) trapsize 5
\i (00:13:13) zoom out 1
\i (00:13:13) setwindow pcb
\i (00:13:13) zoom out -2.252 5.906
\i (00:13:13) trapsize 10
\i (00:13:13) zoom out 1
\i (00:13:13) setwindow pcb
\i (00:13:13) zoom out -2.251 5.906
\i (00:13:13) trapsize 21
\i (00:13:13) zoom out 1
\i (00:13:13) setwindow pcb
\i (00:13:13) zoom out -2.252 5.906
\i (00:13:13) trapsize 42
\i (00:13:13) zoom out 1
\i (00:13:13) setwindow pcb
\i (00:13:13) zoom out -2.252 5.905
\i (00:13:13) trapsize 83
\i (00:13:13) zoom out 1
\i (00:13:13) setwindow pcb
\i (00:13:13) zoom out -2.252 5.906
\i (00:13:13) trapsize 167
\i (00:13:16) save
\i (00:13:16) fillin yes
\t (00:13:17) Symbol 'htssop-56.psm' created.
\i (00:13:18) zoom in 1
\i (00:13:18) setwindow pcb
\i (00:13:18) zoom in -4.721 1.542
\i (00:13:18) trapsize 83
\i (00:13:18) zoom in 1
\i (00:13:18) setwindow pcb
\i (00:13:18) zoom in -4.721 1.542
\i (00:13:18) trapsize 42
\i (00:13:19) zoom out 1
\i (00:13:19) setwindow pcb
\i (00:13:19) zoom out -3.147 1.293
\i (00:13:19) trapsize 83
\i (00:14:42) step pkg map
\i (00:14:42) fillin yes
\i (00:14:51) setwindow form.pkgmap3d
\i (00:14:51) FORM pkgmap3d stplist htssop-56.step
\i (00:14:53) FORM pkgmap3d overlay YES
\i (00:14:57) FORM pkgmap3d view_orientation Top
\i (00:15:04) FORM pkgmap3d view_orientation Bottom
\i (00:15:06) FORM pkgmap3d hide_board YES
\i (00:15:09) FORM pkgmap3d save_current
\i (00:15:11) FORM pkgmap3d done
\i (00:15:12) setwindow pcb
\i (00:15:12) save
\i (00:15:13) fillin yes
\t (00:15:13) Symbol 'htssop-56.psm' created.
\i (00:15:14) exit
\t (00:15:15) Journal end - Wed Aug 7 01:16:16 2024
\t (00:00:02) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Fri Apr 25 15:00:50 2025
\t (00:00:02) Host=XEROLYSKINNER User=Xeroly Pid=5220 CPUs=16
\t (00:00:02) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\chip\tqfp-48-ep.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "tqfp-48-ep"
\d (00:00:04) Design opened: D:/Workspace/GitHub/pcb_lib/chip/tqfp-48-ep.dra
\t (00:00:05) Grids are drawn 0.160, 0.160 apart for enhanced viewing.
\i (00:00:05) trapsize 102
\i (00:00:05) trapsize 104
\i (00:00:05) trapsize 102
\t (00:00:05) Grids are drawn 0.160, 0.160 apart for enhanced viewing.
\i (00:00:05) trapsize 108
\t (00:00:05) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
\i (00:00:05) trapsize 74
\i (00:00:12) add pin
\i (00:00:16) setwindow form.mini
\i (00:00:16) FORM mini pad_name tqfp-48-ep-gnd
\w (00:00:16) WARNING(SPMHUT-48): Scaled value has been rounded off.
\t (00:00:16) Using 'TQFP-48-EP-GND.pad'.
\e (00:00:20) Command not found: X 0 0
\i (00:00:22) setwindow pcb
\i (00:00:22) pick 0 0
\t (00:00:22) last pick: 0.000 0.000
\t (00:00:22) Using 'TQFP-48-EP-GND.pad'.
\i (00:00:23) prepopup 6.355 6.505
\i (00:00:27) oops
\t (00:00:27) Using 'TQFP-48-EP-GND.pad'.
\i (00:00:32) setwindow form.mini
\i (00:00:32) FORM mini text_name pin
\i (00:00:34) FORM mini next_pin_number 49
\i (00:00:36) setwindow pcb
\i (00:00:36) pick 0 0
\t (00:00:36) last pick: 0.000 0.000
\t (00:00:36) Using 'TQFP-48-EP-GND.pad'.
\i (00:00:37) prepopup 7.902 3.812
\i (00:00:38) done
\t (00:00:38) Exiting from Add Pin.
\i (00:00:39) save
\i (00:00:40) fillin yes
\t (00:00:40) Symbol 'tqfp-48-ep.psm' created.
\i (00:00:41) exit
\t (00:00:41) Journal end - Fri Apr 25 15:01:29 2025

1219
chip/allegro.jrl,1
View File

File diff suppressed because it is too large Load Diff

8
chip/batch_drc.log
View File

@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : sym_template.dra )
( Software Version : 17.4S035 )
( Date/Time : Wed Aug 7 01:08:43 2024 )
( Drawing : tqfp-48-ep.dra )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:37:19 2025 )
( )
(---------------------------------------------------------------------)
@@ -20,7 +20,7 @@
========= check standalone text 0:00:00
========= check standalone rectangles 0:00:00
..... Total number of DRC errors 156
..... Total number of DRC errors 0
..... DRC update completed, total CPU time 0:00:00
*************************************************************************

4
chip/batch_drc.log,1
View File

@@ -3,8 +3,8 @@
( DRC Update )
( )
( Drawing : sym_template.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 04:40:22 2024 )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:20:55 2025 )
( )
(---------------------------------------------------------------------)

6
chip/batch_drc.log,2
View File

@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : ssop-4.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 22:07:56 2024 )
( Drawing : sym_template.dra )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:20:56 2025 )
( )
(---------------------------------------------------------------------)

6
chip/batch_drc.log,3
View File

@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : sym_template.dra )
( Software Version : 17.4S035 )
( Date/Time : Wed Aug 7 01:08:42 2024 )
( Drawing : tqfp-48-ep.dra )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:35:37 2025 )
( )
(---------------------------------------------------------------------)

6
chip/downrev.log
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : htssop-56.dra )
( Software Version : 17.4S035 )
( Date/Time : Wed Aug 7 01:16:14 2024 )
( Drawing : tqfp-48-ep.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri Apr 25 15:01:28 2025 )
( )
(---------------------------------------------------------------------)

6
chip/downrev.log,1
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : htssop-56.dra )
( Software Version : 17.4S035 )
( Date/Time : Wed Aug 7 01:14:18 2024 )
( Drawing : tqfp-48-ep-gnd.pad )
( Software Version : 23.1P001 )
( Date/Time : Fri Apr 25 15:00:42 2025 )
( )
(---------------------------------------------------------------------)

6
chip/downrev.log,2
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : htssop-56.dra )
( Software Version : 17.4S035 )
( Date/Time : Wed Aug 7 01:16:14 2024 )
( Drawing : tqfp-48-ep.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri Apr 25 15:01:28 2025 )
( )
(---------------------------------------------------------------------)

6
chip/downrev.log,3
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : htssop-56.dra )
( Software Version : 17.4S035 )
( Date/Time : Wed Aug 7 01:16:14 2024 )
( Drawing : tqfp-48-ep.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri Apr 25 15:01:28 2025 )
( )
(---------------------------------------------------------------------)

BIN
chip/lqfp48.dra
View File

Binary file not shown.

23
chip/lqfp48.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : lqfp48.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:52:47 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/Workspace/GitHub/pcb_lib/chip
Name = lqfp48.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

BIN
chip/lqfp48.psm
View File

Binary file not shown.

2
chip/master.tag
View File

@@ -1 +1 @@
htssop-56.dra
tqfp-48-ep.dra

32
chip/padstack_editor.jrl
View File

@@ -1,8 +1,24 @@
\t (00:00:01) padstack_editor 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:01) Journal start - Wed Aug 7 01:05:16 2024
\t (00:00:01) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=10064 CPUs=12
\t (00:00:01) CmdLine= d:\software\cadence\spb_17.4\tools\bin\padstack_editor.exe D:\workspace\GitHub\pcb_lib\chip\htssop-56-1.pad
\t (00:00:01)
\d (00:00:02) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:03) QtSignal MainWindow Save triggered
\t (00:00:05) Journal end - Wed Aug 7 01:05:20 2024
\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:00) Journal start - Fri Apr 25 15:00:00 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=24896 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\chip\tqfp-48-ep-gnd.pad
\t (00:00:00)
\d (00:00:02) QtSignal GuidedTabsParent NewPads currentRowChanged 1
\d (00:00:02) QtSignal GuidedTabsParent NewPads itemSelectionChanged Square
\d (00:00:02) QtSignal GuidedTabsParent NewPads itemClicked Square
\d (00:00:03) QtFillin Yes
\d (00:00:05) QtSignal GuidedTabsParent GuidedStartTab keyPressEvent 16777251 134217728 false 1
\d (00:00:07) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:08) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
\d (00:00:08) QtSignal 1
\d (00:00:22) QtSignal GuidedDesignLayersTab PadWidth editingFinished "5.0000"
\d (00:00:26) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:27) QtSignal GuidedMaskLayersTab LayersTable cellClicked 0 "Regular Pad" 0 1
\d (00:00:29) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0000"
\d (00:00:36) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0600"
\d (00:00:37) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
\d (00:00:37) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 "Regular Pad" 2 1
\d (00:00:40) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0000"
\d (00:00:42) QtSignal MainWindow Save triggered
\d (00:00:43) QtSignal MainWindow Exit triggered
\t (00:00:43) Journal end - Fri Apr 25 15:00:44 2025

29
chip/padstack_editor.jrl,1
View File

@@ -1,8 +1,21 @@
\t (00:00:01) padstack_editor 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:01) Journal start - Wed Aug 7 01:05:05 2024
\t (00:00:01) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=26352 CPUs=12
\t (00:00:01) CmdLine= d:\software\cadence\spb_17.4\tools\bin\padstack_editor.exe D:\workspace\GitHub\pcb_lib\chip\htssop-56.pad
\t (00:00:01)
\d (00:00:06) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:08) QtSignal MainWindow Save triggered
\t (00:00:10) Journal end - Wed Aug 7 01:05:13 2024
\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:00) Journal start - Thu Apr 24 23:36:01 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=13068 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\chip\tqfp-48-ep.pad
\t (00:00:00)
\d (00:00:03) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:11) QtSignal GuidedDesignLayersTab PadHeight editingFinished "0.2600"
\d (00:00:11) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777220 0 false 1 "
"
\d (00:00:13) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:14) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:18) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:28) QtSignal GuidedMaskLayersTab PadHeight editingFinished "0.2800"
\d (00:00:28) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
\d (00:00:30) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
\d (00:00:32) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 "Regular Pad" 2 1
\d (00:00:33) QtSignal GuidedMaskLayersTab PadHeight editingFinished "0.2600"
\d (00:00:33) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
\d (00:00:36) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"

10
chip/param_read.log
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : htssop-56.dra )
( Software Version : 17.4S035 )
( Date/Time : Wed Aug 7 01:10:16 2024 )
( Drawing : tqfp-48-ep.dra )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:38:15 2025 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/workspace/GitHub/pcb_lib/chip/htssop-56.dra
Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/Workspace/GitHub/pcb_lib/chip/tqfp-48-ep.dra
Reading...parameter_header:
Reading...db_common_type:

8
chip/param_read.log,1
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : sop-16.dra )
( Drawing : ssop-4.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 04:40:41 2024 )
( Date/Time : Sat Aug 3 22:01:23 2024 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/¹¤×÷¿â/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/¹¤×÷¿â/GitHub/pcb_lib/chip/sop-16.dra
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/workspace/GitHub/pcb_lib/chip/ssop-4.dra
Reading...parameter_header:
Reading...db_common_type:

6
chip/param_read.log,2
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : ssop-4.dra )
( Drawing : htssop-56.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 22:01:23 2024 )
( Date/Time : Wed Aug 7 01:10:16 2024 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/workspace/GitHub/pcb_lib/chip/ssop-4.dra
Layout Name : D:/workspace/GitHub/pcb_lib/chip/htssop-56.dra
Reading...parameter_header:
Reading...db_common_type:

128
chip/param_read.log,3 Normal file
View File

@@ -0,0 +1,128 @@
(---------------------------------------------------------------------)
( )
( Parameter File READ )
( )
( Drawing : wsop-16.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:01:05 2025 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/Workspace/GitHub/pcb_lib/chip/wsop-16.dra
Reading...parameter_header:
Reading...db_common_type:
Reading...grid_parms_type:
WARNING: The value of element <etchcount> is not equal to the number of
user defined subclass under ETCH class.
Reading...UnusedPadsSuppressionSettings:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
WARNING: Unmatched Data - Field Name: subclass , Value: "SIGNEDTOP"
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
WARNING: Unmatched Data - Field Name: subclass , Value: "SIGNEDBOTTOM"
Reading...art_class_type:
Reading...art_class_type:
Reading...color_table_table:
Reading...ColorParmType:
Reading...profileCustomColors:
Reading...text_size_table:
Reading...drf_parm_type:
Reading...av_parm_type:
Reading...dynfill_parm_type:
Reading...probe_parm_type:
Reading...ifp_parm_type:
Reading...ministat_parm_type:
WARNING: Unmatched Data - Field Name: acon_active_sc , Value: "SIGNEDTOP"
Reading...ats_parm_type:
Reading...placement_parameter_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
..... Total number of errors: 0.
..... Total number of warnings: 4.

25872
chip/stepFacetFiles4Map/ssop-16.xml Normal file
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File diff suppressed because it is too large Load Diff

5
chip/stepFacetFiles4Map/stepFileInfo.txt
View File

@@ -5,6 +5,9 @@ SOT-223.step ! 227596 ! 1710578258
htssop-56.step ! 2056211 ! 1722964516
tssop8.STEP ! 174674 ! 1711377980
lqfp48.step ! 1919983 ! 1711219780
wsop_16.step ! 827104 ! 1745399292
ssop-16.step ! 873879 ! 1745399033
tqfp-48.STEP ! 166679 ! 1745422272
D8-L.step ! 282667 ! 1568096060
SOP-16.STEP ! 3778717 ! 1722501952
DIP_2x5.step ! 720870 ! 1710578258
@@ -16,5 +19,5 @@ tssop8.step ! 306368 ! 1711457082
LED_0603_G.STEP ! 178570 ! 1710578258
KEY_SOT_P2.step ! 151224 ! 1710578258
sop-14.step ! 521672 ! 1710578258
ssop-4.STEP ! 294871 ! 1722693500
ufqfpn28_2.step ! 4307335 ! 1711439232
ssop-4.STEP ! 294871 ! 1722693500

6
chip/stepFacetFiles4Map/stepFileInfo.txt,1
View File

@@ -2,8 +2,12 @@
D8-M.step ! 282667 ! 1568096060
SOT-223.step ! 227596 ! 1710578258
htssop-56.step ! 2056211 ! 1722964516
tssop8.STEP ! 174674 ! 1711377980
lqfp48.step ! 1919983 ! 1711219780
wsop_16.step ! 827104 ! 1745399292
ssop-16.step ! 873879 ! 1745399033
tqfp-48.STEP ! 166679 ! 1745422272
D8-L.step ! 282667 ! 1568096060
SOP-16.STEP ! 3778717 ! 1722501952
DIP_2x5.step ! 720870 ! 1710578258
@@ -15,5 +19,5 @@ tssop8.step ! 306368 ! 1711457082
LED_0603_G.STEP ! 178570 ! 1710578258
KEY_SOT_P2.step ! 151224 ! 1710578258
sop-14.step ! 521672 ! 1710578258
ufqfpn28_2.step ! 4307335 ! 1711439232
ssop-4.STEP ! 294871 ! 1722693500
ufqfpn28_2.step ! 4307335 ! 1711439232

4041
chip/stepFacetFiles4Map/tqfp-48.xml Normal file
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File diff suppressed because it is too large Load Diff

26224
chip/stepFacetFiles4Map/wsop_16.xml Normal file
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File diff suppressed because it is too large Load Diff

BIN
chip/tqfp-48-ep-gnd.pad Normal file
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Binary file not shown.

BIN
chip/tqfp-48-ep.dra Normal file
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Binary file not shown.

23
chip/tqfp-48-ep.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : tqfp-48-ep.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri Apr 25 15:01:28 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/Workspace/GitHub/pcb_lib/chip
Name = tqfp-48-ep.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

23
chip/tqfp-48-ep.log,1 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : tqfp-48-ep.dra )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:39:25 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/Workspace/GitHub/pcb_lib/chip
Name = tqfp-48-ep.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

23
chip/tqfp-48-ep.log,2 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : tqfp-48-ep.dra )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:40:41 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/Workspace/GitHub/pcb_lib/chip
Name = tqfp-48-ep.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

23
chip/tqfp-48-ep.log,3 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : tqfp-48-ep.dra )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:43:01 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/Workspace/GitHub/pcb_lib/chip
Name = tqfp-48-ep.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

BIN
chip/tqfp-48-ep.pad Normal file
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Binary file not shown.

BIN
chip/tqfp-48-ep.psm Normal file
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Binary file not shown.

BIN
chip/wsop-16.dra Normal file
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Binary file not shown.

23
chip/wsop-16.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : wsop-16.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:37:56 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/Workspace/GitHub/pcb_lib/chip
Name = wsop-16.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

23
chip/wsop-16.log,1 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : wsop-16.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:18:34 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/Workspace/GitHub/pcb_lib/chip
Name = wsop-16.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

23
chip/wsop-16.log,2 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : wsop-16.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:18:43 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/Workspace/GitHub/pcb_lib/chip
Name = wsop-16.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

23
chip/wsop-16.log,3 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : wsop-16.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:37:39 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/Workspace/GitHub/pcb_lib/chip
Name = wsop-16.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

BIN
chip/wsop-16.pad Normal file
View File

Binary file not shown.

BIN
chip/wsop-16.psm Normal file
View File

Binary file not shown.