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XerolySkinner
2024-08-02 02:32:24 +08:00
parent 70f78434d9
commit 79562d2813
152 changed files with 827512 additions and 4998 deletions
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\i (00:08:32) add circle
\t (00:08:32) Pick center point of the circle.
\t (00:08:32) Pick center point of the circle.
\i (00:08:38) setwindow form.mini
\i (00:08:38) FORM mini subclass PLACE_BOUND_TOP
\i (00:08:38) setwindow pcb
\i (00:08:38) updateport CVPane
\i (00:08:43) shape add circle
\i (00:08:47) pick 0 0
\t (00:08:47) last pick: 0.0000 0.0000
\i (00:08:48) pick 0 5
\t (00:08:48) last pick: 0.0000 5.0000
\i (00:08:49) prepopup 4.7093 4.8723
\i (00:08:50) done
\i (00:08:52) add pin
\i (00:09:04) setwindow form.mini
\i (00:09:04) FORM mini pad_name thr-1r02_1r8
\t (00:09:04) Using 'THR-1R02_1R8.pad'.
\i (00:09:29) setwindow pcb
\i (00:09:29) pick 0 2.5
\t (00:09:29) last pick: 0.0000 2.5000
\t (00:09:29) Using 'THR-1R02_1R8.pad'.
\i (00:09:30) prepopup 3.6232 -2.8394
\i (00:09:31) oops
\t (00:09:31) Using 'THR-1R02_1R8.pad'.
\i (00:09:36) setwindow form.mini
\i (00:09:36) FORM mini next_pin_number 1
\i (00:09:37) FORM mini text_block 2
\i (00:09:38) FORM mini text_block 1
\i (00:09:40) FORM mini text_name pin
\i (00:09:46) setwindow pcb
\i (00:09:46) pick -2.5 0
\t (00:09:46) last pick: -2.5000 0.0000
\t (00:09:46) Using 'THR-1R02_1R8.pad'.
\i (00:09:49) pick 2.5 0
\t (00:09:49) last pick: 2.5000 0.0000
\t (00:09:49) Using 'THR-1R02_1R8.pad'.
\i (00:09:50) prepopup 4.1197 3.6154
\i (00:09:51) done
\t (00:09:51) Exiting from Add Pin.
\i (00:09:53) save
\e (00:09:53) ERROR(SPMHGE-7): Error(s) occurred, check logfile.
\i (00:09:56) setwindow text
\i (00:09:56) close
\i (00:09:56) setwindow pcb
\i (00:09:56) label refdes
\t (00:09:56) Pick text location.
\i (00:10:03) setwindow form.mini
\i (00:10:03) FORM mini text_name asm
\i (00:10:06) setwindow pcb
\i (00:10:06) pick 0 0
\t (00:10:06) last pick: 0.0000 0.0000
\t (00:10:06) Enter text string.
\i (00:10:07) setwindow pcb
\i (00:10:07) pick 0.0000 0.0000
\i (00:10:13) setwindow form.mini
\i (00:10:13) FORM mini subclass SILKSCREEN_TOP
\i (00:10:13) setwindow pcb
\i (00:10:13) updateport CVPane
\i (00:10:16) setwindow form.mini
\i (00:10:16) FORM mini text_name ski
\i (00:10:17) setwindow pcb
\i (00:10:17) pick 0 0
\t (00:10:17) last pick: 0.0000 0.0000
\t (00:10:17) Enter text string.
\i (00:10:18) setwindow pcb
\i (00:10:18) pick 0.0000 0.0000
\i (00:10:19) setwindow pcb
\i (00:10:19) prepopup 8.4488 3.3672
\i (00:10:20) done
\i (00:10:21) save
\i (00:10:21) fillin yes
\t (00:10:22) Symbol 'ecap-10-16.psm' created.
\i (25:40:10) save
\i (25:40:11) fillin yes
\t (25:40:11) Symbol 'ecap-10-16.psm' created.
\i (25:40:12) exit
\t (25:40:12) Journal end - Sat Jul 20 07:13:10 2024

14
cap_smd/downrev.log Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : ecap-10-16.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Jul 20 07:13:09 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
cap_smd/downrev.log,1 Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : ecap-10-16.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Jul 19 05:43:19 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
cap_smd/downrev.log,2 Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : ecap-10-16.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Jul 20 07:13:08 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
cap_smd/downrev.log,3 Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : ecap-10-16.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Jul 20 07:13:08 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

BIN
cap_smd/ecap-10-16.dra Normal file
View File

Binary file not shown.

23
cap_smd/ecap-10-16.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : ecap-10-16.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Jul 20 07:13:09 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/š¤×÷żâ/GitHub/pcb_lib/cap_smd
Name = ecap-10-16.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

24
cap_smd/ecap-10-16.log,1 Normal file
View File

@@ -0,0 +1,24 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : ecap-10-16.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Jul 19 05:42:51 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/¹¤×÷¿â/GitHub/pcb_lib/cap_smd
Name = ecap-10-16.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
ERROR(SPMHCS-1): Symbol is missing a refdes.
ERROR(SPMHA1-291): Create symbol has been aborted.

23
cap_smd/ecap-10-16.log,2 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : ecap-10-16.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Jul 19 05:43:19 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/š¤×÷żâ/GitHub/pcb_lib/cap_smd
Name = ecap-10-16.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
cap_smd/ecap-10-16.psm Normal file
View File

Binary file not shown.

BIN
cap_smd/ecap-12_5-20.dra Normal file
View File

Binary file not shown.

BIN
cap_smd/ecap-12_5-20.psm Normal file
View File

Binary file not shown.

BIN
cap_smd/ecap-6_3-11_2.dra Normal file
View File

Binary file not shown.

BIN
cap_smd/ecap-6_3-11_2.psm Normal file
View File

Binary file not shown.

1
cap_smd/master.tag Normal file
View File

@@ -0,0 +1 @@
ecap-10-16.dra

8
thr/param_read.log → cap_smd/param_read.log
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : thr_pin.dra )
( Drawing : ecap-10-16.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Apr 15 22:48:56 2024 )
( Date/Time : Fri Jul 19 05:40:35 2024 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : thr_pin.dra
Paramfile Name : D:/¹¤×÷¿â/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : ecap-10-16.dra
Reading...parameter_header:
Reading...db_common_type:

4913
cap_smd/stepFacetFiles4Map/C0603.xml Normal file
View File

File diff suppressed because it is too large Load Diff

8852
cap_smd/stepFacetFiles4Map/ecap-12_5-20.xml Normal file
View File

File diff suppressed because it is too large Load Diff

7300
cap_smd/stepFacetFiles4Map/ecap-6_3-11_2.xml Normal file
View File

File diff suppressed because it is too large Load Diff

3
cap_smd/stepFacetFiles4Map/stepFileInfo.txt
View File

@@ -1,5 +1,7 @@
#STEP_FILE ! FILE_SIZE ! MOD_TIME
ecap-12_5-20.STEP ! 134812 ! 1720534070
C0603.stp ! 74996 ! 1710578258
cap-smd-4x5_4.STEP ! 253153 ! 1710578258
cap-smd-10x10_2.STEP ! 253069 ! 1710578258
D8-L.step ! 282667 ! 1568096060
@@ -7,3 +9,4 @@ cap-smd-5x5_4.STEP ! 236170 ! 1710578258
CONN-2P-P5.step ! 1193777 ! 1710578258
cap-smd-6_3x5_4.STEP ! 236141 ! 1710578258
cap-smd-8x6_5.STEP ! 236073 ! 1710578258
ecap-6_3-11_2.STEP ! 103312 ! 1720704337

3
cap_smd/stepFacetFiles4Map/stepFileInfo.txt,1
View File

@@ -1,8 +1,11 @@
#STEP_FILE ! FILE_SIZE ! MOD_TIME
ecap-12_5-20.STEP ! 134812 ! 1720534070
C0603.stp ! 74996 ! 1710578258
cap-smd-4x5_4.STEP ! 253153 ! 1710578258
cap-smd-10x10_2.STEP ! 253069 ! 1710578258
D8-L.step ! 282667 ! 1568096060
cap-smd-5x5_4.STEP ! 236170 ! 1710578258
CONN-2P-P5.step ! 1193777 ! 1710578258
cap-smd-6_3x5_4.STEP ! 236141 ! 1710578258
cap-smd-8x6_5.STEP ! 236073 ! 1710578258

BIN
cap_smd/unnamed.brd
View File

Binary file not shown.

80
chip/allegro.jrl Normal file
View File

@@ -0,0 +1,80 @@
\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Mon Jul 29 04:50:28 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=13504 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\chip\lqfp64.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged lqfp64
\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/chip/lqfp64.dra
\t (00:00:02) Grids are drawn 0.200, 0.200 apart for enhanced viewing.
\i (00:00:02) trapsize 135
\i (00:00:02) trapsize 139
\i (00:00:02) trapsize 135
\i (00:00:03) trapsize 118
\i (00:00:03) trapsize 122
\i (00:00:03) trapsize 125
\t (00:00:03) Grids are drawn 0.200, 0.200 apart for enhanced viewing.
\i (00:00:03) trapsize 128
\i (00:00:06) delete
\i (00:00:08) pick grid 0.029 2.342
\t (00:00:08) last pick: 0.000 2.300
\t (00:00:08) Shape "Package Geometry/Silkscreen_Top"
\i (00:00:08) prepopup 7.913 10.740
\i (00:00:09) done
\i (00:00:14) shape add rect
\i (00:00:16) pick 0 0
\t (00:00:16) last pick: 0.000 0.000
\i (00:00:18) zoom in 1
\i (00:00:18) setwindow pcb
\i (00:00:18) zoom in -5.004 5.424
\i (00:00:18) trapsize 64
\i (00:00:18) zoom in 1
\i (00:00:18) setwindow pcb
\i (00:00:18) zoom in -5.004 5.424
\i (00:00:18) trapsize 32
\i (00:00:18) zoom in 1
\i (00:00:18) setwindow pcb
\i (00:00:18) zoom in -5.004 5.424
\i (00:00:18) trapsize 16
\i (00:00:18) zoom in 1
\i (00:00:18) setwindow pcb
\i (00:00:18) zoom in -5.004 5.425
\i (00:00:18) trapsize 8
\i (00:00:18) zoom in 1
\i (00:00:18) setwindow pcb
\i (00:00:18) zoom in -5.004 5.425
\i (00:00:18) trapsize 4
\i (00:00:19) pick grid -4.991 5.049
\t (00:00:19) last pick: -5.000 5.000
\i (00:00:19) zoom out 1
\i (00:00:19) setwindow pcb
\i (00:00:19) zoom out -4.944 5.410
\i (00:00:19) trapsize 8
\i (00:00:19) zoom out 1
\i (00:00:19) setwindow pcb
\i (00:00:19) zoom out -4.945 5.409
\i (00:00:19) trapsize 16
\i (00:00:19) zoom out 1
\i (00:00:19) setwindow pcb
\i (00:00:19) zoom out -4.945 5.409
\i (00:00:19) trapsize 32
\i (00:00:19) zoom out 1
\i (00:00:19) setwindow pcb
\i (00:00:19) zoom out -4.944 5.410
\i (00:00:19) trapsize 64
\i (00:00:20) prepopup -4.945 5.411
\i (00:00:21) done
\i (00:00:22) delete
\i (00:00:23) pick grid -4.689 4.679
\t (00:00:23) last pick: -4.700 4.700
\t (00:00:23) Line "Package Geometry/Silkscreen_Top"
\i (00:00:24) pick grid -7.886 5.244
\t (00:00:24) last pick: -7.900 5.200
\i (00:00:24) prepopup -7.886 5.244
\i (00:00:25) done
\i (00:00:26) save
\i (00:00:26) fillin yes
\t (00:00:26) Symbol 'lqfp64.psm' created.
\i (00:00:27) exit
\t (00:00:28) Journal end - Mon Jul 29 04:50:54 2024

111
chip/allegro.jrl,1 Normal file
View File

@@ -0,0 +1,111 @@
\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Mon Jul 29 04:48:36 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=18232 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\chip\sop-8.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sop-8"
\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/chip/sop-8.dra
\i (00:00:02) trapsize 106
\i (00:00:02) trapsize 109
\i (00:00:03) trapsize 106
\i (00:00:03) trapsize 93
\i (00:00:03) trapsize 95
\i (00:00:03) trapsize 98
\i (00:00:03) trapsize 98
\i (00:00:10) shape add rect
\i (00:00:14) setwindow form.mini
\i (00:00:14) FORM mini class 'PACKAGE GEOMETRY'
\i (00:00:16) FORM mini subclass SILKSCREEN_TOP
\i (00:00:16) setwindow pcb
\i (00:00:16) updateport CVPane
\i (00:00:21) pick 0 0
\t (00:00:21) last pick: 0.000 0.000
\i (00:00:23) zoom in 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom in -0.968 2.055
\i (00:00:23) trapsize 49
\i (00:00:23) zoom in 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom in -0.968 2.055
\i (00:00:23) trapsize 25
\i (00:00:23) zoom in 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom in -0.968 2.056
\i (00:00:23) trapsize 12
\i (00:00:23) zoom in 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom in -0.968 2.056
\i (00:00:23) trapsize 6
\i (00:00:23) zoom out 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom out -1.143 1.793
\i (00:00:23) trapsize 12
\i (00:00:23) zoom out 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom out -1.142 1.793
\i (00:00:23) trapsize 25
\i (00:00:23) zoom out 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom out -1.142 1.793
\i (00:00:23) trapsize 49
\i (00:00:24) zoom in 1
\i (00:00:24) setwindow pcb
\i (00:00:24) zoom in -1.398 2.469
\i (00:00:24) trapsize 25
\i (00:00:24) zoom in 1
\i (00:00:24) setwindow pcb
\i (00:00:24) zoom in -1.398 2.469
\i (00:00:24) trapsize 12
\i (00:00:24) zoom in 1
\i (00:00:24) setwindow pcb
\i (00:00:24) zoom in -1.398 2.469
\i (00:00:24) trapsize 6
\i (00:00:26) pick grid -1.469 2.450
\t (00:00:26) last pick: -1.500 2.500
\i (00:00:27) prepopup -1.205 2.640
\i (00:00:28) done
\i (00:00:31) delete
\i (00:00:33) pick grid -1.096 2.170
\t (00:00:33) last pick: -1.100 2.200
\t (00:00:33) Line "Package Geometry/Silkscreen_Top"
\i (00:00:33) prepopup -1.049 2.662
\i (00:00:34) done
\i (00:00:34) zoom out 1
\i (00:00:34) setwindow pcb
\i (00:00:34) zoom out -1.049 2.662
\i (00:00:34) trapsize 12
\i (00:00:34) zoom out 1
\i (00:00:34) setwindow pcb
\i (00:00:34) zoom out -1.050 2.662
\i (00:00:34) trapsize 25
\i (00:00:34) zoom out 1
\i (00:00:34) setwindow pcb
\i (00:00:34) zoom out -1.049 2.662
\i (00:00:35) trapsize 49
\i (00:00:35) zoom out 1
\i (00:00:35) setwindow pcb
\i (00:00:35) zoom out -1.049 2.662
\i (00:00:35) trapsize 98
\i (00:00:35) zoom out 1
\i (00:00:35) setwindow pcb
\i (00:00:35) zoom out 1.288 2.270
\i (00:00:35) trapsize 98
\i (00:00:35) save
\i (00:00:36) fillin yes
\t (00:00:36) Symbol 'sop-8.psm' created.
\i (00:00:37) delete
\i (00:00:39) pick grid 0.366 3.447
\t (00:00:39) last pick: 0.400 3.400
\t (00:00:39) Text "Last Edit:2024-3-16"
\i (00:00:40) pick grid 0.582 -3.398
\t (00:00:40) last pick: 0.600 -3.400
\t (00:00:40) Text "Approved[2]"
\i (00:00:40) prepopup 0.582 -3.398
\i (00:00:41) done
\i (00:00:42) save
\i (00:00:42) fillin yes
\t (00:00:42) Symbol 'sop-8.psm' created.
\i (00:00:43) exit
\t (00:00:44) Journal end - Mon Jul 29 04:49:18 2024

14
chip/downrev.log Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : lqfp64.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:50:52 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
chip/downrev.log,1 Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : sop-8.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:49:17 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
chip/downrev.log,2 Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : lqfp64.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:50:52 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
chip/downrev.log,3 Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : lqfp64.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:50:52 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

BIN
chip/lqfp64.dra
View File

Binary file not shown.

23
chip/lqfp64.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : lqfp64.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:50:52 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = lqfp64.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
chip/lqfp64.log,1 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : lqfp64.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:47:43 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = lqfp64.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
chip/lqfp64.psm
View File

Binary file not shown.

1
chip/master.tag Normal file
View File

@@ -0,0 +1 @@
lqfp64.dra

BIN
chip/sop-8.dra
View File

Binary file not shown.

23
chip/sop-8.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : sop-8.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:49:17 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = sop-8.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
chip/sop-8.log,1 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : sop-8.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:49:11 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = sop-8.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
chip/sop-8.psm
View File

Binary file not shown.

14
hold/downrev.log Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : thr-1r6-2r3.pad )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 01:49:11 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

39
hold/padstack_editor.jrl Normal file
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@@ -0,0 +1,39 @@
\t (00:00:01) padstack_editor 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:01) Journal start - Fri Aug 2 01:48:19 2024
\t (00:00:01) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=8148 CPUs=12
\t (00:00:01) CmdLine= d:\software\cadence\spb_17.4\tools\bin\padstack_editor.exe D:\workspace\GitHub\pcb_lib\hold\thr-1r6-2r3.pad
\t (00:00:01)
\d (00:00:03) QtSignal GuidedTabsParent GuidedTabs currentChanged Drill
\d (00:00:06) QtSignal GuidedDrillTab holeXSize editingFinished "1.6000"
\d (00:00:06) QtSignal GuidedTabsParent GuidedDrillTab keyPressEvent 16777220 0 false 1 "
"
\d (00:00:08) QtSignal GuidedTabsParent GuidedTabs currentChanged "Secondary Drill"
\d (00:00:08) QtSignal GuidedTabsParent GuidedTabs currentChanged "Drill Symbol"
\d (00:00:12) QtSignal GuidedDrillSymbol FigureDiameter editingFinished "1.6000"
\d (00:00:13) QtSignal GuidedTabsParent GuidedTabs currentChanged "Drill Offset"
\d (00:00:13) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:14) QtSignal GuidedDesignLayersTab LayersTable itemSelectionChanged 0 "Regular Pad"
\d (00:00:14) QtSignal GuidedDesignLayersTab LayersTable cellClicked 0 "Regular Pad" 0 2
\d (00:00:15) QtSignal GuidedDesignLayersTab LayersTable itemSelectionChanged 1 "Regular Pad"
\d (00:00:15) QtSignal GuidedDesignLayersTab LayersTable cellClicked 1 "Regular Pad" 1 2
\d (00:00:16) QtSignal GuidedDesignLayersTab LayersTable itemSelectionChanged 0 "Regular Pad"
\d (00:00:16) QtSignal GuidedDesignLayersTab LayersTable cellClicked 0 "Regular Pad" 0 2
\d (00:00:19) QtSignal GuidedDesignLayersTab PadDiameter editingFinished "2.3000"
\d (00:00:20) QtSignal GuidedDesignLayersTab LayersTable itemSelectionChanged 1 "Regular Pad"
\d (00:00:20) QtSignal GuidedDesignLayersTab LayersTable cellClicked 1 "Regular Pad" 1 2
\d (00:00:22) QtSignal GuidedDesignLayersTab PadDiameter editingFinished "2.3000"
\d (00:00:23) QtSignal GuidedDesignLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
\d (00:00:23) QtSignal GuidedDesignLayersTab LayersTable cellClicked 2 "Regular Pad" 2 2
\d (00:00:25) QtSignal GuidedDesignLayersTab PadDiameter editingFinished "2.3000"
\d (00:00:28) QtSignal GuidedDesignLayersTab LayersTable itemSelectionChanged 1 "Thermal Pad"
\d (00:00:28) QtSignal GuidedDesignLayersTab LayersTable cellClicked 1 "Thermal Pad" 1 3
\d (00:00:30) QtSignal GuidedDesignLayersTab LayersTable itemSelectionChanged 1 "Anti Pad"
\d (00:00:30) QtSignal GuidedDesignLayersTab LayersTable cellClicked 1 "Anti Pad" 1 4
\d (00:00:36) QtSignal GuidedDesignLayersTab PadDiameter editingFinished "2.4000"
\d (00:00:39) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:46) QtSignal GuidedMaskLayersTab PadDiameter editingFinished "2.3700"
\d (00:00:47) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 1 Pad
\d (00:00:47) QtSignal GuidedMaskLayersTab LayersTable cellClicked 1 Pad 1 1
\d (00:00:49) QtSignal GuidedMaskLayersTab PadDiameter editingFinished "2.3700"
\d (00:00:50) QtSignal GuidedTabsParent GuidedTabs currentChanged Options
\d (00:00:53) QtSignal MainWindow Save triggered

BIN
hold/thr-1r6-2r3.pad Normal file
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Binary file not shown.

BIN
smc/1812.pad Normal file
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88
smc/allegro.jrl
View File

@@ -1,78 +1,18 @@
\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Fri Apr 12 18:47:52 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=10460 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\smc\c1206.dra
\t (00:00:02) Journal start - Sun Jul 28 23:00:44 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=26612 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\smc\ll34.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged c1206
\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/smc/c1206.dra
\i (00:00:02) trapsize 181
\i (00:00:02) trapsize 186
\i (00:00:03) trapsize 181
\i (00:00:03) trapsize 159
\i (00:00:03) trapsize 163
\i (00:00:03) trapsize 168
\i (00:00:03) trapsize 172
\i (00:00:15) step pkg map
\i (00:00:16) fillin yes
\i (00:00:29) setwindow form.pkgmap3d
\i (00:00:29) FORM pkgmap3d stplist c1206.stp
\i (00:00:38) FORM pkgmap3d done
\i (00:00:41) setwindow pcb
\i (00:00:41) step pkg map
\i (00:00:43) fillin yes
\i (00:01:09) setwindow form.pkgmap3d
\i (00:01:09) FORM pkgmap3d stplist C0603.stp
\i (00:01:13) FORM pkgmap3d stplist c1206.stp
\i (00:01:23) FORM pkgmap3d view_orientation Right
\i (00:01:27) FORM pkgmap3d offset_z -10
\i (00:01:29) FORM pkgmap3d offset_z -100
\i (00:01:32) FORM pkgmap3d offset_z -50
\i (00:01:34) FORM pkgmap3d offset_z -20
\i (00:01:38) FORM pkgmap3d offset_z -30
\i (00:01:40) FORM pkgmap3d offset_z -40
\i (00:01:44) FORM pkgmap3d view_orientation 'Front Right'
\i (00:01:48) FORM pkgmap3d rotation_x 90
\i (00:02:08) FORM pkgmap3d view_orientation 'Front Left'
\i (00:02:11) FORM pkgmap3d view_orientation Top
\i (00:02:22) FORM pkgmap3d view_orientation Bottom
\i (00:02:24) FORM pkgmap3d view_orientation 'Front Left'
\i (00:02:25) FORM pkgmap3d overlay NO
\i (00:02:26) FORM pkgmap3d hide_board YES
\i (00:02:27) FORM pkgmap3d overlay YES
\i (00:02:29) FORM pkgmap3d view_orientation Top
\i (00:02:31) FORM pkgmap3d view_orientation Bottom
\i (00:02:33) FORM pkgmap3d view_orientation Right
\i (00:02:34) FORM pkgmap3d hide_board NO
\i (00:02:34) FORM pkgmap3d hide_board YES
\i (00:02:35) FORM pkgmap3d save_current
\i (00:02:36) FORM pkgmap3d done
\i (00:02:39) setwindow pcb
\i (00:02:39) step pkg map
\i (00:02:40) fillin yes
\i (00:02:48) setwindow form.pkgmap3d
\i (00:02:48) FORM pkgmap3d hide_board NO
\i (00:02:52) FORM pkgmap3d view_orientation Top
\i (00:02:58) FORM pkgmap3d view_orientation 'Front Right'
\i (00:03:02) FORM pkgmap3d view_orientation Right
\i (00:03:03) FORM pkgmap3d save_current
\i (00:03:04) FORM pkgmap3d done
\i (00:03:06) setwindow pcb
\i (00:03:06) step pkg map
\i (00:03:07) fillin yes
\i (00:03:16) setwindow form.pkgmap3d
\i (00:03:16) FORM pkgmap3d offset_z --11
\w (00:03:16) Illegal value
\i (00:03:20) FORM pkgmap3d offset_z -15
\i (00:03:22) FORM pkgmap3d offset_z -10
\i (00:03:25) FORM pkgmap3d offset_z -11
\i (00:03:28) FORM pkgmap3d offset_z -10.5
\i (00:03:30) FORM pkgmap3d save_current
\i (00:03:31) FORM pkgmap3d done
\i (00:03:31) setwindow pcb
\i (00:03:31) exit
\e (00:03:31) Do you want to save the changes you made to c1206.dra?
\i (00:03:32) fillin yes
\t (00:03:32) Symbol 'c1206.psm' created.
\t (00:03:32) Journal end - Fri Apr 12 18:51:22 2024
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged ll34
\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/smc/ll34.dra
\i (00:00:02) trapsize 344
\i (00:00:02) trapsize 353
\i (00:00:02) trapsize 344
\i (00:00:03) trapsize 302
\i (00:00:03) trapsize 310
\i (00:00:03) trapsize 319
\i (00:00:03) trapsize 327
\i (00:09:26) exit
\t (00:09:26) Journal end - Sun Jul 28 23:10:09 2024

55
smc/allegro.jrl,1
View File

@@ -1,35 +1,30 @@
\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Fri Apr 12 18:40:47 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=21924 CPUs=12
\t (00:00:02) Journal start - Sun Jul 28 22:59:58 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=21904 CPUs=12
\t (00:00:02) CmdLine= D:\SOFTWARE\Cadence\SPB_17.4\tools\bin\allegro.exe
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "pdfnwb5x6-8l"
\d (00:00:04) Design opened: D:/workspace/GitHub/pcb_lib/smc/pdfnwb5x6-8l.dra
\t (00:00:05) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:05) trapsize 1593
\i (00:00:05) trapsize 1636
\i (00:00:05) trapsize 1593
\i (00:00:05) trapsize 1398
\i (00:00:05) trapsize 1436
\i (00:00:05) trapsize 1476
\t (00:00:05) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:05) trapsize 1515
\i (00:00:14) open
\i (00:00:32) fillin "D:/workspace/Cadence/motor/allegro/motor.brd"
\i (00:00:32) cd "D:/workspace/Cadence/motor/allegro"
\t (00:00:32) Opening existing design...
\t (00:00:32) Grids are drawn 0.3200, 0.3200 apart for enhanced viewing.
\i (00:00:32) trapsize 3981
\t (00:00:33) Grids are drawn 0.6400, 0.6400 apart for enhanced viewing.
\i (00:00:33) trapsize 4079
\t (00:00:33) Grids are drawn 163.8400, 163.8400 apart for enhanced viewing.
\t (00:00:33) Grids are drawn 0.6400, 0.6400 apart for enhanced viewing.
\i (00:00:33) trapsize 4071
\i (00:00:33) setwindow form.mini
\i (00:00:33) FORM mini tree 'Components by refdes'
\i (00:00:33) setwindow pcb
\i (00:00:33) trapsize 4071
\t (00:00:33) > Sending response DoneOpenBoard
\t (00:00:33) Journal end - Fri Apr 12 18:41:19 2024
\i (00:00:05) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged ll34
\d (00:00:05) Design opened: D:/workspace/GitHub/pcb_lib/smc/ll34.dra
\i (00:00:05) trapsize 344
\i (00:00:05) trapsize 353
\i (00:00:05) trapsize 344
\i (00:00:05) trapsize 302
\i (00:00:05) trapsize 310
\i (00:00:05) trapsize 319
\i (00:00:05) trapsize 327
\i (00:00:08) open
\i (00:00:18) fillin "D:/workspace/Cadence/buck_loop/allegro/buck_loop.brd"
\i (00:00:18) cd "D:/workspace/Cadence/buck_loop/allegro"
\t (00:00:18) Opening existing design...
\i (00:00:18) trapsize 252
\i (00:00:19) trapsize 259
\t (00:00:19) Grids are drawn 12.8000, 12.8000 apart for enhanced viewing.
\i (00:00:19) trapsize 276
\i (00:00:19) setwindow form.mini
\i (00:00:19) FORM mini tree 'Components by refdes'
\i (00:00:19) setwindow pcb
\i (00:00:19) trapsize 276
\t (00:00:19) > Sending response DoneOpenBoard
\t (00:00:19) Journal end - Sun Jul 28 23:00:15 2024

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smc/c0603.dra
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23
smc/c0603.log Normal file
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@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : c0603.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun May 5 20:17:37 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = c0603.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
smc/c0603.psm
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BIN
smc/c0805.dra
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23
smc/c0805.log Normal file
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@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : c0805.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun May 5 20:23:08 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = c0805.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
smc/c0805.psm
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4
smc/downrev.log
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : c1206.dra )
( Drawing : ll34.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Apr 12 18:51:22 2024 )
( Date/Time : Sun Jul 28 22:59:48 2024 )
( )
(---------------------------------------------------------------------)

4
smc/downrev.log,1
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : pdfnwb5x6-8l.dra )
( Drawing : f1812.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Apr 12 18:02:09 2024 )
( Date/Time : Sun Jul 28 22:43:54 2024 )
( )
(---------------------------------------------------------------------)

4
smc/downrev.log,2
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : c1206.dra )
( Drawing : ll34.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Apr 12 18:51:22 2024 )
( Date/Time : Sun Jul 28 22:59:48 2024 )
( )
(---------------------------------------------------------------------)

4
smc/downrev.log,3
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : c1206.dra )
( Drawing : ll34.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Apr 12 18:51:22 2024 )
( Date/Time : Sun Jul 28 22:59:48 2024 )
( )
(---------------------------------------------------------------------)

BIN
smc/f1812.dra Normal file
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23
smc/f1812.log Normal file
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@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : f1812.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Jul 28 22:43:54 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = f1812.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
smc/f1812.log,1 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : f1812.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Jul 28 22:36:15 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = f1812.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
smc/f1812.psm Normal file
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BIN
smc/ll34.dra
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23
smc/ll34.log Normal file
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@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : ll34.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Jul 28 22:59:48 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = ll34.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
smc/ll34.psm
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2
smc/master.tag
View File

@@ -1 +1 @@
pdfnwb5x6-8l.dra
ll34.dra

47
smc/padstack_editor.jrl Normal file
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@@ -0,0 +1,47 @@
\t (00:00:01) padstack_editor 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:01) Journal start - Sun Jul 28 22:28:03 2024
\t (00:00:01) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=14944 CPUs=12
\t (00:00:01) CmdLine= d:\software\cadence\spb_17.4\tools\bin\padstack_editor.exe D:\workspace\GitHub\pcb_lib\smc\0201.pad
\t (00:00:01)
\d (00:00:03) QtSignal MainWindow New triggered
\d (00:00:06) QtSignal fileNewDialog dirPath editingFinished 1812
\d (00:00:09) QtSignal fileNewDialog dataCombo CurrentIndexChanged "SMD Pin"
\d (00:00:10) QtSignal fileNewDialog OK clicked
\d (00:00:11) QtSignal GuidedTabsParent NewPads currentRowChanged 1
\d (00:00:11) QtSignal GuidedTabsParent NewPads itemSelectionChanged Square
\d (00:00:11) QtSignal GuidedTabsParent NewPads itemClicked Square
\d (00:00:12) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:15) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
\d (00:00:15) QtSignal 1
\d (00:00:20) QtSignal GuidedTabsParent GuidedTabs currentChanged Start
\d (00:00:22) QtSignal GuidedTabsParent NewPads currentRowChanged 3
\d (00:00:22) QtSignal GuidedTabsParent NewPads itemSelectionChanged Rectangle
\d (00:00:22) QtSignal GuidedTabsParent NewPads itemClicked Rectangle
\d (00:00:24) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:25) QtSignal GuidedDesignLayersTab LayersTable cellClicked 0 "Regular Pad" 0 2
\d (00:00:29) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:29) QtSignal 1
\d (00:00:30) QtSignal GuidedDesignLayersTab PadWidth editingFinished "1.7800"
\d (00:00:39) QtSignal GuidedDesignLayersTab PadHeight editingFinished "3.2000"
\d (00:00:48) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:51) QtSignal GuidedMaskLayersTab LayersTable cellClicked 0 Pad 0 1
\d (00:00:52) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:52) QtSignal 1
\d (00:00:54) QtSignal GuidedMaskLayersTab PadWidth editingFinished "1.7800"
\d (00:01:04) QtSignal GuidedMaskLayersTab PadWidth editingFinished "1.8800"
\d (00:01:07) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:01:07) QtSignal 1
\d (00:01:10) QtSignal GuidedMaskLayersTab PadHeight editingFinished "3.3000"
\d (00:01:14) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 Pad
\d (00:01:14) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 Pad 2 1
\d (00:01:16) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:01:16) QtSignal 1
\d (00:01:17) QtSignal GuidedMaskLayersTab PadWidth editingFinished "1.7800"
\d (00:01:19) QtSignal GuidedMaskLayersTab PadHeight editingFinished "3.2000"
\d (00:01:26) QtSignal GuidedTabsParent GuidedTabs currentChanged Options
\d (00:01:27) QtSignal GuidedTabsParent GuidedTabs currentChanged Summary
\d (00:01:28) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:01:28) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:01:35) QtSignal MainWindow Save triggered
\w (00:01:35) WARNING(SPMHUT-48): Scaled value has been rounded off.
\t (00:01:37) Journal end - Sun Jul 28 22:29:39 2024

14
smc/padstack_editor.jrl,1 Normal file
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@@ -0,0 +1,14 @@
\t (00:00:01) padstack_editor 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:01) Journal start - Sun Jul 28 22:27:40 2024
\t (00:00:01) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=21076 CPUs=12
\t (00:00:01) CmdLine= d:\software\cadence\spb_17.4\tools\bin\padstack_editor.exe D:\workspace\GitHub\pcb_lib\smc\0201.pad
\t (00:00:01)
\d (00:00:03) QtSignal MainWindow New triggered
\d (00:00:07) QtSignal fileNewDialog dirPath editingFinished 1812
\d (00:00:08) QtSignal fileNewDialog dataCombo CurrentIndexChanged "SMD Pin"
\d (00:00:10) QtSignal fileNewDialog OK clicked
\d (00:00:12) QtSignal GuidedTabsParent NewPads currentRowChanged 1
\d (00:00:12) QtSignal GuidedTabsParent NewPads itemSelectionChanged Square
\d (00:00:12) QtSignal GuidedTabsParent NewPads itemClicked Square
\d (00:00:21) QtFillin No
\t (00:00:21) Journal end - Sun Jul 28 22:28:01 2024

128
smc/param_read.log Normal file
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@@ -0,0 +1,128 @@
(---------------------------------------------------------------------)
( )
( Parameter File READ )
( )
( Drawing : smb.dra )
( Software Version : 17.4S035 )
( Date/Time : Thu Jul 11 02:24:02 2024 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/¹¤×÷¿â/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : smb.dra
Reading...parameter_header:
Reading...db_common_type:
Reading...grid_parms_type:
WARNING: The value of element <etchcount> is not equal to the number of
user defined subclass under ETCH class.
Reading...UnusedPadsSuppressionSettings:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
WARNING: Unmatched Data - Field Name: subclass , Value: "SIGNEDTOP"
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
WARNING: Unmatched Data - Field Name: subclass , Value: "SIGNEDBOTTOM"
Reading...art_class_type:
Reading...art_class_type:
Reading...color_table_table:
Reading...ColorParmType:
Reading...profileCustomColors:
Reading...text_size_table:
Reading...drf_parm_type:
Reading...av_parm_type:
Reading...dynfill_parm_type:
Reading...probe_parm_type:
Reading...ifp_parm_type:
Reading...ministat_parm_type:
WARNING: Unmatched Data - Field Name: acon_active_sc , Value: "SIGNEDTOP"
Reading...ats_parm_type:
Reading...placement_parameter_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
..... Total number of errors: 0.
..... Total number of warnings: 4.

BIN
smc/r0805.dra Normal file
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