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XerolySkinner
2024-08-02 02:32:24 +08:00
parent 70f78434d9
commit 79562d2813
152 changed files with 827512 additions and 4998 deletions
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80
chip/allegro.jrl Normal file
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\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Mon Jul 29 04:50:28 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=13504 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\chip\lqfp64.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged lqfp64
\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/chip/lqfp64.dra
\t (00:00:02) Grids are drawn 0.200, 0.200 apart for enhanced viewing.
\i (00:00:02) trapsize 135
\i (00:00:02) trapsize 139
\i (00:00:02) trapsize 135
\i (00:00:03) trapsize 118
\i (00:00:03) trapsize 122
\i (00:00:03) trapsize 125
\t (00:00:03) Grids are drawn 0.200, 0.200 apart for enhanced viewing.
\i (00:00:03) trapsize 128
\i (00:00:06) delete
\i (00:00:08) pick grid 0.029 2.342
\t (00:00:08) last pick: 0.000 2.300
\t (00:00:08) Shape "Package Geometry/Silkscreen_Top"
\i (00:00:08) prepopup 7.913 10.740
\i (00:00:09) done
\i (00:00:14) shape add rect
\i (00:00:16) pick 0 0
\t (00:00:16) last pick: 0.000 0.000
\i (00:00:18) zoom in 1
\i (00:00:18) setwindow pcb
\i (00:00:18) zoom in -5.004 5.424
\i (00:00:18) trapsize 64
\i (00:00:18) zoom in 1
\i (00:00:18) setwindow pcb
\i (00:00:18) zoom in -5.004 5.424
\i (00:00:18) trapsize 32
\i (00:00:18) zoom in 1
\i (00:00:18) setwindow pcb
\i (00:00:18) zoom in -5.004 5.424
\i (00:00:18) trapsize 16
\i (00:00:18) zoom in 1
\i (00:00:18) setwindow pcb
\i (00:00:18) zoom in -5.004 5.425
\i (00:00:18) trapsize 8
\i (00:00:18) zoom in 1
\i (00:00:18) setwindow pcb
\i (00:00:18) zoom in -5.004 5.425
\i (00:00:18) trapsize 4
\i (00:00:19) pick grid -4.991 5.049
\t (00:00:19) last pick: -5.000 5.000
\i (00:00:19) zoom out 1
\i (00:00:19) setwindow pcb
\i (00:00:19) zoom out -4.944 5.410
\i (00:00:19) trapsize 8
\i (00:00:19) zoom out 1
\i (00:00:19) setwindow pcb
\i (00:00:19) zoom out -4.945 5.409
\i (00:00:19) trapsize 16
\i (00:00:19) zoom out 1
\i (00:00:19) setwindow pcb
\i (00:00:19) zoom out -4.945 5.409
\i (00:00:19) trapsize 32
\i (00:00:19) zoom out 1
\i (00:00:19) setwindow pcb
\i (00:00:19) zoom out -4.944 5.410
\i (00:00:19) trapsize 64
\i (00:00:20) prepopup -4.945 5.411
\i (00:00:21) done
\i (00:00:22) delete
\i (00:00:23) pick grid -4.689 4.679
\t (00:00:23) last pick: -4.700 4.700
\t (00:00:23) Line "Package Geometry/Silkscreen_Top"
\i (00:00:24) pick grid -7.886 5.244
\t (00:00:24) last pick: -7.900 5.200
\i (00:00:24) prepopup -7.886 5.244
\i (00:00:25) done
\i (00:00:26) save
\i (00:00:26) fillin yes
\t (00:00:26) Symbol 'lqfp64.psm' created.
\i (00:00:27) exit
\t (00:00:28) Journal end - Mon Jul 29 04:50:54 2024

111
chip/allegro.jrl,1 Normal file
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\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Mon Jul 29 04:48:36 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=18232 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\chip\sop-8.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sop-8"
\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/chip/sop-8.dra
\i (00:00:02) trapsize 106
\i (00:00:02) trapsize 109
\i (00:00:03) trapsize 106
\i (00:00:03) trapsize 93
\i (00:00:03) trapsize 95
\i (00:00:03) trapsize 98
\i (00:00:03) trapsize 98
\i (00:00:10) shape add rect
\i (00:00:14) setwindow form.mini
\i (00:00:14) FORM mini class 'PACKAGE GEOMETRY'
\i (00:00:16) FORM mini subclass SILKSCREEN_TOP
\i (00:00:16) setwindow pcb
\i (00:00:16) updateport CVPane
\i (00:00:21) pick 0 0
\t (00:00:21) last pick: 0.000 0.000
\i (00:00:23) zoom in 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom in -0.968 2.055
\i (00:00:23) trapsize 49
\i (00:00:23) zoom in 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom in -0.968 2.055
\i (00:00:23) trapsize 25
\i (00:00:23) zoom in 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom in -0.968 2.056
\i (00:00:23) trapsize 12
\i (00:00:23) zoom in 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom in -0.968 2.056
\i (00:00:23) trapsize 6
\i (00:00:23) zoom out 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom out -1.143 1.793
\i (00:00:23) trapsize 12
\i (00:00:23) zoom out 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom out -1.142 1.793
\i (00:00:23) trapsize 25
\i (00:00:23) zoom out 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom out -1.142 1.793
\i (00:00:23) trapsize 49
\i (00:00:24) zoom in 1
\i (00:00:24) setwindow pcb
\i (00:00:24) zoom in -1.398 2.469
\i (00:00:24) trapsize 25
\i (00:00:24) zoom in 1
\i (00:00:24) setwindow pcb
\i (00:00:24) zoom in -1.398 2.469
\i (00:00:24) trapsize 12
\i (00:00:24) zoom in 1
\i (00:00:24) setwindow pcb
\i (00:00:24) zoom in -1.398 2.469
\i (00:00:24) trapsize 6
\i (00:00:26) pick grid -1.469 2.450
\t (00:00:26) last pick: -1.500 2.500
\i (00:00:27) prepopup -1.205 2.640
\i (00:00:28) done
\i (00:00:31) delete
\i (00:00:33) pick grid -1.096 2.170
\t (00:00:33) last pick: -1.100 2.200
\t (00:00:33) Line "Package Geometry/Silkscreen_Top"
\i (00:00:33) prepopup -1.049 2.662
\i (00:00:34) done
\i (00:00:34) zoom out 1
\i (00:00:34) setwindow pcb
\i (00:00:34) zoom out -1.049 2.662
\i (00:00:34) trapsize 12
\i (00:00:34) zoom out 1
\i (00:00:34) setwindow pcb
\i (00:00:34) zoom out -1.050 2.662
\i (00:00:34) trapsize 25
\i (00:00:34) zoom out 1
\i (00:00:34) setwindow pcb
\i (00:00:34) zoom out -1.049 2.662
\i (00:00:35) trapsize 49
\i (00:00:35) zoom out 1
\i (00:00:35) setwindow pcb
\i (00:00:35) zoom out -1.049 2.662
\i (00:00:35) trapsize 98
\i (00:00:35) zoom out 1
\i (00:00:35) setwindow pcb
\i (00:00:35) zoom out 1.288 2.270
\i (00:00:35) trapsize 98
\i (00:00:35) save
\i (00:00:36) fillin yes
\t (00:00:36) Symbol 'sop-8.psm' created.
\i (00:00:37) delete
\i (00:00:39) pick grid 0.366 3.447
\t (00:00:39) last pick: 0.400 3.400
\t (00:00:39) Text "Last Edit:2024-3-16"
\i (00:00:40) pick grid 0.582 -3.398
\t (00:00:40) last pick: 0.600 -3.400
\t (00:00:40) Text "Approved[2]"
\i (00:00:40) prepopup 0.582 -3.398
\i (00:00:41) done
\i (00:00:42) save
\i (00:00:42) fillin yes
\t (00:00:42) Symbol 'sop-8.psm' created.
\i (00:00:43) exit
\t (00:00:44) Journal end - Mon Jul 29 04:49:18 2024

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chip/downrev.log Normal file
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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : lqfp64.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:50:52 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
chip/downrev.log,1 Normal file
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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : sop-8.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:49:17 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
chip/downrev.log,2 Normal file
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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : lqfp64.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:50:52 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
chip/downrev.log,3 Normal file
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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : lqfp64.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:50:52 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

BIN
chip/lqfp64.dra
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23
chip/lqfp64.log Normal file
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(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : lqfp64.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:50:52 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = lqfp64.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
chip/lqfp64.log,1 Normal file
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(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : lqfp64.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:47:43 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = lqfp64.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

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chip/lqfp64.psm
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1
chip/master.tag Normal file
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lqfp64.dra

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chip/sop-8.dra
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23
chip/sop-8.log Normal file
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(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : sop-8.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:49:17 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = sop-8.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
chip/sop-8.log,1 Normal file
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(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : sop-8.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:49:11 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = sop-8.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
chip/sop-8.psm
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