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This commit is contained in:
XerolySkinner
2025-09-27 11:01:31 +08:00
parent 7394f89550
commit b67fb10b08
109 changed files with 42752 additions and 1562 deletions
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57
chip/allegro.jrl
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@@ -1,45 +1,20 @@
\t (00:00:02) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Fri Apr 25 15:00:50 2025
\t (00:00:02) Host=XEROLYSKINNER User=Xeroly Pid=5220 CPUs=16
\t (00:00:02) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\chip\tqfp-48-ep.dra
\t (00:00:02) Journal start - Sat May 10 04:57:54 2025
\t (00:00:02) Host=XEROLYSKINNER User=Xeroly Pid=35792 CPUs=16
\t (00:00:02) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "tqfp-48-ep"
\d (00:00:04) Design opened: D:/Workspace/GitHub/pcb_lib/chip/tqfp-48-ep.dra
\t (00:00:05) Grids are drawn 0.160, 0.160 apart for enhanced viewing.
\i (00:00:05) trapsize 102
\i (00:00:05) trapsize 104
\i (00:00:05) trapsize 102
\t (00:00:05) Grids are drawn 0.160, 0.160 apart for enhanced viewing.
\i (00:00:05) trapsize 108
\t (00:00:05) Opening existing design...
\i (00:00:05) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "wsoic-8"
\d (00:00:05) Design opened: D:/workspace/GitHub/pcb_lib/chip/wsoic-8.dra
\t (00:00:05) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
\i (00:00:05) trapsize 74
\i (00:00:12) add pin
\i (00:00:16) setwindow form.mini
\i (00:00:16) FORM mini pad_name tqfp-48-ep-gnd
\w (00:00:16) WARNING(SPMHUT-48): Scaled value has been rounded off.
\t (00:00:16) Using 'TQFP-48-EP-GND.pad'.
\e (00:00:20) Command not found: X 0 0
\i (00:00:22) setwindow pcb
\i (00:00:22) pick 0 0
\t (00:00:22) last pick: 0.000 0.000
\t (00:00:22) Using 'TQFP-48-EP-GND.pad'.
\i (00:00:23) prepopup 6.355 6.505
\i (00:00:27) oops
\t (00:00:27) Using 'TQFP-48-EP-GND.pad'.
\i (00:00:32) setwindow form.mini
\i (00:00:32) FORM mini text_name pin
\i (00:00:34) FORM mini next_pin_number 49
\i (00:00:36) setwindow pcb
\i (00:00:36) pick 0 0
\t (00:00:36) last pick: 0.000 0.000
\t (00:00:36) Using 'TQFP-48-EP-GND.pad'.
\i (00:00:37) prepopup 7.902 3.812
\i (00:00:38) done
\t (00:00:38) Exiting from Add Pin.
\i (00:00:39) save
\i (00:00:40) fillin yes
\t (00:00:40) Symbol 'tqfp-48-ep.psm' created.
\i (00:00:41) exit
\t (00:00:41) Journal end - Fri Apr 25 15:01:29 2025
\i (00:00:05) trapsize 71
\i (00:00:05) trapsize 73
\i (00:00:06) trapsize 71
\i (00:00:06) trapsize 76
\t (00:00:06) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
\i (00:00:06) trapsize 79
\i (00:00:06) trapsize 53
\i (00:00:20) new
\i (00:00:37) newdrawfillin "smd_4.dra" "Package Symbol (Wizard)"
\t (00:00:37) Journal end - Sat May 10 04:58:28 2025

1408
chip/allegro.jrl,1
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4
chip/batch_drc.log
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@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : tqfp-48-ep.dra )
( Drawing : sym_template.dra )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:37:19 2025 )
( Date/Time : Sat May 10 04:32:11 2025 )
( )
(---------------------------------------------------------------------)

4
chip/batch_drc.log,1
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@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : sym_template.dra )
( Drawing : tqfp-48-ep.dra )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:20:55 2025 )
( Date/Time : Thu Apr 24 23:35:37 2025 )
( )
(---------------------------------------------------------------------)

4
chip/batch_drc.log,2
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@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : sym_template.dra )
( Drawing : tqfp-48-ep.dra )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:20:56 2025 )
( Date/Time : Thu Apr 24 23:37:19 2025 )
( )
(---------------------------------------------------------------------)

4
chip/batch_drc.log,3
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@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : tqfp-48-ep.dra )
( Drawing : sym_template.dra )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:35:37 2025 )
( Date/Time : Sat May 10 04:32:11 2025 )
( )
(---------------------------------------------------------------------)

29
chip/dangling_lines.rpt Normal file
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@@ -0,0 +1,29 @@
(---------------------------------------------------------------------)
( )
( Dangling Line, Via and Antenna Report )
( )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 04:34:41 2025 )
( )
(---------------------------------------------------------------------)
Report methodology:
- Dangling lines have at least one end not connected.
- Dangling vias have one or no connection
- Plus are not a test, thieving or netshort property via.
- Antenna vias do not have connections on their start and end layers.
- Plus they are not a thieving vias.
- Optionally, VOLTAGE nets, testvias and through vias can be suppressed with
the environment variable report_antennavia.
- Section may be suppressed by variable report_noantennavia.
- Not part of the current partition.
- To suppress items in dangle report add the OK_DANGLE property to the via
or connect line.
<< Summary >>
Total dangling lines: 0
Total dangling vias: 0
Total antenna vias: 0

4
chip/downrev.log
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@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : tqfp-48-ep.dra )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri Apr 25 15:01:28 2025 )
( Date/Time : Sat May 10 04:45:31 2025 )
( )
(---------------------------------------------------------------------)

4
chip/downrev.log,1
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@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : tqfp-48-ep-gnd.pad )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri Apr 25 15:00:42 2025 )
( Date/Time : Sat May 10 04:45:17 2025 )
( )
(---------------------------------------------------------------------)

4
chip/downrev.log,2
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@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : tqfp-48-ep.dra )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri Apr 25 15:01:28 2025 )
( Date/Time : Sat May 10 04:45:31 2025 )
( )
(---------------------------------------------------------------------)

4
chip/downrev.log,3
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@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : tqfp-48-ep.dra )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri Apr 25 15:01:28 2025 )
( Date/Time : Sat May 10 04:45:31 2025 )
( )
(---------------------------------------------------------------------)

2
chip/master.tag
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@@ -1 +1 @@
tqfp-48-ep.dra
wsoic-8.dra

27
chip/padstack_editor.jrl
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@@ -1,24 +1,7 @@
\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:00) Journal start - Fri Apr 25 15:00:00 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=24896 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\chip\tqfp-48-ep-gnd.pad
\t (00:00:00) Journal start - Sat May 10 04:28:20 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=37520 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\chip\wsoic-8.pad
\t (00:00:00)
\d (00:00:02) QtSignal GuidedTabsParent NewPads currentRowChanged 1
\d (00:00:02) QtSignal GuidedTabsParent NewPads itemSelectionChanged Square
\d (00:00:02) QtSignal GuidedTabsParent NewPads itemClicked Square
\d (00:00:03) QtFillin Yes
\d (00:00:05) QtSignal GuidedTabsParent GuidedStartTab keyPressEvent 16777251 134217728 false 1
\d (00:00:07) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:08) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
\d (00:00:08) QtSignal 1
\d (00:00:22) QtSignal GuidedDesignLayersTab PadWidth editingFinished "5.0000"
\d (00:00:26) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:27) QtSignal GuidedMaskLayersTab LayersTable cellClicked 0 "Regular Pad" 0 1
\d (00:00:29) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0000"
\d (00:00:36) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0600"
\d (00:00:37) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
\d (00:00:37) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 "Regular Pad" 2 1
\d (00:00:40) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0000"
\d (00:00:42) QtSignal MainWindow Save triggered
\d (00:00:43) QtSignal MainWindow Exit triggered
\t (00:00:43) Journal end - Fri Apr 25 15:00:44 2025
\d (00:00:05) QtSignal MainWindow Exit triggered
\t (00:00:05) Journal end - Sat May 10 04:28:26 2025

45
chip/padstack_editor.jrl,1
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@@ -1,21 +1,24 @@
\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:00) Journal start - Thu Apr 24 23:36:01 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=13068 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\chip\tqfp-48-ep.pad
\t (00:00:00)
\d (00:00:03) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:11) QtSignal GuidedDesignLayersTab PadHeight editingFinished "0.2600"
\d (00:00:11) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777220 0 false 1 "
"
\d (00:00:13) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:14) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:18) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:28) QtSignal GuidedMaskLayersTab PadHeight editingFinished "0.2800"
\d (00:00:28) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
\d (00:00:30) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
\d (00:00:32) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 "Regular Pad" 2 1
\d (00:00:33) QtSignal GuidedMaskLayersTab PadHeight editingFinished "0.2600"
\d (00:00:33) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
\d (00:00:36) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:00) Journal start - Fri Apr 25 15:00:00 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=24896 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\chip\tqfp-48-ep-gnd.pad
\t (00:00:00)
\d (00:00:02) QtSignal GuidedTabsParent NewPads currentRowChanged 1
\d (00:00:02) QtSignal GuidedTabsParent NewPads itemSelectionChanged Square
\d (00:00:02) QtSignal GuidedTabsParent NewPads itemClicked Square
\d (00:00:03) QtFillin Yes
\d (00:00:05) QtSignal GuidedTabsParent GuidedStartTab keyPressEvent 16777251 134217728 false 1
\d (00:00:07) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:08) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
\d (00:00:08) QtSignal 1
\d (00:00:22) QtSignal GuidedDesignLayersTab PadWidth editingFinished "5.0000"
\d (00:00:26) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:27) QtSignal GuidedMaskLayersTab LayersTable cellClicked 0 "Regular Pad" 0 1
\d (00:00:29) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0000"
\d (00:00:36) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0600"
\d (00:00:37) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
\d (00:00:37) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 "Regular Pad" 2 1
\d (00:00:40) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0000"
\d (00:00:42) QtSignal MainWindow Save triggered
\d (00:00:43) QtSignal MainWindow Exit triggered
\t (00:00:43) Journal end - Fri Apr 25 15:00:44 2025

8
chip/param_read.log
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@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : tqfp-48-ep.dra )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:38:15 2025 )
( Date/Time : Sat May 10 04:32:23 2025 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/Workspace/GitHub/pcb_lib/chip/tqfp-48-ep.dra
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/workspace/GitHub/pcb_lib/chip/wsoic-8.dra
Reading...parameter_header:
Reading...db_common_type:

6
chip/param_read.log,1
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@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : ssop-4.dra )
( Drawing : htssop-56.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 22:01:23 2024 )
( Date/Time : Wed Aug 7 01:10:16 2024 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/workspace/GitHub/pcb_lib/chip/ssop-4.dra
Layout Name : D:/workspace/GitHub/pcb_lib/chip/htssop-56.dra
Reading...parameter_header:
Reading...db_common_type:

10
chip/param_read.log,2
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@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : htssop-56.dra )
( Software Version : 17.4S035 )
( Date/Time : Wed Aug 7 01:10:16 2024 )
( Drawing : wsop-16.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:01:05 2025 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/workspace/GitHub/pcb_lib/chip/htssop-56.dra
Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/Workspace/GitHub/pcb_lib/chip/wsop-16.dra
Reading...parameter_header:
Reading...db_common_type:

6
chip/param_read.log,3
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@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : wsop-16.dra )
( Drawing : tqfp-48-ep.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:01:05 2025 )
( Date/Time : Thu Apr 24 23:38:15 2025 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/Workspace/GitHub/pcb_lib/chip/wsop-16.dra
Layout Name : D:/Workspace/GitHub/pcb_lib/chip/tqfp-48-ep.dra
Reading...parameter_header:
Reading...db_common_type:

1
chip/stepFacetFiles4Map/stepFileInfo.txt
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@@ -9,6 +9,7 @@ wsop_16.step ! 827104 ! 1745399292
ssop-16.step ! 873879 ! 1745399033
tqfp-48.STEP ! 166679 ! 1745422272
D8-L.step ! 282667 ! 1568096060
wsop-16.step ! 584105 ! 1746823035
SOP-16.STEP ! 3778717 ! 1722501952
DIP_2x5.step ! 720870 ! 1710578258
SSOP-8.step ! 755497 ! 1712718221

1
chip/stepFacetFiles4Map/stepFileInfo.txt,1
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@@ -9,6 +9,7 @@ wsop_16.step ! 827104 ! 1745399292
ssop-16.step ! 873879 ! 1745399033
tqfp-48.STEP ! 166679 ! 1745422272
D8-L.step ! 282667 ! 1568096060
wsop-16.step ! 584105 ! 1746823035
SOP-16.STEP ! 3778717 ! 1722501952
DIP_2x5.step ! 720870 ! 1710578258
SSOP-8.step ! 755497 ! 1712718221

17160
chip/stepFacetFiles4Map/wsop-16.xml Normal file
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BIN
chip/wsoic-8.dra Normal file
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23
chip/wsoic-8.log Normal file
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@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 04:45:31 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = wsoic-8.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

23
chip/wsoic-8.log,1 Normal file
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@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 04:34:55 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = wsoic-8.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

23
chip/wsoic-8.log,2 Normal file
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@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 04:35:43 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = wsoic-8.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

23
chip/wsoic-8.log,3 Normal file
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@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 04:45:17 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = wsoic-8.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

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chip/wsoic-8.pad Normal file
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chip/wsoic-8.psm Normal file
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chip/wsop-16.dra
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2
chip/wsop-16.log
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@@ -4,7 +4,7 @@
( )
( Drawing : wsop-16.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:37:56 2025 )
( Date/Time : Sat May 3 00:59:54 2025 )
( )
(---------------------------------------------------------------------)

2
chip/wsop-16.log,1
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@@ -4,7 +4,7 @@
( )
( Drawing : wsop-16.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:18:34 2025 )
( Date/Time : Wed Apr 23 17:18:43 2025 )
( )
(---------------------------------------------------------------------)

2
chip/wsop-16.log,2
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@@ -4,7 +4,7 @@
( )
( Drawing : wsop-16.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:18:43 2025 )
( Date/Time : Wed Apr 23 17:37:39 2025 )
( )
(---------------------------------------------------------------------)

2
chip/wsop-16.log,3
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@@ -4,7 +4,7 @@
( )
( Drawing : wsop-16.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:37:39 2025 )
( Date/Time : Wed Apr 23 17:37:56 2025 )
( )
(---------------------------------------------------------------------)

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chip/wsop-16.psm
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