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XerolySkinner
2025-09-27 11:01:31 +08:00
parent 7394f89550
commit b67fb10b08
109 changed files with 42752 additions and 1562 deletions
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other/PCB1094M4.dra
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other/USR-WIFI232-A2.dra Normal file
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other/allegro.jrl
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@@ -1,133 +1,29 @@
\t (00:02:32) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:02:32) Journal start - Sun Apr 27 22:55:41 2025
\t (00:02:32) Host=XEROLYSKINNER User=Xeroly Pid=2016 CPUs=16
\t (00:02:32) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe -mpssession Xeroly -proj d:\workspace\cadence\cedarmotor\cedarmotor.opj d:/workspace/cadence/cedarmotor/allegro/cedarmotor.brd
\t (00:02:32)
\t (00:02:32) Starting new design...
\i (00:02:32) trapsize 14970
\i (00:02:32) trapsize 15291
\i (00:02:32) trapsize 14970
\t (00:02:32) Grids are drawn 1300.4800, 1300.4800 apart for enhanced viewing.
\i (00:02:32) trapsize 19763
\i (00:02:32) trapsize 19763
\i (00:02:32) trapsize 18903
\i (00:02:35) param in
\i (00:02:37) setwindow form.parm_in
\i (00:02:37) FORM parm_in browse
\i (00:02:39) fillin "D:/workspace/GitHub/pcb_lib/XerolySkinner.prm"
\i (00:02:40) FORM parm_in execute
\t (00:02:40) Starting Importing parameter file...
\w (00:02:40) WARNING(SPMHGE-269): param in had warnings, use Viewlog to review the log file.
\t (00:02:40) Opening existing design...
\t (00:02:40) Grids are drawn 2.5400, 2.5400 apart for enhanced viewing.
\i (00:02:40) setwindow pcb
\i (00:02:40) trapsize 18903
\i (00:02:40) trapsize 19289
\i (00:02:41) trapsize 18903
\t (00:02:41) Grids are drawn 2.5400, 2.5400 apart for enhanced viewing.
\i (00:02:41) trapsize 19477
\i (00:02:42) setwindow text
\i (00:02:42) close
\i (00:02:43) setwindow form.parm_in
\i (00:02:43) FORM parm_in cancel
\i (00:02:44) setwindow pcb
\i (00:02:44) zoom in 1
\i (00:02:44) setwindow pcb
\i (00:02:44) zoom in -9.2655 -6.9282
\t (00:02:44) Grids are drawn 1.2700, 1.2700 apart for enhanced viewing.
\i (00:02:44) trapsize 9738
\i (00:02:45) zoom in 1
\i (00:02:45) setwindow pcb
\i (00:02:45) zoom in 1.4468 -0.6956
\i (00:02:45) trapsize 4869
\i (00:02:47) add pin
\i (00:02:49) setwindow form.mini
\i (00:02:49) FORM mini x_count 2
\i (00:02:55) FORM mini x_spacing 6.9000
\i (00:02:59) FORM mini next_pin_number 1
\i (00:02:59) FORM mini pad_browse
\i (00:03:21) fillin "Thr-2r3-3r0"
\t (00:03:21) Using 'THR-2R3-3R0.pad'.
\e (00:03:39) Command not found: X -3.45 0
\i (00:03:46) setwindow pcb
\i (00:03:46) pick -3.45 0
\t (00:03:46) last pick: -3.4500 0.0000
\t (00:03:46) Using 'THR-2R3-3R0.pad'.
\i (00:03:48) prepopup -1.6694 6.2187
\i (00:03:48) done
\t (00:03:48) Exiting from Add Pin.
\i (00:03:49) zoom in 1
\i (00:03:49) setwindow pcb
\i (00:03:49) zoom in -1.0851 1.2521
\i (00:03:49) trapsize 2435
\i (00:03:49) zoom in 1
\i (00:03:49) setwindow pcb
\i (00:03:49) zoom in -1.0851 1.2522
\i (00:03:49) trapsize 1217
\i (00:04:00) shape add rect
\i (00:04:02) setwindow form.mini
\i (00:04:02) FORM mini class 'PACKAGE GEOMETRY'
\i (00:04:04) FORM mini subclass PLACE_BOUND_TOP
\i (00:04:04) setwindow pcb
\i (00:04:04) updateport CVPane
\i (00:04:21) pick -3.95 3.95
\t (00:04:21) last pick: -3.9500 3.9500
\i (00:04:26) pick 3.95 -3.95
\t (00:04:26) last pick: 3.9500 -3.9500
\i (00:04:27) prepopup -2.4485 7.5335
\i (00:04:28) done
\i (00:04:29) add rect
\i (00:04:31) setwindow form.mini
\i (00:04:31) FORM mini subclass ASSEMBLY_TOP
\i (00:04:31) setwindow pcb
\i (00:04:31) updateport CVPane
\i (00:04:35) pick -3.95 3.95
\t (00:04:35) last pick: -3.9500 3.9500
\i (00:04:39) pick 3.95 -3.95
\t (00:04:39) last pick: 3.9500 -3.9500
\i (00:04:40) prepopup 8.8968 5.0989
\i (00:04:41) done
\i (00:04:48) add rect
\i (00:04:51) shape add rect
\i (00:04:54) setwindow form.mini
\i (00:04:54) FORM mini subclass SILKSCREEN_TOP
\i (00:04:54) setwindow pcb
\i (00:04:54) updateport CVPane
\i (00:05:00) pick -3.95 3.95
\t (00:05:00) last pick: -3.9500 3.9500
\i (00:05:05) pick 3.95 -3.95
\t (00:05:05) last pick: 3.9500 -3.9500
\i (00:05:06) prepopup 6.1214 5.3423
\i (00:05:07) done
\i (00:05:08) label refdes
\t (00:05:08) Pick text location.
\i (00:05:11) setwindow form.mini
\i (00:05:11) FORM mini text_name asm
\i (00:05:11) setwindow pcb
\i (00:05:11) pick grid -0.2573 6.1457
\t (00:05:11) last pick: 0.0000 5.0800
\t (00:05:11) Enter text string.
\i (00:05:14) setwindow pcb
\i (00:05:14) pick 0.0000 5.0800
\i (00:05:19) pick grid -2.5945 4.7337
\t (00:05:19) last pick: -2.5400 5.0800
\t (00:05:19) Refdes of this subclass is already defined, change subclass.
\i (00:05:23) setwindow form.mini
\i (00:05:23) FORM mini subclass SILKSCREEN_TOP
\i (00:05:23) setwindow pcb
\i (00:05:23) updateport CVPane
\i (00:05:25) setwindow form.mini
\i (00:05:25) FORM mini text_name ski
\i (00:05:26) setwindow pcb
\i (00:05:26) pick grid -2.7406 4.9528
\t (00:05:26) last pick: -2.5400 5.0800
\t (00:05:26) Enter text string.
\i (00:05:28) setwindow pcb
\i (00:05:28) pick -2.5400 5.0800
\i (00:05:29) save
\t (00:05:29) Symbol 'pcb1094m4.psm' created.
\i (00:05:31) save
\i (00:05:31) fillin yes
\t (00:05:32) Symbol 'pcb1094m4.psm' created.
\i (00:05:33) exit
\t (00:05:33) Journal end - Sun Apr 27 22:58:42 2025
\t (00:00:02) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Sat May 10 13:22:20 2025
\t (00:00:02) Host=XEROLYSKINNER User=Xeroly Pid=20404 CPUs=16
\t (00:00:02) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "rj45-8p8c"
\d (00:00:04) Design opened: D:/Workspace/GitHub/pcb_lib/other/rj45-8p8c.dra
\i (00:00:04) trapsize 2935
\i (00:00:05) trapsize 3019
\i (00:00:05) trapsize 2935
\i (00:00:05) trapsize 3259
\i (00:00:05) trapsize 3259
\i (00:00:05) trapsize 2106
\i (00:00:08) open
\i (00:00:17) fillin "D:/Workspace/Cadence/cedarmain/allegro/cedarmain.brd"
\i (00:00:17) cd "D:/Workspace/Cadence/cedarmain/allegro"
\t (00:00:17) Opening existing design...
\t (00:00:18) Grids are drawn 0.0800, 0.0800 apart for enhanced viewing.
\i (00:00:18) trapsize 951
\i (00:00:18) trapsize 971
\t (00:00:18) Grids are drawn 0.0800, 0.0800 apart for enhanced viewing.
\i (00:00:18) trapsize 988
\t (00:00:18) Grids are drawn 0.1600, 0.1600 apart for enhanced viewing.
\i (00:00:18) trapsize 1013
\i (00:00:18) trapsize 1013
\t (00:00:18) > Sending response DoneOpenBoard
\t (00:00:18) Journal end - Sat May 10 13:22:37 2025

235
other/allegro.jrl,1
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@@ -1,193 +1,42 @@
\t (00:02:25) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:02:25) Journal start - Sun Apr 27 22:49:48 2025
\t (00:02:25) Host=XEROLYSKINNER User=Xeroly Pid=17144 CPUs=16
\t (00:02:25) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe
\t (00:02:25)
\t (00:02:25) Starting new design...
\i (00:02:25) trapsize 14970
\i (00:02:25) trapsize 15291
\i (00:02:25) trapsize 14970
\t (00:02:25) Grids are drawn 1300.4800, 1300.4800 apart for enhanced viewing.
\i (00:02:25) trapsize 19763
\i (00:02:25) trapsize 19763
\i (00:02:26) trapsize 18903
\i (00:02:29) param in
\i (00:02:31) setwindow form.parm_in
\i (00:02:31) FORM parm_in browse
\i (00:02:34) fillin "D:/workspace/GitHub/pcb_lib/XerolySkinner.prm"
\i (00:02:34) FORM parm_in execute
\t (00:02:34) Starting Importing parameter file...
\w (00:02:35) WARNING(SPMHGE-269): param in had warnings, use Viewlog to review the log file.
\t (00:02:35) Opening existing design...
\t (00:02:35) Grids are drawn 2.5400, 2.5400 apart for enhanced viewing.
\i (00:02:35) setwindow pcb
\i (00:02:35) trapsize 18903
\i (00:02:35) trapsize 19289
\i (00:02:35) trapsize 18903
\t (00:02:35) Grids are drawn 2.5400, 2.5400 apart for enhanced viewing.
\i (00:02:35) trapsize 19477
\i (00:02:36) setwindow text
\i (00:02:36) close
\i (00:02:37) setwindow form.parm_in
\i (00:02:37) FORM parm_in cancel
\i (00:02:39) setwindow pcb
\i (00:02:39) prmed
\i (00:02:44) setwindow form.prmedit
\i (00:02:44) FORM prmedit design
\i (00:02:48) FORM prmedit done
\i (00:02:49) setwindow pcb
\i (00:02:49) label refdes
\t (00:02:49) Pick text location.
\i (00:02:51) add pin
\i (00:02:52) setwindow form.mini
\i (00:02:52) FORM mini pad_name pcb-10b
\t (00:02:52) Using 'PCB-10B.pad'.
\i (00:02:54) setwindow pcb
\i (00:02:54) pick 0 0
\t (00:02:54) last pick: 0.0000 0.0000
\t (00:02:54) Using 'PCB-10B.pad'.
\i (00:02:55) prepopup 14.4964 -20.1725
\i (00:02:55) done
\t (00:02:55) Exiting from Add Pin.
\i (00:02:56) zoom in 1
\i (00:02:56) setwindow pcb
\i (00:02:56) zoom in 1.2521 0.4730
\i (00:02:56) trapsize 9738
\i (00:02:56) zoom in 1
\i (00:02:56) setwindow pcb
\i (00:02:56) zoom in 1.2521 0.4730
\i (00:02:56) trapsize 4869
\i (00:02:56) zoom in 1
\i (00:02:56) setwindow pcb
\i (00:02:56) zoom in 1.2521 0.4730
\i (00:02:56) trapsize 2435
\i (00:02:58) undo
\i (00:02:58) trapsize 19477
\i (00:02:59) add pin
\i (00:03:01) setwindow form.mini
\i (00:03:01) FORM mini next_pin_number 1
\i (00:03:02) FORM mini pad_name pcb-10b
\t (00:03:02) Using 'PCB-10B.pad'.
\e (00:03:04) Command not found: x0 0
\i (00:03:06) setwindow pcb
\i (00:03:06) pick 0 0
\t (00:03:06) last pick: 0.0000 0.0000
\t (00:03:06) Using 'PCB-10B.pad'.
\i (00:03:07) prepopup 16.4441 11.7696
\i (00:03:08) done
\t (00:03:08) Exiting from Add Pin.
\i (00:03:08) zoom in 1
\i (00:03:08) setwindow pcb
\i (00:03:08) zoom in -2.6433 -4.2015
\i (00:03:08) trapsize 9738
\i (00:03:09) zoom in 1
\i (00:03:09) setwindow pcb
\i (00:03:09) zoom in 1.0573 -2.2538
\i (00:03:09) trapsize 4869
\i (00:03:09) zoom in 1
\i (00:03:09) setwindow pcb
\i (00:03:09) zoom in 1.0573 -2.2537
\i (00:03:09) trapsize 2435
\i (00:03:09) zoom in 1
\i (00:03:09) setwindow pcb
\i (00:03:09) zoom in 1.0573 -2.2537
\i (00:03:09) trapsize 1217
\i (00:03:09) zoom in 1
\i (00:03:09) setwindow pcb
\i (00:03:09) zoom in 1.0574 -2.2536
\i (00:03:09) trapsize 609
\i (00:03:10) zoom out 1
\i (00:03:10) setwindow pcb
\i (00:03:10) zoom out 1.0574 -2.2536
\i (00:03:10) trapsize 1217
\i (00:03:10) zoom out 1
\i (00:03:10) setwindow pcb
\i (00:03:10) zoom out 1.0574 -2.2535
\i (00:03:10) trapsize 2435
\i (00:03:10) zoom out 1
\i (00:03:10) setwindow pcb
\i (00:03:10) zoom out 1.0572 -2.2536
\i (00:03:10) trapsize 4869
\i (00:03:10) zoom out 1
\i (00:03:10) setwindow pcb
\i (00:03:10) zoom out 1.0573 -2.2535
\i (00:03:10) trapsize 9738
\i (00:03:11) zoom in 1
\i (00:03:11) setwindow pcb
\i (00:03:11) zoom in 3.0050 1.0575
\i (00:03:11) trapsize 4869
\i (00:03:11) zoom in 1
\i (00:03:11) setwindow pcb
\i (00:03:11) zoom in 3.0050 1.0575
\i (00:03:11) trapsize 2435
\i (00:03:13) label refdes
\t (00:03:13) Pick text location.
\i (00:03:13) pick grid -2.6432 12.5976
\t (00:03:13) last pick: -2.5400 12.7000
\t (00:03:13) Enter text string.
\i (00:03:16) setwindow form.mini
\i (00:03:16) FORM mini text_name asm
\i (00:03:19) setwindow pcb
\i (00:03:19) pick -2.5400 12.7000
\i (00:03:20) setwindow pcb
\i (00:03:20) MOVE
\t (00:03:20) Select element(s) to move.
\i (00:03:21) pick grid -1.5720 12.8897
\t (00:03:21) last pick: -2.5400 12.7000
\t (00:03:21) last pick: -2.5400 12.7000
\t (00:03:21) Pick new location for the element(s).
\i (00:03:22) pick grid 1.1061 8.7509
\t (00:03:22) last pick: 0.0000 7.6200
\i (00:03:24) label refdes
\t (00:03:24) Pick text location.
\i (00:03:26) setwindow form.mini
\i (00:03:26) FORM mini subclass SILKSCREEN_TOP
\i (00:03:26) setwindow pcb
\i (00:03:26) updateport CVPane
\i (00:03:27) setwindow form.mini
\i (00:03:27) FORM mini text_name ski
\i (00:03:28) setwindow pcb
\i (00:03:28) pick grid 3.3946 7.6310
\t (00:03:28) last pick: 2.5400 7.6200
\t (00:03:28) Enter text string.
\i (00:03:31) setwindow pcb
\i (00:03:31) pick 2.5400 7.6200
\i (00:03:32) prepopup 7.6308 7.8744
\i (00:03:33) done
\i (00:03:48) save
\t (00:03:49) Symbol 'pcb-10b.psm' created.
\i (00:03:55) shape add rect
\i (00:03:58) setwindow form.mini
\i (00:03:58) FORM mini subclass ASSEMBLY_TOP
\i (00:03:58) setwindow pcb
\i (00:03:58) updateport CVPane
\i (00:04:00) zoom in 1
\i (00:04:00) setwindow pcb
\i (00:04:00) zoom in -6.1491 5.2937
\i (00:04:00) trapsize 1217
\i (00:04:02) define grid
\t (00:04:02) Spacing fields allow simple equations to aid calculations; prefix with =
\i (00:04:03) setwindow form.grid
\i (00:04:03) FORM grid non_etch non_etch_x_grids 0.1
\i (00:04:03) FORM grid non_etch non_etch_y_grids 0.1
\i (00:04:04) FORM grid done
\i (00:04:05) setwindow pcb
\i (00:04:05) zoom in 1
\i (00:04:05) setwindow pcb
\i (00:04:05) zoom in -5.4187 4.8555
\i (00:04:05) trapsize 609
\i (00:04:07) pick grid -5.4673 5.0746
\t (00:04:07) last pick: -5.5000 5.1000
\i (00:04:08) zoom out 1
\i (00:04:08) setwindow pcb
\i (00:04:08) zoom out -4.2866 5.0016
\i (00:04:08) trapsize 1217
\i (00:04:12) pick grid 5.5493 -5.1021
\t (00:04:12) last pick: 5.5000 -5.1000
\i (00:04:12) prepopup 7.2779 -0.4763
\i (00:04:13) done
\i (00:04:13) save
\i (00:04:14) fillin yes
\t (00:04:14) Symbol 'pcb-10b.psm' created.
\i (00:04:15) exit
\t (00:04:15) Journal end - Sun Apr 27 22:51:38 2025
\t (00:00:02) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Sat May 10 13:21:47 2025
\t (00:00:02) Host=XEROLYSKINNER User=Xeroly Pid=45400 CPUs=16
\t (00:00:02) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\other\rj45-8p8c.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "rj45-8p8c"
\d (00:00:02) Design opened: D:/Workspace/GitHub/pcb_lib/other/rj45-8p8c.dra
\i (00:00:02) trapsize 2935
\i (00:00:02) trapsize 3019
\i (00:00:02) trapsize 2935
\i (00:00:02) trapsize 3259
\i (00:00:02) trapsize 3259
\i (00:00:02) trapsize 2106
\i (00:00:04) color192
\i (00:00:06) QtSignal CVDLayerContainer CVDVisibilityOff clicked
\i (00:00:07) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Bottom" 1
\i (00:00:07) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 3 0
\i (00:00:10) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 1
\i (00:00:10) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:11) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 0
\i (00:00:11) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:12) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Bottom" 0
\i (00:00:12) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 3 0
\i (00:00:13) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 1
\i (00:00:13) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:13) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 0
\i (00:00:13) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:14) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Bottom" 1
\i (00:00:14) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 3 0
\i (00:00:15) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 1
\i (00:00:15) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:16) QtSignal ColorVisibilityDialog CVDOkButton clicked
\i (00:00:17) color192
\i (00:00:19) QtSignal CVDLayerContainer CVDVisibilityOn clicked
\i (00:00:20) QtSignal ColorVisibilityDialog CVDOkButton clicked
\i (00:00:24) save
\i (00:00:24) fillin yes
\t (00:00:25) Symbol 'rj45-8p8c.psm' created.
\i (00:00:29) exit
\t (00:00:29) Journal end - Sat May 10 13:22:14 2025

4
other/batch_drc.log
View File

@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : B0505S_1WR3.dra )
( Drawing : rj45-8p8c.dra )
( Software Version : 23.1P001 )
( Date/Time : Tue Apr 22 23:31:49 2025 )
( Date/Time : Sat May 10 09:38:41 2025 )
( )
(---------------------------------------------------------------------)

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other/batch_drc.log,1 Normal file
View File

@@ -0,0 +1,27 @@
(---------------------------------------------------------------------)
( )
( DRC Update )
( )
( Drawing : B0505S_1WR3.dra )
( Software Version : 23.1P001 )
( Date/Time : Tue Apr 22 23:31:49 2025 )
( )
(---------------------------------------------------------------------)
========= check shapes 0:00:00
========= check standalone pins 0:00:00
========= check symbols (pins,lines,text) 0:00:00
========= check xnets 0:00:00
========= check nets 0:00:00
========= check standalone branches 0:00:00
========= check standalone filled rectangles 0:00:00
========= check standalone lines 0:00:00
========= check standalone text 0:00:00
========= check standalone rectangles 0:00:00
..... Total number of DRC errors 0
..... DRC update completed, total CPU time 0:00:00
*************************************************************************

4
other/downrev.log
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : PCB1094M4.dra )
( Drawing : rj45-8p8c.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 22:58:41 2025 )
( Date/Time : Sat May 10 13:22:10 2025 )
( )
(---------------------------------------------------------------------)

4
other/downrev.log,1
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : PCB1094M4.dra )
( Drawing : rj45-8p8c.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 22:58:38 2025 )
( Date/Time : Sat May 10 09:38:41 2025 )
( )
(---------------------------------------------------------------------)

4
other/downrev.log,2
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : PCB1094M4.dra )
( Drawing : rj45-8p8c.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 22:58:41 2025 )
( Date/Time : Sat May 10 13:22:10 2025 )
( )
(---------------------------------------------------------------------)

4
other/downrev.log,3
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : PCB1094M4.dra )
( Drawing : rj45-8p8c.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 22:58:41 2025 )
( Date/Time : Sat May 10 13:22:10 2025 )
( )
(---------------------------------------------------------------------)

2
other/master.tag
View File

@@ -1 +1 @@
PCB1094M4.dra
rj45-8p8c.dra

12
other/padstack_editor.jrl
View File

@@ -1,7 +1,9 @@
\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:00) Journal start - Sun Apr 27 22:51:05 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=28608 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\other\pcb-10b.pad
\t (00:00:00) Journal start - Sat May 10 13:14:47 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=47704 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\other\rj45-8p8c-4.pad
\t (00:00:00)
\d (00:00:03) QtSignal MainWindow Exit triggered
\t (00:00:03) Journal end - Sun Apr 27 22:51:08 2025
\d (00:00:01) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:02) QtSignal GuidedTabsParent GuidedTabs currentChanged "Drill Offset"
\d (00:00:05) QtSignal MainWindow Exit triggered
\t (00:00:05) Journal end - Sat May 10 13:14:52 2025

43
other/padstack_editor.jrl,1
View File

@@ -1,34 +1,9 @@
\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:00) Journal start - Sun Apr 27 22:48:26 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=1428 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\other\pcb-10b.pad
\t (00:00:00)
\d (00:00:02) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:19) QtSignal GuidedDesignLayersTab PadWidth editingFinished "10.0000"
\d (00:00:21) QtSignal GuidedDesignLayersTab PadOffsetX editingFinished "10.8000"
\d (00:00:23) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:26) QtSignal GuidedMaskLayersTab PadWidth editingFinished "10.0000"
\d (00:00:32) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:34) QtSignal GuidedTabsParent GuidedTabs currentChanged Start
\d (00:00:36) QtSignal GuidedTabsParent NewPads currentRowChanged 3
\d (00:00:36) QtSignal GuidedTabsParent NewPads itemSelectionChanged Rectangle
\d (00:00:36) QtSignal GuidedTabsParent NewPads itemClicked Rectangle
\d (00:00:37) QtFillin Yes
\d (00:00:38) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:41) QtSignal GuidedDesignLayersTab PadWidth editingFinished "10.0000"
\d (00:00:43) QtSignal GuidedDesignLayersTab PadHeight editingFinished "10.8000"
\d (00:00:44) QtSignal GuidedDesignLayersTab PadOffsetX editingFinished "0.0000"
\d (00:00:45) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:47) QtSignal GuidedMaskLayersTab PadWidth editingFinished "10.0000"
\d (00:00:50) QtSignal GuidedMaskLayersTab PadHeight editingFinished "10.8600"
\d (00:00:50) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
\d (00:00:52) QtSignal GuidedMaskLayersTab PadWidth editingFinished "10.0600"
\d (00:00:52) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
\d (00:00:53) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
\d (00:00:53) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 "Regular Pad" 2 1
\d (00:00:55) QtSignal GuidedMaskLayersTab PadWidth editingFinished "10.0000"
\d (00:00:57) QtSignal GuidedMaskLayersTab PadHeight editingFinished "10.8000"
\d (00:00:57) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:00) Journal start - Sat May 10 13:14:41 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=1216 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\other\rj45-8p8c-3.pad
\t (00:00:00)
\d (00:00:02) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:03) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:05) QtSignal MainWindow Exit triggered
\t (00:00:05) Journal end - Sat May 10 13:14:46 2025

6
other/param_read.log
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : PCB1094M4.dra )
( Drawing : USR-WIFI232-A2.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 22:55:50 2025 )
( Date/Time : Fri May 2 19:49:43 2025 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : PCB1094M4.dra
Layout Name : USR-WIFI232-A2.dra
Reading...parameter_header:
Reading...db_common_type:

8
other/param_read.log,1
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : fnwx_r1.dra )
( Drawing : WH-LTE-7S1.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 20:29:06 2025 )
( Date/Time : Sun Apr 27 20:57:13 2025 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : fnwx_r1.dra
Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : WH-LTE-7S1.dra
Reading...parameter_header:
Reading...db_common_type:

8
other/param_read.log,2
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : WH-LTE-7S1.dra )
( Drawing : pcb-10b.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 20:57:13 2025 )
( Date/Time : Sun Apr 27 22:49:58 2025 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : WH-LTE-7S1.dra
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : pcb-10b.dra
Reading...parameter_header:
Reading...db_common_type:

6
other/param_read.log,3
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : pcb-10b.dra )
( Drawing : PCB1094M4.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 22:49:58 2025 )
( Date/Time : Sun Apr 27 22:55:50 2025 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : pcb-10b.dra
Layout Name : PCB1094M4.dra
Reading...parameter_header:
Reading...db_common_type:

4
other/pcb1094m4.log
View File

@@ -4,13 +4,13 @@
( )
( Drawing : PCB1094M4.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 22:58:41 2025 )
( Date/Time : Fri May 2 01:53:20 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/other
Directory = D:/Workspace/GitHub/pcb_lib/other
Name = pcb1094m4.psm
User = Xeroly
Machine = XEROLYSKINNER

23
other/pcb1094m4.log,2 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : PCB1094M4.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 22:58:41 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/other
Name = pcb1094m4.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

BIN
other/pcb1094m4.psm
View File

Binary file not shown.

BIN
other/rj45-8p8c-1.pad
View File

Binary file not shown.

BIN
other/rj45-8p8c-2.pad
View File

Binary file not shown.

BIN
other/rj45-8p8c-3.pad
View File

Binary file not shown.

BIN
other/rj45-8p8c-4.pad
View File

Binary file not shown.

BIN
other/rj45-8p8c.dra
View File

Binary file not shown.

23
other/rj45-8p8c.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : rj45-8p8c.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 13:22:10 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/Workspace/GitHub/pcb_lib/other
Name = rj45-8p8c.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

23
other/rj45-8p8c.log,1 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : rj45-8p8c.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 06:04:54 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/Workspace/GitHub/pcb_lib/other
Name = rj45-8p8c.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

23
other/rj45-8p8c.log,2 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : rj45-8p8c.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 09:38:41 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/Workspace/GitHub/pcb_lib/other
Name = rj45-8p8c.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

BIN
other/rj45-8p8c.psm
View File

Binary file not shown.

5851
other/stepFacetFiles4Map/PCB-1094M4.xml Normal file
View File

File diff suppressed because it is too large Load Diff

3
other/stepFacetFiles4Map/stepFileInfo.txt
View File

@@ -4,12 +4,13 @@ XH2_54-W2P.step ! 183892 ! 1745749128
link_3.5_2x1.STEP ! 435783 ! 1723144412
TYPE-C.stp ! 1362496 ! 1710578258
KF7.62-2P.STEP ! 217264 ! 1722981445
EC11.STEP ! 1541194 ! 1712715932
rtl8189-board.STEP ! 1900144 ! 1712473643
EC11.STEP ! 1541194 ! 1712715932
link_3.5_2x5.STEP ! 467005 ! 1723144633
XH2_54-W3P.step ! 213594 ! 1745749034
KF7.62-3P.STEP ! 218099 ! 1722981496
rj45-8p8c.step ! 2080205 ! 1712409758
PCB-1094M4.STEP ! 66472 ! 1746121909
XH2_54-W5P.step ! 305916 ! 1745749057
link_3.5_2x4.STEP ! 466145 ! 1723146123
fpc0_5-40p.stp ! 9221743 ! 1584132940

4
other/stepFacetFiles4Map/stepFileInfo.txt,1
View File

@@ -4,8 +4,8 @@ XH2_54-W2P.step ! 183892 ! 1745749128
link_3.5_2x1.STEP ! 435783 ! 1723144412
TYPE-C.stp ! 1362496 ! 1710578258
KF7.62-2P.STEP ! 217264 ! 1722981445
rtl8189-board.STEP ! 1900144 ! 1712473643
EC11.STEP ! 1541194 ! 1712715932
rtl8189-board.STEP ! 1900144 ! 1712473643
link_3.5_2x5.STEP ! 467005 ! 1723144633
XH2_54-W3P.step ! 213594 ! 1745749034
KF7.62-3P.STEP ! 218099 ! 1722981496
@@ -15,6 +15,6 @@ link_3.5_2x4.STEP ! 466145 ! 1723146123
fpc0_5-40p.stp ! 9221743 ! 1584132940
fpc0_5-6p.stp ! 1966209 ! 1584132963
fpc0_5-50p.stp ! 11408226 ! 1584132947
B05051WR3.STEP ! 65139 ! 1745402887
B05051WR3.STEP ! 65128 ! 1745749519
wh-gm5.STEP ! 888098 ! 1712839932
oled-0_96.step ! 601137 ! 1712757601

23
other/usr-wifi232-a2.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : USR-WIFI232-A2.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri May 2 19:56:28 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/other
Name = usr-wifi232-a2.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

24
other/usr-wifi232-a2.log,1 Normal file
View File

@@ -0,0 +1,24 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : USR-WIFI232-A2.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri May 2 19:56:08 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/other
Name = usr-wifi232-a2.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
ERROR(SPMHCS-1): Symbol is missing a refdes.
ERROR(SPMHA1-291): Create symbol has been aborted.

BIN
other/usr-wifi232-a2.psm Normal file
View File

Binary file not shown.