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XerolySkinner
2025-09-27 11:01:31 +08:00
parent 7394f89550
commit b67fb10b08
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\t (00:02:25) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:02:25) Journal start - Sun Apr 27 22:49:48 2025
\t (00:02:25) Host=XEROLYSKINNER User=Xeroly Pid=17144 CPUs=16
\t (00:02:25) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe
\t (00:02:25)
\t (00:02:25) Starting new design...
\i (00:02:25) trapsize 14970
\i (00:02:25) trapsize 15291
\i (00:02:25) trapsize 14970
\t (00:02:25) Grids are drawn 1300.4800, 1300.4800 apart for enhanced viewing.
\i (00:02:25) trapsize 19763
\i (00:02:25) trapsize 19763
\i (00:02:26) trapsize 18903
\i (00:02:29) param in
\i (00:02:31) setwindow form.parm_in
\i (00:02:31) FORM parm_in browse
\i (00:02:34) fillin "D:/workspace/GitHub/pcb_lib/XerolySkinner.prm"
\i (00:02:34) FORM parm_in execute
\t (00:02:34) Starting Importing parameter file...
\w (00:02:35) WARNING(SPMHGE-269): param in had warnings, use Viewlog to review the log file.
\t (00:02:35) Opening existing design...
\t (00:02:35) Grids are drawn 2.5400, 2.5400 apart for enhanced viewing.
\i (00:02:35) setwindow pcb
\i (00:02:35) trapsize 18903
\i (00:02:35) trapsize 19289
\i (00:02:35) trapsize 18903
\t (00:02:35) Grids are drawn 2.5400, 2.5400 apart for enhanced viewing.
\i (00:02:35) trapsize 19477
\i (00:02:36) setwindow text
\i (00:02:36) close
\i (00:02:37) setwindow form.parm_in
\i (00:02:37) FORM parm_in cancel
\i (00:02:39) setwindow pcb
\i (00:02:39) prmed
\i (00:02:44) setwindow form.prmedit
\i (00:02:44) FORM prmedit design
\i (00:02:48) FORM prmedit done
\i (00:02:49) setwindow pcb
\i (00:02:49) label refdes
\t (00:02:49) Pick text location.
\i (00:02:51) add pin
\i (00:02:52) setwindow form.mini
\i (00:02:52) FORM mini pad_name pcb-10b
\t (00:02:52) Using 'PCB-10B.pad'.
\i (00:02:54) setwindow pcb
\i (00:02:54) pick 0 0
\t (00:02:54) last pick: 0.0000 0.0000
\t (00:02:54) Using 'PCB-10B.pad'.
\i (00:02:55) prepopup 14.4964 -20.1725
\i (00:02:55) done
\t (00:02:55) Exiting from Add Pin.
\i (00:02:56) zoom in 1
\i (00:02:56) setwindow pcb
\i (00:02:56) zoom in 1.2521 0.4730
\i (00:02:56) trapsize 9738
\i (00:02:56) zoom in 1
\i (00:02:56) setwindow pcb
\i (00:02:56) zoom in 1.2521 0.4730
\i (00:02:56) trapsize 4869
\i (00:02:56) zoom in 1
\i (00:02:56) setwindow pcb
\i (00:02:56) zoom in 1.2521 0.4730
\i (00:02:56) trapsize 2435
\i (00:02:58) undo
\i (00:02:58) trapsize 19477
\i (00:02:59) add pin
\i (00:03:01) setwindow form.mini
\i (00:03:01) FORM mini next_pin_number 1
\i (00:03:02) FORM mini pad_name pcb-10b
\t (00:03:02) Using 'PCB-10B.pad'.
\e (00:03:04) Command not found: x0 0
\i (00:03:06) setwindow pcb
\i (00:03:06) pick 0 0
\t (00:03:06) last pick: 0.0000 0.0000
\t (00:03:06) Using 'PCB-10B.pad'.
\i (00:03:07) prepopup 16.4441 11.7696
\i (00:03:08) done
\t (00:03:08) Exiting from Add Pin.
\i (00:03:08) zoom in 1
\i (00:03:08) setwindow pcb
\i (00:03:08) zoom in -2.6433 -4.2015
\i (00:03:08) trapsize 9738
\i (00:03:09) zoom in 1
\i (00:03:09) setwindow pcb
\i (00:03:09) zoom in 1.0573 -2.2538
\i (00:03:09) trapsize 4869
\i (00:03:09) zoom in 1
\i (00:03:09) setwindow pcb
\i (00:03:09) zoom in 1.0573 -2.2537
\i (00:03:09) trapsize 2435
\i (00:03:09) zoom in 1
\i (00:03:09) setwindow pcb
\i (00:03:09) zoom in 1.0573 -2.2537
\i (00:03:09) trapsize 1217
\i (00:03:09) zoom in 1
\i (00:03:09) setwindow pcb
\i (00:03:09) zoom in 1.0574 -2.2536
\i (00:03:09) trapsize 609
\i (00:03:10) zoom out 1
\i (00:03:10) setwindow pcb
\i (00:03:10) zoom out 1.0574 -2.2536
\i (00:03:10) trapsize 1217
\i (00:03:10) zoom out 1
\i (00:03:10) setwindow pcb
\i (00:03:10) zoom out 1.0574 -2.2535
\i (00:03:10) trapsize 2435
\i (00:03:10) zoom out 1
\i (00:03:10) setwindow pcb
\i (00:03:10) zoom out 1.0572 -2.2536
\i (00:03:10) trapsize 4869
\i (00:03:10) zoom out 1
\i (00:03:10) setwindow pcb
\i (00:03:10) zoom out 1.0573 -2.2535
\i (00:03:10) trapsize 9738
\i (00:03:11) zoom in 1
\i (00:03:11) setwindow pcb
\i (00:03:11) zoom in 3.0050 1.0575
\i (00:03:11) trapsize 4869
\i (00:03:11) zoom in 1
\i (00:03:11) setwindow pcb
\i (00:03:11) zoom in 3.0050 1.0575
\i (00:03:11) trapsize 2435
\i (00:03:13) label refdes
\t (00:03:13) Pick text location.
\i (00:03:13) pick grid -2.6432 12.5976
\t (00:03:13) last pick: -2.5400 12.7000
\t (00:03:13) Enter text string.
\i (00:03:16) setwindow form.mini
\i (00:03:16) FORM mini text_name asm
\i (00:03:19) setwindow pcb
\i (00:03:19) pick -2.5400 12.7000
\i (00:03:20) setwindow pcb
\i (00:03:20) MOVE
\t (00:03:20) Select element(s) to move.
\i (00:03:21) pick grid -1.5720 12.8897
\t (00:03:21) last pick: -2.5400 12.7000
\t (00:03:21) last pick: -2.5400 12.7000
\t (00:03:21) Pick new location for the element(s).
\i (00:03:22) pick grid 1.1061 8.7509
\t (00:03:22) last pick: 0.0000 7.6200
\i (00:03:24) label refdes
\t (00:03:24) Pick text location.
\i (00:03:26) setwindow form.mini
\i (00:03:26) FORM mini subclass SILKSCREEN_TOP
\i (00:03:26) setwindow pcb
\i (00:03:26) updateport CVPane
\i (00:03:27) setwindow form.mini
\i (00:03:27) FORM mini text_name ski
\i (00:03:28) setwindow pcb
\i (00:03:28) pick grid 3.3946 7.6310
\t (00:03:28) last pick: 2.5400 7.6200
\t (00:03:28) Enter text string.
\i (00:03:31) setwindow pcb
\i (00:03:31) pick 2.5400 7.6200
\i (00:03:32) prepopup 7.6308 7.8744
\i (00:03:33) done
\i (00:03:48) save
\t (00:03:49) Symbol 'pcb-10b.psm' created.
\i (00:03:55) shape add rect
\i (00:03:58) setwindow form.mini
\i (00:03:58) FORM mini subclass ASSEMBLY_TOP
\i (00:03:58) setwindow pcb
\i (00:03:58) updateport CVPane
\i (00:04:00) zoom in 1
\i (00:04:00) setwindow pcb
\i (00:04:00) zoom in -6.1491 5.2937
\i (00:04:00) trapsize 1217
\i (00:04:02) define grid
\t (00:04:02) Spacing fields allow simple equations to aid calculations; prefix with =
\i (00:04:03) setwindow form.grid
\i (00:04:03) FORM grid non_etch non_etch_x_grids 0.1
\i (00:04:03) FORM grid non_etch non_etch_y_grids 0.1
\i (00:04:04) FORM grid done
\i (00:04:05) setwindow pcb
\i (00:04:05) zoom in 1
\i (00:04:05) setwindow pcb
\i (00:04:05) zoom in -5.4187 4.8555
\i (00:04:05) trapsize 609
\i (00:04:07) pick grid -5.4673 5.0746
\t (00:04:07) last pick: -5.5000 5.1000
\i (00:04:08) zoom out 1
\i (00:04:08) setwindow pcb
\i (00:04:08) zoom out -4.2866 5.0016
\i (00:04:08) trapsize 1217
\i (00:04:12) pick grid 5.5493 -5.1021
\t (00:04:12) last pick: 5.5000 -5.1000
\i (00:04:12) prepopup 7.2779 -0.4763
\i (00:04:13) done
\i (00:04:13) save
\i (00:04:14) fillin yes
\t (00:04:14) Symbol 'pcb-10b.psm' created.
\i (00:04:15) exit
\t (00:04:15) Journal end - Sun Apr 27 22:51:38 2025
\t (00:00:02) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Sat May 10 13:21:47 2025
\t (00:00:02) Host=XEROLYSKINNER User=Xeroly Pid=45400 CPUs=16
\t (00:00:02) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\other\rj45-8p8c.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "rj45-8p8c"
\d (00:00:02) Design opened: D:/Workspace/GitHub/pcb_lib/other/rj45-8p8c.dra
\i (00:00:02) trapsize 2935
\i (00:00:02) trapsize 3019
\i (00:00:02) trapsize 2935
\i (00:00:02) trapsize 3259
\i (00:00:02) trapsize 3259
\i (00:00:02) trapsize 2106
\i (00:00:04) color192
\i (00:00:06) QtSignal CVDLayerContainer CVDVisibilityOff clicked
\i (00:00:07) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Bottom" 1
\i (00:00:07) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 3 0
\i (00:00:10) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 1
\i (00:00:10) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:11) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 0
\i (00:00:11) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:12) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Bottom" 0
\i (00:00:12) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 3 0
\i (00:00:13) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 1
\i (00:00:13) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:13) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 0
\i (00:00:13) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:14) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Bottom" 1
\i (00:00:14) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 3 0
\i (00:00:15) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 1
\i (00:00:15) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:16) QtSignal ColorVisibilityDialog CVDOkButton clicked
\i (00:00:17) color192
\i (00:00:19) QtSignal CVDLayerContainer CVDVisibilityOn clicked
\i (00:00:20) QtSignal ColorVisibilityDialog CVDOkButton clicked
\i (00:00:24) save
\i (00:00:24) fillin yes
\t (00:00:25) Symbol 'rj45-8p8c.psm' created.
\i (00:00:29) exit
\t (00:00:29) Journal end - Sat May 10 13:22:14 2025