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XerolySkinner
2025-09-27 11:01:31 +08:00
parent 7394f89550
commit b67fb10b08
109 changed files with 42752 additions and 1562 deletions
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3D/PC817.STEP Normal file
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ISO-10303-21;
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BIN
basic_lib/BASIC_OBJ.OLB
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BIN
basic_lib/BASIC_OBJ_0.OBK
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57
chip/allegro.jrl
View File

@@ -1,45 +1,20 @@
\t (00:00:02) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Fri Apr 25 15:00:50 2025
\t (00:00:02) Host=XEROLYSKINNER User=Xeroly Pid=5220 CPUs=16
\t (00:00:02) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\chip\tqfp-48-ep.dra
\t (00:00:02) Journal start - Sat May 10 04:57:54 2025
\t (00:00:02) Host=XEROLYSKINNER User=Xeroly Pid=35792 CPUs=16
\t (00:00:02) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "tqfp-48-ep"
\d (00:00:04) Design opened: D:/Workspace/GitHub/pcb_lib/chip/tqfp-48-ep.dra
\t (00:00:05) Grids are drawn 0.160, 0.160 apart for enhanced viewing.
\i (00:00:05) trapsize 102
\i (00:00:05) trapsize 104
\i (00:00:05) trapsize 102
\t (00:00:05) Grids are drawn 0.160, 0.160 apart for enhanced viewing.
\i (00:00:05) trapsize 108
\t (00:00:05) Opening existing design...
\i (00:00:05) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "wsoic-8"
\d (00:00:05) Design opened: D:/workspace/GitHub/pcb_lib/chip/wsoic-8.dra
\t (00:00:05) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
\i (00:00:05) trapsize 74
\i (00:00:12) add pin
\i (00:00:16) setwindow form.mini
\i (00:00:16) FORM mini pad_name tqfp-48-ep-gnd
\w (00:00:16) WARNING(SPMHUT-48): Scaled value has been rounded off.
\t (00:00:16) Using 'TQFP-48-EP-GND.pad'.
\e (00:00:20) Command not found: X 0 0
\i (00:00:22) setwindow pcb
\i (00:00:22) pick 0 0
\t (00:00:22) last pick: 0.000 0.000
\t (00:00:22) Using 'TQFP-48-EP-GND.pad'.
\i (00:00:23) prepopup 6.355 6.505
\i (00:00:27) oops
\t (00:00:27) Using 'TQFP-48-EP-GND.pad'.
\i (00:00:32) setwindow form.mini
\i (00:00:32) FORM mini text_name pin
\i (00:00:34) FORM mini next_pin_number 49
\i (00:00:36) setwindow pcb
\i (00:00:36) pick 0 0
\t (00:00:36) last pick: 0.000 0.000
\t (00:00:36) Using 'TQFP-48-EP-GND.pad'.
\i (00:00:37) prepopup 7.902 3.812
\i (00:00:38) done
\t (00:00:38) Exiting from Add Pin.
\i (00:00:39) save
\i (00:00:40) fillin yes
\t (00:00:40) Symbol 'tqfp-48-ep.psm' created.
\i (00:00:41) exit
\t (00:00:41) Journal end - Fri Apr 25 15:01:29 2025
\i (00:00:05) trapsize 71
\i (00:00:05) trapsize 73
\i (00:00:06) trapsize 71
\i (00:00:06) trapsize 76
\t (00:00:06) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
\i (00:00:06) trapsize 79
\i (00:00:06) trapsize 53
\i (00:00:20) new
\i (00:00:37) newdrawfillin "smd_4.dra" "Package Symbol (Wizard)"
\t (00:00:37) Journal end - Sat May 10 04:58:28 2025

1408
chip/allegro.jrl,1
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File diff suppressed because it is too large Load Diff

4
chip/batch_drc.log
View File

@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : tqfp-48-ep.dra )
( Drawing : sym_template.dra )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:37:19 2025 )
( Date/Time : Sat May 10 04:32:11 2025 )
( )
(---------------------------------------------------------------------)

4
chip/batch_drc.log,1
View File

@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : sym_template.dra )
( Drawing : tqfp-48-ep.dra )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:20:55 2025 )
( Date/Time : Thu Apr 24 23:35:37 2025 )
( )
(---------------------------------------------------------------------)

4
chip/batch_drc.log,2
View File

@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : sym_template.dra )
( Drawing : tqfp-48-ep.dra )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:20:56 2025 )
( Date/Time : Thu Apr 24 23:37:19 2025 )
( )
(---------------------------------------------------------------------)

4
chip/batch_drc.log,3
View File

@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : tqfp-48-ep.dra )
( Drawing : sym_template.dra )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:35:37 2025 )
( Date/Time : Sat May 10 04:32:11 2025 )
( )
(---------------------------------------------------------------------)

29
chip/dangling_lines.rpt Normal file
View File

@@ -0,0 +1,29 @@
(---------------------------------------------------------------------)
( )
( Dangling Line, Via and Antenna Report )
( )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 04:34:41 2025 )
( )
(---------------------------------------------------------------------)
Report methodology:
- Dangling lines have at least one end not connected.
- Dangling vias have one or no connection
- Plus are not a test, thieving or netshort property via.
- Antenna vias do not have connections on their start and end layers.
- Plus they are not a thieving vias.
- Optionally, VOLTAGE nets, testvias and through vias can be suppressed with
the environment variable report_antennavia.
- Section may be suppressed by variable report_noantennavia.
- Not part of the current partition.
- To suppress items in dangle report add the OK_DANGLE property to the via
or connect line.
<< Summary >>
Total dangling lines: 0
Total dangling vias: 0
Total antenna vias: 0

4
chip/downrev.log
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : tqfp-48-ep.dra )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri Apr 25 15:01:28 2025 )
( Date/Time : Sat May 10 04:45:31 2025 )
( )
(---------------------------------------------------------------------)

4
chip/downrev.log,1
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : tqfp-48-ep-gnd.pad )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri Apr 25 15:00:42 2025 )
( Date/Time : Sat May 10 04:45:17 2025 )
( )
(---------------------------------------------------------------------)

4
chip/downrev.log,2
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : tqfp-48-ep.dra )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri Apr 25 15:01:28 2025 )
( Date/Time : Sat May 10 04:45:31 2025 )
( )
(---------------------------------------------------------------------)

4
chip/downrev.log,3
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : tqfp-48-ep.dra )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri Apr 25 15:01:28 2025 )
( Date/Time : Sat May 10 04:45:31 2025 )
( )
(---------------------------------------------------------------------)

2
chip/master.tag
View File

@@ -1 +1 @@
tqfp-48-ep.dra
wsoic-8.dra

27
chip/padstack_editor.jrl
View File

@@ -1,24 +1,7 @@
\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:00) Journal start - Fri Apr 25 15:00:00 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=24896 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\chip\tqfp-48-ep-gnd.pad
\t (00:00:00) Journal start - Sat May 10 04:28:20 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=37520 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\chip\wsoic-8.pad
\t (00:00:00)
\d (00:00:02) QtSignal GuidedTabsParent NewPads currentRowChanged 1
\d (00:00:02) QtSignal GuidedTabsParent NewPads itemSelectionChanged Square
\d (00:00:02) QtSignal GuidedTabsParent NewPads itemClicked Square
\d (00:00:03) QtFillin Yes
\d (00:00:05) QtSignal GuidedTabsParent GuidedStartTab keyPressEvent 16777251 134217728 false 1
\d (00:00:07) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:08) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
\d (00:00:08) QtSignal 1
\d (00:00:22) QtSignal GuidedDesignLayersTab PadWidth editingFinished "5.0000"
\d (00:00:26) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:27) QtSignal GuidedMaskLayersTab LayersTable cellClicked 0 "Regular Pad" 0 1
\d (00:00:29) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0000"
\d (00:00:36) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0600"
\d (00:00:37) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
\d (00:00:37) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 "Regular Pad" 2 1
\d (00:00:40) QtSignal GuidedMaskLayersTab PadWidth editingFinished "5.0000"
\d (00:00:42) QtSignal MainWindow Save triggered
\d (00:00:43) QtSignal MainWindow Exit triggered
\t (00:00:43) Journal end - Fri Apr 25 15:00:44 2025
\d (00:00:05) QtSignal MainWindow Exit triggered
\t (00:00:05) Journal end - Sat May 10 04:28:26 2025

41
chip/padstack_editor.jrl,1
View File

@@ -1,21 +1,24 @@
\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:00) Journal start - Thu Apr 24 23:36:01 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=13068 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\chip\tqfp-48-ep.pad
\t (00:00:00) Journal start - Fri Apr 25 15:00:00 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=24896 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\chip\tqfp-48-ep-gnd.pad
\t (00:00:00)
\d (00:00:03) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:11) QtSignal GuidedDesignLayersTab PadHeight editingFinished "0.2600"
\d (00:00:11) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777220 0 false 1 "
"
\d (00:00:13) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:14) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:18) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:28) QtSignal GuidedMaskLayersTab PadHeight editingFinished "0.2800"
\d (00:00:28) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
\d (00:00:30) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
\d (00:00:32) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 "Regular Pad" 2 1
\d (00:00:33) QtSignal GuidedMaskLayersTab PadHeight editingFinished "0.2600"
\d (00:00:33) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
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\d (00:00:36) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
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\d (00:00:05) QtSignal GuidedTabsParent GuidedStartTab keyPressEvent 16777251 134217728 false 1
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\d (00:00:08) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
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\d (00:00:42) QtSignal MainWindow Save triggered
\d (00:00:43) QtSignal MainWindow Exit triggered
\t (00:00:43) Journal end - Fri Apr 25 15:00:44 2025

8
chip/param_read.log
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : tqfp-48-ep.dra )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Thu Apr 24 23:38:15 2025 )
( Date/Time : Sat May 10 04:32:23 2025 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/Workspace/GitHub/pcb_lib/chip/tqfp-48-ep.dra
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/workspace/GitHub/pcb_lib/chip/wsoic-8.dra
Reading...parameter_header:
Reading...db_common_type:

6
chip/param_read.log,1
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : ssop-4.dra )
( Drawing : htssop-56.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 22:01:23 2024 )
( Date/Time : Wed Aug 7 01:10:16 2024 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/workspace/GitHub/pcb_lib/chip/ssop-4.dra
Layout Name : D:/workspace/GitHub/pcb_lib/chip/htssop-56.dra
Reading...parameter_header:
Reading...db_common_type:

10
chip/param_read.log,2
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : htssop-56.dra )
( Software Version : 17.4S035 )
( Date/Time : Wed Aug 7 01:10:16 2024 )
( Drawing : wsop-16.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:01:05 2025 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/workspace/GitHub/pcb_lib/chip/htssop-56.dra
Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/Workspace/GitHub/pcb_lib/chip/wsop-16.dra
Reading...parameter_header:
Reading...db_common_type:

6
chip/param_read.log,3
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : wsop-16.dra )
( Drawing : tqfp-48-ep.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:01:05 2025 )
( Date/Time : Thu Apr 24 23:38:15 2025 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/Workspace/GitHub/pcb_lib/chip/wsop-16.dra
Layout Name : D:/Workspace/GitHub/pcb_lib/chip/tqfp-48-ep.dra
Reading...parameter_header:
Reading...db_common_type:

1
chip/stepFacetFiles4Map/stepFileInfo.txt
View File

@@ -9,6 +9,7 @@ wsop_16.step ! 827104 ! 1745399292
ssop-16.step ! 873879 ! 1745399033
tqfp-48.STEP ! 166679 ! 1745422272
D8-L.step ! 282667 ! 1568096060
wsop-16.step ! 584105 ! 1746823035
SOP-16.STEP ! 3778717 ! 1722501952
DIP_2x5.step ! 720870 ! 1710578258
SSOP-8.step ! 755497 ! 1712718221

1
chip/stepFacetFiles4Map/stepFileInfo.txt,1
View File

@@ -9,6 +9,7 @@ wsop_16.step ! 827104 ! 1745399292
ssop-16.step ! 873879 ! 1745399033
tqfp-48.STEP ! 166679 ! 1745422272
D8-L.step ! 282667 ! 1568096060
wsop-16.step ! 584105 ! 1746823035
SOP-16.STEP ! 3778717 ! 1722501952
DIP_2x5.step ! 720870 ! 1710578258
SSOP-8.step ! 755497 ! 1712718221

17160
chip/stepFacetFiles4Map/wsop-16.xml Normal file
View File

File diff suppressed because it is too large Load Diff

BIN
chip/wsoic-8.dra Normal file
View File

Binary file not shown.

14
machine/m3x0_5.log,1 → chip/wsoic-8.log
View File

@@ -2,18 +2,18 @@
( )
( CREATE SYMBOL )
( )
( Drawing : m3x0_5.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 05:25:21 2024 )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 04:45:31 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/¹¤×÷¿â/GitHub/pcb_lib/machine
Name = m3x0_5.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = wsoic-8.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.

14
machine/m3x0_5.log,2 → chip/wsoic-8.log,1
View File

@@ -2,18 +2,18 @@
( )
( CREATE SYMBOL )
( )
( Drawing : m3x0_5.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 06:03:48 2024 )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 04:34:55 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/¹¤×÷¿â/GitHub/pcb_lib/machine
Name = m3x0_5.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = wsoic-8.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.

14
machine/m3x0_5.log,3 → chip/wsoic-8.log,2
View File

@@ -2,18 +2,18 @@
( )
( CREATE SYMBOL )
( )
( Drawing : m3x0_5.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 06:19:52 2024 )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 04:35:43 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/machine
Name = m3x0_5.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = wsoic-8.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.

23
chip/wsoic-8.log,3 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : wsoic-8.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 04:45:17 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = wsoic-8.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

BIN
chip/wsoic-8.pad Normal file
View File

Binary file not shown.

BIN
chip/wsoic-8.psm Normal file
View File

Binary file not shown.

BIN
chip/wsop-16.dra
View File

Binary file not shown.

2
chip/wsop-16.log
View File

@@ -4,7 +4,7 @@
( )
( Drawing : wsop-16.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:37:56 2025 )
( Date/Time : Sat May 3 00:59:54 2025 )
( )
(---------------------------------------------------------------------)

2
chip/wsop-16.log,1
View File

@@ -4,7 +4,7 @@
( )
( Drawing : wsop-16.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:18:34 2025 )
( Date/Time : Wed Apr 23 17:18:43 2025 )
( )
(---------------------------------------------------------------------)

2
chip/wsop-16.log,2
View File

@@ -4,7 +4,7 @@
( )
( Drawing : wsop-16.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:18:43 2025 )
( Date/Time : Wed Apr 23 17:37:39 2025 )
( )
(---------------------------------------------------------------------)

2
chip/wsop-16.log,3
View File

@@ -4,7 +4,7 @@
( )
( Drawing : wsop-16.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 17:37:39 2025 )
( Date/Time : Wed Apr 23 17:37:56 2025 )
( )
(---------------------------------------------------------------------)

BIN
chip/wsop-16.psm
View File

Binary file not shown.

57
machine/allegro.jrl
View File

@@ -1,29 +1,28 @@
\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:03) Journal start - Fri Aug 2 06:23:15 2024
\t (00:00:03) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=25644 CPUs=12
\t (00:00:03) CmdLine= D:\SOFTWARE\Cadence\SPB_17.4\tools\bin\allegro.exe
\t (00:00:03)
(00:00:03) Loading axlcore.cxt
\t (00:00:05) Opening existing design...
\i (00:00:05) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "m3x0_5"
\d (00:00:05) Design opened: D:/workspace/GitHub/pcb_lib/machine/m3x0_5.dra
\i (00:00:06) trapsize 671
\i (00:00:06) trapsize 688
\i (00:00:06) trapsize 671
\i (00:00:06) trapsize 588
\i (00:00:06) trapsize 604
\i (00:00:06) trapsize 621
\i (00:00:06) trapsize 638
\i (00:00:15) open
\i (00:00:25) fillin "D:/workspace/Cadence/cardrive/allegro/cardrive.brd"
\i (00:00:25) cd "D:/workspace/Cadence/cardrive/allegro"
\t (00:00:26) Opening existing design...
\t (00:00:26) Grids are drawn 0.8000, 0.8000 apart for enhanced viewing.
\i (00:00:26) trapsize 5428
\i (00:00:26) trapsize 5562
\t (00:00:26) Grids are drawn 409.6000, 409.6000 apart for enhanced viewing.
\t (00:00:26) Grids are drawn 0.8000, 0.8000 apart for enhanced viewing.
\i (00:00:26) trapsize 6033
\i (00:00:26) trapsize 6033
\t (00:00:26) > Sending response DoneOpenBoard
\t (00:00:26) Journal end - Fri Aug 2 06:23:39 2024
\t (00:00:02) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Sat May 10 12:52:41 2025
\t (00:00:02) Host=XEROLYSKINNER User=Xeroly Pid=35720 CPUs=16
\t (00:00:02) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\machine\m3x0_5.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "m3x0_5"
\d (00:00:02) Design opened: D:/Workspace/GitHub/pcb_lib/machine/m3x0_5.dra
\i (00:00:02) trapsize 722
\i (00:00:02) trapsize 743
\i (00:00:02) trapsize 722
\i (00:00:02) trapsize 769
\i (00:00:02) trapsize 816
\i (00:00:02) trapsize 550
\i (00:00:10) step pkg map
\i (00:00:11) fillin yes
\i (00:01:51) setwindow form.pkgmap3d
\i (00:01:51) FORM pkgmap3d offset_z 10.0000
\i (00:01:55) FORM pkgmap3d offset_z 5.0000
\i (00:02:00) FORM pkgmap3d save_current
\i (00:02:02) FORM pkgmap3d done
\i (00:02:03) setwindow pcb
\i (00:02:03) exit
\e (00:02:03) Do you want to save the changes you made to m3x0_5.dra?
\i (00:02:03) fillin yes
\t (00:02:04) Symbol 'm3x0_5.psm' created.
\t (00:02:04) Journal end - Sat May 10 12:54:43 2025

44
machine/allegro.jrl,1
View File

@@ -1,44 +0,0 @@
\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:03) Journal start - Fri Aug 2 06:19:47 2024
\t (00:00:03) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=24944 CPUs=12
\t (00:00:03) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\machine\m3x0_5.dra
\t (00:00:03)
(00:00:03) Loading axlcore.cxt
\t (00:00:05) Opening existing design...
\i (00:00:06) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "m3x0_5"
\d (00:00:06) Design opened: D:/workspace/GitHub/pcb_lib/machine/m3x0_5.dra
\i (00:00:06) trapsize 653
\i (00:00:06) trapsize 671
\i (00:00:06) trapsize 653
\i (00:00:06) trapsize 573
\i (00:00:06) trapsize 589
\i (00:00:06) trapsize 605
\i (00:00:06) trapsize 621
\i (00:00:07) save
\i (00:00:08) fillin yes
\t (00:00:08) Symbol 'm3x0_5.psm' created.
\i (00:00:10) step pkg map
\i (00:00:11) fillin yes
\i (00:00:16) setwindow form.pkgmap3d
\i (00:00:16) FORM pkgmap3d stplist M3x18.STEP
\i (00:02:49) setwindow pcb
\i (00:02:49) step pkg map
\i (00:02:53) fillin no
\i (00:02:57) setwindow form.pkgmap3d
\i (00:02:57) FORM pkgmap3d rotation_y 90
\i (00:02:59) FORM pkgmap3d rotation_y 0
\i (00:03:00) FORM pkgmap3d rotation_x 90
\i (00:03:02) FORM pkgmap3d hide_board YES
\i (00:03:06) FORM pkgmap3d view_orientation Top
\i (00:03:08) FORM pkgmap3d view_orientation Left
\i (00:03:12) FORM pkgmap3d offset_z 10
\i (00:03:14) FORM pkgmap3d offset_z 20
\i (00:03:17) FORM pkgmap3d offset_z 15
\i (00:03:21) FORM pkgmap3d save_current
\i (00:03:22) FORM pkgmap3d done
\i (00:03:23) setwindow pcb
\i (00:03:23) save
\i (00:03:24) fillin yes
\t (00:03:24) Symbol 'm3x0_5.psm' created.
\i (00:03:25) exit
\t (00:03:25) Journal end - Fri Aug 2 06:23:09 2024

4
machine/downrev.log
View File

@@ -3,8 +3,8 @@
( Downrev Design )
( )
( Drawing : m3x0_5.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 06:23:08 2024 )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 12:54:43 2025 )
( )
(---------------------------------------------------------------------)

4
machine/downrev.log,1
View File

@@ -3,8 +3,8 @@
( Downrev Design )
( )
( Drawing : m3x0_5.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 06:19:52 2024 )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 12:54:43 2025 )
( )
(---------------------------------------------------------------------)

4
machine/downrev.log,2
View File

@@ -3,8 +3,8 @@
( Downrev Design )
( )
( Drawing : m3x0_5.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 06:23:08 2024 )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 12:54:43 2025 )
( )
(---------------------------------------------------------------------)

14
machine/downrev.log,3
View File

@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : m3x0_5.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 06:23:08 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

BIN
machine/m3x0_5.dra
View File

Binary file not shown.

10
machine/m3x0_5.log
View File

@@ -3,17 +3,17 @@
( CREATE SYMBOL )
( )
( Drawing : m3x0_5.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 06:23:08 2024 )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 12:54:43 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/machine
Directory = D:/Workspace/GitHub/pcb_lib/machine
Name = m3x0_5.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.

BIN
machine/m3x0_5.psm
View File

Binary file not shown.

2
machine/stepFacetFiles4Map/stepFileInfo.txt
View File

@@ -1,6 +1,6 @@
#STEP_FILE ! FILE_SIZE ! MOD_TIME
P8.step ! 229628 ! 1568096060
M3x18.STEP ! 717806 ! 1722547502
M3x18.STEP ! 717806 ! 1724688650
M3x8.step ! 440671 ! 1722533353
LED_0603_G.STEP ! 178570 ! 1710578258

BIN
other/PCB1094M4.dra
View File

Binary file not shown.

BIN
other/USR-WIFI232-A2.dra Normal file
View File

Binary file not shown.

162
other/allegro.jrl
View File

@@ -1,133 +1,29 @@
\t (00:02:32) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:02:32) Journal start - Sun Apr 27 22:55:41 2025
\t (00:02:32) Host=XEROLYSKINNER User=Xeroly Pid=2016 CPUs=16
\t (00:02:32) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe -mpssession Xeroly -proj d:\workspace\cadence\cedarmotor\cedarmotor.opj d:/workspace/cadence/cedarmotor/allegro/cedarmotor.brd
\t (00:02:32)
\t (00:02:32) Starting new design...
\i (00:02:32) trapsize 14970
\i (00:02:32) trapsize 15291
\i (00:02:32) trapsize 14970
\t (00:02:32) Grids are drawn 1300.4800, 1300.4800 apart for enhanced viewing.
\i (00:02:32) trapsize 19763
\i (00:02:32) trapsize 19763
\i (00:02:32) trapsize 18903
\i (00:02:35) param in
\i (00:02:37) setwindow form.parm_in
\i (00:02:37) FORM parm_in browse
\i (00:02:39) fillin "D:/workspace/GitHub/pcb_lib/XerolySkinner.prm"
\i (00:02:40) FORM parm_in execute
\t (00:02:40) Starting Importing parameter file...
\w (00:02:40) WARNING(SPMHGE-269): param in had warnings, use Viewlog to review the log file.
\t (00:02:40) Opening existing design...
\t (00:02:40) Grids are drawn 2.5400, 2.5400 apart for enhanced viewing.
\i (00:02:40) setwindow pcb
\i (00:02:40) trapsize 18903
\i (00:02:40) trapsize 19289
\i (00:02:41) trapsize 18903
\t (00:02:41) Grids are drawn 2.5400, 2.5400 apart for enhanced viewing.
\i (00:02:41) trapsize 19477
\i (00:02:42) setwindow text
\i (00:02:42) close
\i (00:02:43) setwindow form.parm_in
\i (00:02:43) FORM parm_in cancel
\i (00:02:44) setwindow pcb
\i (00:02:44) zoom in 1
\i (00:02:44) setwindow pcb
\i (00:02:44) zoom in -9.2655 -6.9282
\t (00:02:44) Grids are drawn 1.2700, 1.2700 apart for enhanced viewing.
\i (00:02:44) trapsize 9738
\i (00:02:45) zoom in 1
\i (00:02:45) setwindow pcb
\i (00:02:45) zoom in 1.4468 -0.6956
\i (00:02:45) trapsize 4869
\i (00:02:47) add pin
\i (00:02:49) setwindow form.mini
\i (00:02:49) FORM mini x_count 2
\i (00:02:55) FORM mini x_spacing 6.9000
\i (00:02:59) FORM mini next_pin_number 1
\i (00:02:59) FORM mini pad_browse
\i (00:03:21) fillin "Thr-2r3-3r0"
\t (00:03:21) Using 'THR-2R3-3R0.pad'.
\e (00:03:39) Command not found: X -3.45 0
\i (00:03:46) setwindow pcb
\i (00:03:46) pick -3.45 0
\t (00:03:46) last pick: -3.4500 0.0000
\t (00:03:46) Using 'THR-2R3-3R0.pad'.
\i (00:03:48) prepopup -1.6694 6.2187
\i (00:03:48) done
\t (00:03:48) Exiting from Add Pin.
\i (00:03:49) zoom in 1
\i (00:03:49) setwindow pcb
\i (00:03:49) zoom in -1.0851 1.2521
\i (00:03:49) trapsize 2435
\i (00:03:49) zoom in 1
\i (00:03:49) setwindow pcb
\i (00:03:49) zoom in -1.0851 1.2522
\i (00:03:49) trapsize 1217
\i (00:04:00) shape add rect
\i (00:04:02) setwindow form.mini
\i (00:04:02) FORM mini class 'PACKAGE GEOMETRY'
\i (00:04:04) FORM mini subclass PLACE_BOUND_TOP
\i (00:04:04) setwindow pcb
\i (00:04:04) updateport CVPane
\i (00:04:21) pick -3.95 3.95
\t (00:04:21) last pick: -3.9500 3.9500
\i (00:04:26) pick 3.95 -3.95
\t (00:04:26) last pick: 3.9500 -3.9500
\i (00:04:27) prepopup -2.4485 7.5335
\i (00:04:28) done
\i (00:04:29) add rect
\i (00:04:31) setwindow form.mini
\i (00:04:31) FORM mini subclass ASSEMBLY_TOP
\i (00:04:31) setwindow pcb
\i (00:04:31) updateport CVPane
\i (00:04:35) pick -3.95 3.95
\t (00:04:35) last pick: -3.9500 3.9500
\i (00:04:39) pick 3.95 -3.95
\t (00:04:39) last pick: 3.9500 -3.9500
\i (00:04:40) prepopup 8.8968 5.0989
\i (00:04:41) done
\i (00:04:48) add rect
\i (00:04:51) shape add rect
\i (00:04:54) setwindow form.mini
\i (00:04:54) FORM mini subclass SILKSCREEN_TOP
\i (00:04:54) setwindow pcb
\i (00:04:54) updateport CVPane
\i (00:05:00) pick -3.95 3.95
\t (00:05:00) last pick: -3.9500 3.9500
\i (00:05:05) pick 3.95 -3.95
\t (00:05:05) last pick: 3.9500 -3.9500
\i (00:05:06) prepopup 6.1214 5.3423
\i (00:05:07) done
\i (00:05:08) label refdes
\t (00:05:08) Pick text location.
\i (00:05:11) setwindow form.mini
\i (00:05:11) FORM mini text_name asm
\i (00:05:11) setwindow pcb
\i (00:05:11) pick grid -0.2573 6.1457
\t (00:05:11) last pick: 0.0000 5.0800
\t (00:05:11) Enter text string.
\i (00:05:14) setwindow pcb
\i (00:05:14) pick 0.0000 5.0800
\i (00:05:19) pick grid -2.5945 4.7337
\t (00:05:19) last pick: -2.5400 5.0800
\t (00:05:19) Refdes of this subclass is already defined, change subclass.
\i (00:05:23) setwindow form.mini
\i (00:05:23) FORM mini subclass SILKSCREEN_TOP
\i (00:05:23) setwindow pcb
\i (00:05:23) updateport CVPane
\i (00:05:25) setwindow form.mini
\i (00:05:25) FORM mini text_name ski
\i (00:05:26) setwindow pcb
\i (00:05:26) pick grid -2.7406 4.9528
\t (00:05:26) last pick: -2.5400 5.0800
\t (00:05:26) Enter text string.
\i (00:05:28) setwindow pcb
\i (00:05:28) pick -2.5400 5.0800
\i (00:05:29) save
\t (00:05:29) Symbol 'pcb1094m4.psm' created.
\i (00:05:31) save
\i (00:05:31) fillin yes
\t (00:05:32) Symbol 'pcb1094m4.psm' created.
\i (00:05:33) exit
\t (00:05:33) Journal end - Sun Apr 27 22:58:42 2025
\t (00:00:02) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Sat May 10 13:22:20 2025
\t (00:00:02) Host=XEROLYSKINNER User=Xeroly Pid=20404 CPUs=16
\t (00:00:02) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "rj45-8p8c"
\d (00:00:04) Design opened: D:/Workspace/GitHub/pcb_lib/other/rj45-8p8c.dra
\i (00:00:04) trapsize 2935
\i (00:00:05) trapsize 3019
\i (00:00:05) trapsize 2935
\i (00:00:05) trapsize 3259
\i (00:00:05) trapsize 3259
\i (00:00:05) trapsize 2106
\i (00:00:08) open
\i (00:00:17) fillin "D:/Workspace/Cadence/cedarmain/allegro/cedarmain.brd"
\i (00:00:17) cd "D:/Workspace/Cadence/cedarmain/allegro"
\t (00:00:17) Opening existing design...
\t (00:00:18) Grids are drawn 0.0800, 0.0800 apart for enhanced viewing.
\i (00:00:18) trapsize 951
\i (00:00:18) trapsize 971
\t (00:00:18) Grids are drawn 0.0800, 0.0800 apart for enhanced viewing.
\i (00:00:18) trapsize 988
\t (00:00:18) Grids are drawn 0.1600, 0.1600 apart for enhanced viewing.
\i (00:00:18) trapsize 1013
\i (00:00:18) trapsize 1013
\t (00:00:18) > Sending response DoneOpenBoard
\t (00:00:18) Journal end - Sat May 10 13:22:37 2025

235
other/allegro.jrl,1
View File

@@ -1,193 +1,42 @@
\t (00:02:25) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:02:25) Journal start - Sun Apr 27 22:49:48 2025
\t (00:02:25) Host=XEROLYSKINNER User=Xeroly Pid=17144 CPUs=16
\t (00:02:25) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe
\t (00:02:25)
\t (00:02:25) Starting new design...
\i (00:02:25) trapsize 14970
\i (00:02:25) trapsize 15291
\i (00:02:25) trapsize 14970
\t (00:02:25) Grids are drawn 1300.4800, 1300.4800 apart for enhanced viewing.
\i (00:02:25) trapsize 19763
\i (00:02:25) trapsize 19763
\i (00:02:26) trapsize 18903
\i (00:02:29) param in
\i (00:02:31) setwindow form.parm_in
\i (00:02:31) FORM parm_in browse
\i (00:02:34) fillin "D:/workspace/GitHub/pcb_lib/XerolySkinner.prm"
\i (00:02:34) FORM parm_in execute
\t (00:02:34) Starting Importing parameter file...
\w (00:02:35) WARNING(SPMHGE-269): param in had warnings, use Viewlog to review the log file.
\t (00:02:35) Opening existing design...
\t (00:02:35) Grids are drawn 2.5400, 2.5400 apart for enhanced viewing.
\i (00:02:35) setwindow pcb
\i (00:02:35) trapsize 18903
\i (00:02:35) trapsize 19289
\i (00:02:35) trapsize 18903
\t (00:02:35) Grids are drawn 2.5400, 2.5400 apart for enhanced viewing.
\i (00:02:35) trapsize 19477
\i (00:02:36) setwindow text
\i (00:02:36) close
\i (00:02:37) setwindow form.parm_in
\i (00:02:37) FORM parm_in cancel
\i (00:02:39) setwindow pcb
\i (00:02:39) prmed
\i (00:02:44) setwindow form.prmedit
\i (00:02:44) FORM prmedit design
\i (00:02:48) FORM prmedit done
\i (00:02:49) setwindow pcb
\i (00:02:49) label refdes
\t (00:02:49) Pick text location.
\i (00:02:51) add pin
\i (00:02:52) setwindow form.mini
\i (00:02:52) FORM mini pad_name pcb-10b
\t (00:02:52) Using 'PCB-10B.pad'.
\i (00:02:54) setwindow pcb
\i (00:02:54) pick 0 0
\t (00:02:54) last pick: 0.0000 0.0000
\t (00:02:54) Using 'PCB-10B.pad'.
\i (00:02:55) prepopup 14.4964 -20.1725
\i (00:02:55) done
\t (00:02:55) Exiting from Add Pin.
\i (00:02:56) zoom in 1
\i (00:02:56) setwindow pcb
\i (00:02:56) zoom in 1.2521 0.4730
\i (00:02:56) trapsize 9738
\i (00:02:56) zoom in 1
\i (00:02:56) setwindow pcb
\i (00:02:56) zoom in 1.2521 0.4730
\i (00:02:56) trapsize 4869
\i (00:02:56) zoom in 1
\i (00:02:56) setwindow pcb
\i (00:02:56) zoom in 1.2521 0.4730
\i (00:02:56) trapsize 2435
\i (00:02:58) undo
\i (00:02:58) trapsize 19477
\i (00:02:59) add pin
\i (00:03:01) setwindow form.mini
\i (00:03:01) FORM mini next_pin_number 1
\i (00:03:02) FORM mini pad_name pcb-10b
\t (00:03:02) Using 'PCB-10B.pad'.
\e (00:03:04) Command not found: x0 0
\i (00:03:06) setwindow pcb
\i (00:03:06) pick 0 0
\t (00:03:06) last pick: 0.0000 0.0000
\t (00:03:06) Using 'PCB-10B.pad'.
\i (00:03:07) prepopup 16.4441 11.7696
\i (00:03:08) done
\t (00:03:08) Exiting from Add Pin.
\i (00:03:08) zoom in 1
\i (00:03:08) setwindow pcb
\i (00:03:08) zoom in -2.6433 -4.2015
\i (00:03:08) trapsize 9738
\i (00:03:09) zoom in 1
\i (00:03:09) setwindow pcb
\i (00:03:09) zoom in 1.0573 -2.2538
\i (00:03:09) trapsize 4869
\i (00:03:09) zoom in 1
\i (00:03:09) setwindow pcb
\i (00:03:09) zoom in 1.0573 -2.2537
\i (00:03:09) trapsize 2435
\i (00:03:09) zoom in 1
\i (00:03:09) setwindow pcb
\i (00:03:09) zoom in 1.0573 -2.2537
\i (00:03:09) trapsize 1217
\i (00:03:09) zoom in 1
\i (00:03:09) setwindow pcb
\i (00:03:09) zoom in 1.0574 -2.2536
\i (00:03:09) trapsize 609
\i (00:03:10) zoom out 1
\i (00:03:10) setwindow pcb
\i (00:03:10) zoom out 1.0574 -2.2536
\i (00:03:10) trapsize 1217
\i (00:03:10) zoom out 1
\i (00:03:10) setwindow pcb
\i (00:03:10) zoom out 1.0574 -2.2535
\i (00:03:10) trapsize 2435
\i (00:03:10) zoom out 1
\i (00:03:10) setwindow pcb
\i (00:03:10) zoom out 1.0572 -2.2536
\i (00:03:10) trapsize 4869
\i (00:03:10) zoom out 1
\i (00:03:10) setwindow pcb
\i (00:03:10) zoom out 1.0573 -2.2535
\i (00:03:10) trapsize 9738
\i (00:03:11) zoom in 1
\i (00:03:11) setwindow pcb
\i (00:03:11) zoom in 3.0050 1.0575
\i (00:03:11) trapsize 4869
\i (00:03:11) zoom in 1
\i (00:03:11) setwindow pcb
\i (00:03:11) zoom in 3.0050 1.0575
\i (00:03:11) trapsize 2435
\i (00:03:13) label refdes
\t (00:03:13) Pick text location.
\i (00:03:13) pick grid -2.6432 12.5976
\t (00:03:13) last pick: -2.5400 12.7000
\t (00:03:13) Enter text string.
\i (00:03:16) setwindow form.mini
\i (00:03:16) FORM mini text_name asm
\i (00:03:19) setwindow pcb
\i (00:03:19) pick -2.5400 12.7000
\i (00:03:20) setwindow pcb
\i (00:03:20) MOVE
\t (00:03:20) Select element(s) to move.
\i (00:03:21) pick grid -1.5720 12.8897
\t (00:03:21) last pick: -2.5400 12.7000
\t (00:03:21) last pick: -2.5400 12.7000
\t (00:03:21) Pick new location for the element(s).
\i (00:03:22) pick grid 1.1061 8.7509
\t (00:03:22) last pick: 0.0000 7.6200
\i (00:03:24) label refdes
\t (00:03:24) Pick text location.
\i (00:03:26) setwindow form.mini
\i (00:03:26) FORM mini subclass SILKSCREEN_TOP
\i (00:03:26) setwindow pcb
\i (00:03:26) updateport CVPane
\i (00:03:27) setwindow form.mini
\i (00:03:27) FORM mini text_name ski
\i (00:03:28) setwindow pcb
\i (00:03:28) pick grid 3.3946 7.6310
\t (00:03:28) last pick: 2.5400 7.6200
\t (00:03:28) Enter text string.
\i (00:03:31) setwindow pcb
\i (00:03:31) pick 2.5400 7.6200
\i (00:03:32) prepopup 7.6308 7.8744
\i (00:03:33) done
\i (00:03:48) save
\t (00:03:49) Symbol 'pcb-10b.psm' created.
\i (00:03:55) shape add rect
\i (00:03:58) setwindow form.mini
\i (00:03:58) FORM mini subclass ASSEMBLY_TOP
\i (00:03:58) setwindow pcb
\i (00:03:58) updateport CVPane
\i (00:04:00) zoom in 1
\i (00:04:00) setwindow pcb
\i (00:04:00) zoom in -6.1491 5.2937
\i (00:04:00) trapsize 1217
\i (00:04:02) define grid
\t (00:04:02) Spacing fields allow simple equations to aid calculations; prefix with =
\i (00:04:03) setwindow form.grid
\i (00:04:03) FORM grid non_etch non_etch_x_grids 0.1
\i (00:04:03) FORM grid non_etch non_etch_y_grids 0.1
\i (00:04:04) FORM grid done
\i (00:04:05) setwindow pcb
\i (00:04:05) zoom in 1
\i (00:04:05) setwindow pcb
\i (00:04:05) zoom in -5.4187 4.8555
\i (00:04:05) trapsize 609
\i (00:04:07) pick grid -5.4673 5.0746
\t (00:04:07) last pick: -5.5000 5.1000
\i (00:04:08) zoom out 1
\i (00:04:08) setwindow pcb
\i (00:04:08) zoom out -4.2866 5.0016
\i (00:04:08) trapsize 1217
\i (00:04:12) pick grid 5.5493 -5.1021
\t (00:04:12) last pick: 5.5000 -5.1000
\i (00:04:12) prepopup 7.2779 -0.4763
\i (00:04:13) done
\i (00:04:13) save
\i (00:04:14) fillin yes
\t (00:04:14) Symbol 'pcb-10b.psm' created.
\i (00:04:15) exit
\t (00:04:15) Journal end - Sun Apr 27 22:51:38 2025
\t (00:00:02) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Sat May 10 13:21:47 2025
\t (00:00:02) Host=XEROLYSKINNER User=Xeroly Pid=45400 CPUs=16
\t (00:00:02) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\other\rj45-8p8c.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "rj45-8p8c"
\d (00:00:02) Design opened: D:/Workspace/GitHub/pcb_lib/other/rj45-8p8c.dra
\i (00:00:02) trapsize 2935
\i (00:00:02) trapsize 3019
\i (00:00:02) trapsize 2935
\i (00:00:02) trapsize 3259
\i (00:00:02) trapsize 3259
\i (00:00:02) trapsize 2106
\i (00:00:04) color192
\i (00:00:06) QtSignal CVDLayerContainer CVDVisibilityOff clicked
\i (00:00:07) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Bottom" 1
\i (00:00:07) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 3 0
\i (00:00:10) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 1
\i (00:00:10) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:11) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 0
\i (00:00:11) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:12) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Bottom" 0
\i (00:00:12) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 3 0
\i (00:00:13) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 1
\i (00:00:13) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:13) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 0
\i (00:00:13) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:14) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Bottom" 1
\i (00:00:14) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 3 0
\i (00:00:15) QtSignal CVDLayerTable VertHeader clickedCheckBox "Soldermask_Top" 1
\i (00:00:15) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:16) QtSignal ColorVisibilityDialog CVDOkButton clicked
\i (00:00:17) color192
\i (00:00:19) QtSignal CVDLayerContainer CVDVisibilityOn clicked
\i (00:00:20) QtSignal ColorVisibilityDialog CVDOkButton clicked
\i (00:00:24) save
\i (00:00:24) fillin yes
\t (00:00:25) Symbol 'rj45-8p8c.psm' created.
\i (00:00:29) exit
\t (00:00:29) Journal end - Sat May 10 13:22:14 2025

4
other/batch_drc.log
View File

@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : B0505S_1WR3.dra )
( Drawing : rj45-8p8c.dra )
( Software Version : 23.1P001 )
( Date/Time : Tue Apr 22 23:31:49 2025 )
( Date/Time : Sat May 10 09:38:41 2025 )
( )
(---------------------------------------------------------------------)

27
other/batch_drc.log,1 Normal file
View File

@@ -0,0 +1,27 @@
(---------------------------------------------------------------------)
( )
( DRC Update )
( )
( Drawing : B0505S_1WR3.dra )
( Software Version : 23.1P001 )
( Date/Time : Tue Apr 22 23:31:49 2025 )
( )
(---------------------------------------------------------------------)
========= check shapes 0:00:00
========= check standalone pins 0:00:00
========= check symbols (pins,lines,text) 0:00:00
========= check xnets 0:00:00
========= check nets 0:00:00
========= check standalone branches 0:00:00
========= check standalone filled rectangles 0:00:00
========= check standalone lines 0:00:00
========= check standalone text 0:00:00
========= check standalone rectangles 0:00:00
..... Total number of DRC errors 0
..... DRC update completed, total CPU time 0:00:00
*************************************************************************

4
other/downrev.log
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : PCB1094M4.dra )
( Drawing : rj45-8p8c.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 22:58:41 2025 )
( Date/Time : Sat May 10 13:22:10 2025 )
( )
(---------------------------------------------------------------------)

4
other/downrev.log,1
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : PCB1094M4.dra )
( Drawing : rj45-8p8c.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 22:58:38 2025 )
( Date/Time : Sat May 10 09:38:41 2025 )
( )
(---------------------------------------------------------------------)

4
other/downrev.log,2
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : PCB1094M4.dra )
( Drawing : rj45-8p8c.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 22:58:41 2025 )
( Date/Time : Sat May 10 13:22:10 2025 )
( )
(---------------------------------------------------------------------)

4
other/downrev.log,3
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : PCB1094M4.dra )
( Drawing : rj45-8p8c.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 22:58:41 2025 )
( Date/Time : Sat May 10 13:22:10 2025 )
( )
(---------------------------------------------------------------------)

2
other/master.tag
View File

@@ -1 +1 @@
PCB1094M4.dra
rj45-8p8c.dra

12
other/padstack_editor.jrl
View File

@@ -1,7 +1,9 @@
\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:00) Journal start - Sun Apr 27 22:51:05 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=28608 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\other\pcb-10b.pad
\t (00:00:00) Journal start - Sat May 10 13:14:47 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=47704 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\other\rj45-8p8c-4.pad
\t (00:00:00)
\d (00:00:03) QtSignal MainWindow Exit triggered
\t (00:00:03) Journal end - Sun Apr 27 22:51:08 2025
\d (00:00:01) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:02) QtSignal GuidedTabsParent GuidedTabs currentChanged "Drill Offset"
\d (00:00:05) QtSignal MainWindow Exit triggered
\t (00:00:05) Journal end - Sat May 10 13:14:52 2025

39
other/padstack_editor.jrl,1
View File

@@ -1,34 +1,9 @@
\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:00) Journal start - Sun Apr 27 22:48:26 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=1428 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\other\pcb-10b.pad
\t (00:00:00) Journal start - Sat May 10 13:14:41 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=1216 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\other\rj45-8p8c-3.pad
\t (00:00:00)
\d (00:00:02) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:19) QtSignal GuidedDesignLayersTab PadWidth editingFinished "10.0000"
\d (00:00:21) QtSignal GuidedDesignLayersTab PadOffsetX editingFinished "10.8000"
\d (00:00:23) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:26) QtSignal GuidedMaskLayersTab PadWidth editingFinished "10.0000"
\d (00:00:32) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:34) QtSignal GuidedTabsParent GuidedTabs currentChanged Start
\d (00:00:36) QtSignal GuidedTabsParent NewPads currentRowChanged 3
\d (00:00:36) QtSignal GuidedTabsParent NewPads itemSelectionChanged Rectangle
\d (00:00:36) QtSignal GuidedTabsParent NewPads itemClicked Rectangle
\d (00:00:37) QtFillin Yes
\d (00:00:38) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:41) QtSignal GuidedDesignLayersTab PadWidth editingFinished "10.0000"
\d (00:00:43) QtSignal GuidedDesignLayersTab PadHeight editingFinished "10.8000"
\d (00:00:44) QtSignal GuidedDesignLayersTab PadOffsetX editingFinished "0.0000"
\d (00:00:45) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:47) QtSignal GuidedMaskLayersTab PadWidth editingFinished "10.0000"
\d (00:00:50) QtSignal GuidedMaskLayersTab PadHeight editingFinished "10.8600"
\d (00:00:50) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
\d (00:00:52) QtSignal GuidedMaskLayersTab PadWidth editingFinished "10.0600"
\d (00:00:52) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
\d (00:00:53) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
\d (00:00:53) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 "Regular Pad" 2 1
\d (00:00:55) QtSignal GuidedMaskLayersTab PadWidth editingFinished "10.0000"
\d (00:00:57) QtSignal GuidedMaskLayersTab PadHeight editingFinished "10.8000"
\d (00:00:57) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
\d (00:00:02) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:03) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:05) QtSignal MainWindow Exit triggered
\t (00:00:05) Journal end - Sat May 10 13:14:46 2025

6
other/param_read.log
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : PCB1094M4.dra )
( Drawing : USR-WIFI232-A2.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 22:55:50 2025 )
( Date/Time : Fri May 2 19:49:43 2025 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : PCB1094M4.dra
Layout Name : USR-WIFI232-A2.dra
Reading...parameter_header:
Reading...db_common_type:

8
other/param_read.log,1
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : fnwx_r1.dra )
( Drawing : WH-LTE-7S1.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 20:29:06 2025 )
( Date/Time : Sun Apr 27 20:57:13 2025 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : fnwx_r1.dra
Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : WH-LTE-7S1.dra
Reading...parameter_header:
Reading...db_common_type:

8
other/param_read.log,2
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : WH-LTE-7S1.dra )
( Drawing : pcb-10b.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 20:57:13 2025 )
( Date/Time : Sun Apr 27 22:49:58 2025 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : WH-LTE-7S1.dra
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : pcb-10b.dra
Reading...parameter_header:
Reading...db_common_type:

6
other/param_read.log,3
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : pcb-10b.dra )
( Drawing : PCB1094M4.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 22:49:58 2025 )
( Date/Time : Sun Apr 27 22:55:50 2025 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : pcb-10b.dra
Layout Name : PCB1094M4.dra
Reading...parameter_header:
Reading...db_common_type:

4
other/pcb1094m4.log
View File

@@ -4,13 +4,13 @@
( )
( Drawing : PCB1094M4.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 22:58:41 2025 )
( Date/Time : Fri May 2 01:53:20 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/other
Directory = D:/Workspace/GitHub/pcb_lib/other
Name = pcb1094m4.psm
User = Xeroly
Machine = XEROLYSKINNER

23
other/pcb1094m4.log,2 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : PCB1094M4.dra )
( Software Version : 23.1P001 )
( Date/Time : Sun Apr 27 22:58:41 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/other
Name = pcb1094m4.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

BIN
other/pcb1094m4.psm
View File

Binary file not shown.

BIN
other/rj45-8p8c-1.pad
View File

Binary file not shown.

BIN
other/rj45-8p8c-2.pad
View File

Binary file not shown.

BIN
other/rj45-8p8c-3.pad
View File

Binary file not shown.

BIN
other/rj45-8p8c-4.pad
View File

Binary file not shown.

BIN
other/rj45-8p8c.dra
View File

Binary file not shown.

23
other/rj45-8p8c.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : rj45-8p8c.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 13:22:10 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/Workspace/GitHub/pcb_lib/other
Name = rj45-8p8c.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

23
other/rj45-8p8c.log,1 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : rj45-8p8c.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 06:04:54 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/Workspace/GitHub/pcb_lib/other
Name = rj45-8p8c.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

23
other/rj45-8p8c.log,2 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : rj45-8p8c.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 09:38:41 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/Workspace/GitHub/pcb_lib/other
Name = rj45-8p8c.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

BIN
other/rj45-8p8c.psm
View File

Binary file not shown.

5851
other/stepFacetFiles4Map/PCB-1094M4.xml Normal file
View File

File diff suppressed because it is too large Load Diff

3
other/stepFacetFiles4Map/stepFileInfo.txt
View File

@@ -4,12 +4,13 @@ XH2_54-W2P.step ! 183892 ! 1745749128
link_3.5_2x1.STEP ! 435783 ! 1723144412
TYPE-C.stp ! 1362496 ! 1710578258
KF7.62-2P.STEP ! 217264 ! 1722981445
EC11.STEP ! 1541194 ! 1712715932
rtl8189-board.STEP ! 1900144 ! 1712473643
EC11.STEP ! 1541194 ! 1712715932
link_3.5_2x5.STEP ! 467005 ! 1723144633
XH2_54-W3P.step ! 213594 ! 1745749034
KF7.62-3P.STEP ! 218099 ! 1722981496
rj45-8p8c.step ! 2080205 ! 1712409758
PCB-1094M4.STEP ! 66472 ! 1746121909
XH2_54-W5P.step ! 305916 ! 1745749057
link_3.5_2x4.STEP ! 466145 ! 1723146123
fpc0_5-40p.stp ! 9221743 ! 1584132940

4
other/stepFacetFiles4Map/stepFileInfo.txt,1
View File

@@ -4,8 +4,8 @@ XH2_54-W2P.step ! 183892 ! 1745749128
link_3.5_2x1.STEP ! 435783 ! 1723144412
TYPE-C.stp ! 1362496 ! 1710578258
KF7.62-2P.STEP ! 217264 ! 1722981445
rtl8189-board.STEP ! 1900144 ! 1712473643
EC11.STEP ! 1541194 ! 1712715932
rtl8189-board.STEP ! 1900144 ! 1712473643
link_3.5_2x5.STEP ! 467005 ! 1723144633
XH2_54-W3P.step ! 213594 ! 1745749034
KF7.62-3P.STEP ! 218099 ! 1722981496
@@ -15,6 +15,6 @@ link_3.5_2x4.STEP ! 466145 ! 1723146123
fpc0_5-40p.stp ! 9221743 ! 1584132940
fpc0_5-6p.stp ! 1966209 ! 1584132963
fpc0_5-50p.stp ! 11408226 ! 1584132947
B05051WR3.STEP ! 65139 ! 1745402887
B05051WR3.STEP ! 65128 ! 1745749519
wh-gm5.STEP ! 888098 ! 1712839932
oled-0_96.step ! 601137 ! 1712757601

23
other/usr-wifi232-a2.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : USR-WIFI232-A2.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri May 2 19:56:28 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/other
Name = usr-wifi232-a2.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

24
other/usr-wifi232-a2.log,1 Normal file
View File

@@ -0,0 +1,24 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : USR-WIFI232-A2.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri May 2 19:56:08 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/other
Name = usr-wifi232-a2.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
ERROR(SPMHCS-1): Symbol is missing a refdes.
ERROR(SPMHA1-291): Create symbol has been aborted.

BIN
other/usr-wifi232-a2.psm Normal file
View File

Binary file not shown.

473
smc/allegro.jrl
View File

@@ -1,33 +1,440 @@
\t (00:00:01) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:01) Journal start - Fri Apr 25 17:19:42 2025
\t (00:00:01) Host=XEROLYSKINNER User=Xeroly Pid=23772 CPUs=16
\t (00:00:01) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\smc\sod-323.dra
\t (00:00:01)
(00:00:01) Loading axlcore.cxt
\t (00:00:01) Opening existing design...
\i (00:00:01) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sod-323"
\d (00:00:01) Design opened: D:/Workspace/GitHub/pcb_lib/smc/sod-323.dra
\i (00:00:02) trapsize 370
\i (00:00:02) trapsize 381
\i (00:00:02) trapsize 370
\i (00:00:02) trapsize 418
\i (00:00:02) trapsize 288
\i (00:00:04) delete
\i (00:00:05) pick grid -1.7374 2.9915
\t (00:00:05) last pick: -1.7000 3.0000
\t (00:00:05) Text "Last Edit:2024-3-28"
\i (00:00:06) pick grid -2.1403 1.4894
\t (00:00:06) last pick: -2.1000 1.5000
\t (00:00:06) Text "Approved[1]"
\i (00:00:07) pick grid -2.1403 -1.6759
\t (00:00:07) last pick: -2.1000 -1.7000
\t (00:00:07) Text "*Untested*"
\i (00:00:14) pick grid 1.6409 -1.4054
\t (00:00:14) last pick: 1.6000 -1.4000
\i (00:00:17) prepopup 1.4222 -1.6816
\i (00:00:18) done
\i (00:00:19) save
\i (00:00:19) fillin yes
\t (00:00:20) Symbol 'sod-323.psm' created.
\i (00:00:20) exit
\t (00:00:20) Journal end - Fri Apr 25 17:20:01 2025
\t (00:00:37) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:37) Journal start - Sat May 10 04:58:28 2025
\t (00:00:37) Host=XEROLYSKINNER User=Xeroly Pid=35792 CPUs=16
\t (00:00:37) CmdLine= D:\software\Cadence\SPB_23.1\tools\bin\allegro.exe
\t (00:00:37)
\t (00:00:37) Starting new design...
\i (00:00:37) trapsize 101
\i (00:00:37) trapsize 103
\i (00:00:37) trapsize 101
\t (00:00:37) Grids are drawn 40.640, 40.640 apart for enhanced viewing.
\i (00:00:37) trapsize 101
\i (00:00:37) trapsize 101
\i (00:00:37) package symbol wizard
(00:00:39) Loading cmds.cxt
\i (00:00:39) setwindow form.sym_wizard
\i (00:00:39) FORM sym_wizard soic YES
\i (00:00:40) FORM sym_wizard wiz_next
\i (00:00:41) FORM sym_wizard load_template
\t (00:00:41) Opening existing design...
\t (00:00:41) Grids are drawn 200, 200 apart for enhanced viewing.
\i (00:00:41) setwindow pcb
\i (00:00:41) trapsize 126
\i (00:00:41) trapsize 129
\i (00:00:41) trapsize 126
\t (00:00:41) Grids are drawn 200, 200 apart for enhanced viewing.
\i (00:00:41) trapsize 148
\d (00:00:41) Design opened: D:/software/Cadence/SPB_23.1/share/pcb/pcb_lib/symbols/template/sym_template.dra
\i (00:00:41) trapsize 143
\i (00:00:42) setwindow form.sym_wizard
\i (00:00:42) FORM sym_wizard wiz_next
\i (00:00:44) FORM sym_wizard pack_units Millimeter
\i (00:00:46) FORM sym_wizard pack_units_create Millimeter
\i (00:00:47) FORM sym_wizard wiz_next
\i (00:00:58) FORM sym_wizard sop_pin_count 1
\i (00:00:58) FORM sym_wizard sop_pin_count 4
\i (00:01:04) FORM sym_wizard sop_e 2.540
\i (00:01:31) FORM sym_wizard sop_e1 9.160
\i (00:01:34) FORM sym_wizard sop_width 6.450
\i (00:02:05) FORM sym_wizard sop_len 4.500
\i (00:02:05) FORM sym_wizard wiz_next
\i (00:02:08) FORM sym_wizard default_padstack smd_4
\i (00:02:09) FORM sym_wizard wiz_next
\i (00:02:10) FORM sym_wizard wiz_next
\i (00:02:11) FORM sym_wizard wiz_finish
\w (00:02:11) WARNING(SPMHUT-48): Scaled value has been rounded off.
\t (00:02:11) Grids are drawn 5.080, 5.080 apart for enhanced viewing.
\i (00:02:11) setwindow pcb
\i (00:02:11) trapsize 3638
\t (00:02:11) Performing DRC...
\t (00:02:11) No DRC errors detected.
\w (00:02:11) WARNING(SPMHUT-48): Scaled value has been rounded off.
\i (00:02:11) trapsize 3638
\i (00:02:11) trapsize 44
\i (00:02:11) trapsize 44
\i (00:02:11) trapsize 44
\i (00:02:11) trapsize 44
\t (00:02:11) Performing DRC...
\t (00:02:11) No DRC errors detected.
\t (00:02:11) Creating package symbol 'D:/workspace/GitHub/pcb_lib/smc/smd_4.psm'.
\t (00:02:11) Starting Create symbol...
\i (00:02:15) param in
\i (00:02:16) setwindow form.parm_in
\i (00:02:16) FORM parm_in browse
\i (00:02:20) fillin "D:/workspace/GitHub/pcb_lib/XerolySkinner.prm"
\i (00:02:21) FORM parm_in execute
\t (00:02:21) Starting Importing parameter file...
\w (00:02:21) WARNING(SPMHGE-269): param in had warnings, use Viewlog to review the log file.
\t (00:02:21) Opening existing design...
\t (00:02:22) Grids are drawn 40.640, 40.640 apart for enhanced viewing.
\i (00:02:22) setwindow pcb
\i (00:02:22) trapsize 44
\i (00:02:23) setwindow text
\i (00:02:23) close
\i (00:02:25) setwindow form.parm_in
\i (00:02:25) FORM parm_in cancel
\i (00:02:30) setwindow pcb
\i (00:02:30) define grid
\t (00:02:30) Spacing fields allow simple equations to aid calculations; prefix with =
\i (00:02:33) setwindow form.grid
\i (00:02:33) FORM grid non_etch non_etch_x_grids 0.01
\i (00:02:34) FORM grid non_etch non_etch_y_grids 0.01
\i (00:02:36) FORM grid all_etch all_etch_x_grids 0.01
\i (00:02:36) FORM grid all_etch all_etch_y_grids 0.01
\i (00:02:37) FORM grid all_etch all_etch_x_offset 0.000
\i (00:02:37) FORM grid all_etch all_etch_y_offset 0.000
\i (00:02:38) FORM grid top subclass_x_grids 0.010
\i (00:02:38) FORM grid top subclass_x_grids 0.010
\i (00:02:38) FORM grid done
\t (00:02:38) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
\i (00:02:39) setwindow pcb
\i (00:02:39) zoom out 1
\i (00:02:39) setwindow pcb
\i (00:02:39) zoom out -0.775 -4.376
\t (00:02:39) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
\i (00:02:39) trapsize 87
\i (00:02:41) zoom in 1
\i (00:02:41) setwindow pcb
\i (00:02:41) zoom in 0.658 1.234
\t (00:02:41) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
\i (00:02:41) trapsize 44
\i (00:02:41) zoom in 1
\i (00:02:41) setwindow pcb
\i (00:02:41) zoom in 0.658 1.234
\t (00:02:41) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
\i (00:02:41) trapsize 22
\i (00:02:42) zoom out 1
\i (00:02:42) setwindow pcb
\i (00:02:42) zoom out 0.659 1.234
\t (00:02:42) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
\i (00:02:42) trapsize 44
\i (00:02:42) zoom out 1
\i (00:02:42) setwindow pcb
\i (00:02:42) zoom out 0.658 1.235
\t (00:02:42) Grids are drawn 0.080, 0.080 apart for enhanced viewing.
\i (00:02:42) trapsize 87
\i (00:02:43) add line
\i (00:02:46) setwindow form.mini
\i (00:02:46) FORM mini class 'PACKAGE GEOMETRY'
\i (00:02:48) FORM mini subclass SILKSCREEN_TOP
\i (00:02:48) setwindow pcb
\i (00:02:48) updateport CVPane
\i (00:02:50) setwindow form.mini
\i (00:02:50) FORM mini line_width 0.150
\i (00:02:52) setwindow pcb
\i (00:02:52) zoom in 1
\i (00:02:52) setwindow pcb
\i (00:02:52) zoom in -3.147 2.316
\t (00:02:52) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
\i (00:02:52) trapsize 44
\i (00:02:52) zoom in 1
\i (00:02:52) setwindow pcb
\i (00:02:52) zoom in -3.147 2.316
\t (00:02:52) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
\i (00:02:52) trapsize 22
\i (00:02:52) zoom in 1
\i (00:02:52) setwindow pcb
\i (00:02:52) zoom in -3.147 2.316
\i (00:02:52) trapsize 11
\i (00:02:53) zoom out 1
\i (00:02:53) setwindow pcb
\i (00:02:53) zoom out -3.146 2.316
\i (00:02:53) trapsize 22
\i (00:02:53) zoom out 1
\i (00:02:53) setwindow pcb
\i (00:02:53) zoom out -3.147 2.316
\t (00:02:53) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
\i (00:02:53) trapsize 44
\i (00:02:54) color192
\i (00:02:55) QtSignal CVDLayerContainer CVDVisibilityOff clicked
\i (00:02:59) QtSignal CVDLayerContainer CVDFilterLayerEntry editingFinished silk
\i (00:02:59) QtSignal CVDLayerTable VertHeader clickedCheckBox "Silkscreen_Top" 1
\i (00:02:59) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 1 0
\i (00:03:00) QtSignal ColorVisibilityDialog CVDOkButton clicked
\i (00:03:01) delete
\i (00:03:04) setwindow form.find
\i (00:03:04) FORM find all_on
\i (00:03:05) setwindow pcb
\i (00:03:05) pick grid 2.832 2.228
\t (00:03:05) last pick: 2.830 2.230
\t (00:03:05) Line "Package Geometry/Silkscreen_Top"
\i (00:03:05) prepopup 3.016 2.534
\i (00:03:06) done
\i (00:03:07) color192
\i (00:03:08) QtSignal CVDLayerContainer CVDVisibilityOn clicked
\i (00:03:09) QtSignal ColorVisibilityDialog CVDOkButton clicked
\i (00:03:10) add line
\i (00:03:13) zoom in 1
\i (00:03:13) setwindow pcb
\i (00:03:13) zoom in -3.173 2.220
\t (00:03:13) Grids are drawn 0.020, 0.020 apart for enhanced viewing.
\i (00:03:13) trapsize 22
\i (00:03:13) zoom in 1
\i (00:03:13) setwindow pcb
\i (00:03:13) zoom in -3.173 2.220
\i (00:03:13) trapsize 11
\i (00:03:13) zoom in 1
\i (00:03:13) setwindow pcb
\i (00:03:13) zoom in -3.173 2.220
\i (00:03:13) trapsize 5
\i (00:03:14) zoom in 1
\i (00:03:14) setwindow pcb
\i (00:03:14) zoom in -3.208 2.254
\i (00:03:14) trapsize 3
\i (00:03:14) zoom in 1
\i (00:03:14) setwindow pcb
\i (00:03:14) zoom in -3.208 2.254
\i (00:03:14) trapsize 1
\i (00:03:17) define grid
\t (00:03:17) Spacing fields allow simple equations to aid calculations; prefix with =
\i (00:03:18) setwindow form.grid
\i (00:03:18) FORM grid non_etch non_etch_x_grids 0.1
\i (00:03:19) FORM grid non_etch non_etch_y_grids 0.1
\i (00:03:20) FORM grid all_etch all_etch_x_grids 0.1
\i (00:03:20) FORM grid all_etch all_etch_y_grids 0.1
\i (00:03:20) FORM grid all_etch all_etch_x_offset 0.000
\i (00:03:21) FORM grid all_etch all_etch_y_offset 0.000
\i (00:03:21) FORM grid top subclass_x_grids 0.100
\i (00:03:21) FORM grid top subclass_x_grids 0.100
\i (00:03:21) FORM grid done
\i (00:03:22) setwindow pcb
\i (00:03:22) zoom out 1
\i (00:03:22) setwindow pcb
\i (00:03:22) zoom out -3.218 2.264
\i (00:03:22) trapsize 3
\i (00:03:23) zoom out 1
\i (00:03:23) setwindow pcb
\i (00:03:23) zoom out -3.214 2.243
\i (00:03:23) trapsize 5
\i (00:03:23) zoom out 1
\i (00:03:23) setwindow pcb
\i (00:03:23) zoom out -3.215 2.243
\i (00:03:23) trapsize 11
\i (00:03:23) zoom out 1
\i (00:03:23) setwindow pcb
\i (00:03:23) zoom out -3.214 2.243
\i (00:03:23) trapsize 22
\i (00:03:26) pick grid -3.197 2.300
\t (00:03:26) last pick: -3.200 2.300
\i (00:03:26) pick grid -3.351 1.815
\t (00:03:26) last pick: -3.400 1.800
\i (00:03:26) zoom in 1
\i (00:03:26) setwindow pcb
\i (00:03:26) zoom in -3.429 1.780
\i (00:03:26) trapsize 11
\i (00:03:26) zoom in 1
\i (00:03:26) setwindow pcb
\i (00:03:26) zoom in -3.429 1.780
\i (00:03:26) trapsize 5
\i (00:03:27) prepopup -3.428 1.780
\i (00:03:28) oops
\t (00:03:28) last pick: -3.200 2.300
\i (00:03:28) zoom out 1
\i (00:03:28) setwindow pcb
\i (00:03:28) zoom out -3.428 1.780
\i (00:03:28) trapsize 11
\i (00:03:28) zoom out 1
\i (00:03:28) setwindow pcb
\i (00:03:28) zoom out -3.429 1.780
\i (00:03:28) trapsize 22
\i (00:03:28) zoom out 1
\i (00:03:28) setwindow pcb
\i (00:03:28) zoom out -3.428 1.781
\i (00:03:28) trapsize 44
\i (00:03:28) zoom out 1
\i (00:03:28) setwindow pcb
\i (00:03:28) zoom out -3.429 1.780
\i (00:03:28) trapsize 88
\i (00:03:29) zoom out 1
\i (00:03:29) setwindow pcb
\i (00:03:29) zoom out 2.978 1.954
\i (00:03:29) trapsize 125
\i (00:03:29) zoom out 1
\i (00:03:29) setwindow pcb
\i (00:03:29) zoom out -2.036 -0.089
\i (00:03:29) trapsize 125
\i (00:03:29) zoom out 1
\i (00:03:29) setwindow pcb
\i (00:03:29) zoom out -2.036 -0.089
\i (00:03:29) trapsize 125
\i (00:03:30) zoom in 1
\i (00:03:30) setwindow pcb
\i (00:03:30) zoom in 3.755 2.831
\i (00:03:30) trapsize 62
\i (00:03:30) zoom in 1
\i (00:03:30) setwindow pcb
\i (00:03:30) zoom in 3.755 4.790
\i (00:03:30) trapsize 31
\i (00:03:30) zoom in 1
\i (00:03:30) setwindow pcb
\i (00:03:30) zoom in 3.755 4.790
\i (00:03:30) trapsize 16
\i (00:03:30) zoom in 1
\i (00:03:30) setwindow pcb
\i (00:03:30) zoom in 3.755 4.790
\i (00:03:30) trapsize 8
\i (00:03:31) zoom out 1
\i (00:03:31) setwindow pcb
\i (00:03:31) zoom out 3.496 4.337
\i (00:03:31) trapsize 16
\i (00:03:33) pick grid 3.216 2.346
\t (00:03:33) last pick: 3.200 2.300
\i (00:03:34) zoom out 1
\i (00:03:34) setwindow pcb
\i (00:03:34) zoom out 3.337 3.653
\i (00:03:34) trapsize 31
\i (00:03:34) zoom out 1
\i (00:03:34) setwindow pcb
\i (00:03:34) zoom out 3.338 2.589
\i (00:03:34) trapsize 62
\i (00:03:34) zoom out 1
\i (00:03:34) setwindow pcb
\i (00:03:34) zoom out 3.338 -1.572
\i (00:03:34) trapsize 125
\i (00:03:34) zoom out 1
\i (00:03:34) setwindow pcb
\i (00:03:34) zoom out -1.662 -9.899
\i (00:03:34) trapsize 125
\i (00:03:35) zoom in 1
\i (00:03:35) setwindow pcb
\i (00:03:35) zoom in 3.106 -2.136
\i (00:03:35) trapsize 62
\i (00:03:35) zoom in 1
\i (00:03:35) setwindow pcb
\i (00:03:35) zoom in 3.106 2.307
\i (00:03:35) trapsize 31
\i (00:03:38) pick grid 3.249 -2.323
\t (00:03:38) last pick: 3.200 -2.300
\i (00:03:39) zoom out 1
\i (00:03:39) setwindow pcb
\i (00:03:39) zoom out 3.149 -0.981
\i (00:03:39) trapsize 62
\i (00:03:39) zoom out 1
\i (00:03:39) setwindow pcb
\i (00:03:39) zoom out 3.150 -4.270
\i (00:03:39) trapsize 125
\i (00:03:40) zoom in 1
\i (00:03:40) setwindow pcb
\i (00:03:40) zoom in -2.311 -2.036
\i (00:03:40) trapsize 62
\i (00:03:42) zoom in 1
\i (00:03:42) setwindow pcb
\i (00:03:42) zoom in -3.147 -2.298
\i (00:03:42) trapsize 31
\i (00:03:44) pick grid -3.246 -2.298
\t (00:03:44) last pick: -3.200 -2.300
\i (00:03:44) zoom out 1
\i (00:03:44) setwindow pcb
\i (00:03:44) zoom out -3.315 -2.704
\i (00:03:44) trapsize 62
\i (00:03:46) zoom out 1
\i (00:03:46) setwindow pcb
\i (00:03:46) zoom out -3.040 2.394
\i (00:03:46) trapsize 125
\i (00:03:46) zoom out 1
\i (00:03:46) setwindow pcb
\i (00:03:46) zoom out -4.108 -1.961
\i (00:03:46) trapsize 125
\i (00:03:46) zoom out 1
\i (00:03:46) setwindow pcb
\i (00:03:46) zoom out -4.108 -1.961
\i (00:03:46) trapsize 125
\i (00:03:47) zoom in 1
\i (00:03:47) setwindow pcb
\i (00:03:47) zoom in -2.935 2.956
\i (00:03:47) trapsize 62
\i (00:03:48) zoom in 1
\i (00:03:48) setwindow pcb
\i (00:03:48) zoom in -2.760 2.619
\i (00:03:48) trapsize 31
\i (00:03:50) pick grid -3.153 2.282
\t (00:03:50) last pick: -3.200 2.300
\i (00:03:50) prepopup -3.228 2.282
\i (00:03:50) done
\i (00:03:53) shape add rect
\i (00:03:56) pick grid -3.203 2.301
\t (00:03:56) last pick: -3.200 2.300
\i (00:03:59) pick 0 0
\t (00:03:59) last pick: 0.000 0.000
\i (00:04:00) prepopup -2.885 3.518
\i (00:04:00) done
\i (00:04:01) zoom out 1
\i (00:04:01) setwindow pcb
\i (00:04:01) zoom out -3.871 3.412
\i (00:04:01) trapsize 62
\i (00:04:04) change
\i (00:04:07) setwindow form.mini
\i (00:04:07) FORM mini change_class 'PACKAGE GEOMETRY'
\i (00:04:08) FORM mini change_subclass PIN_NUMBER
\i (00:04:10) FORM mini text_name pin
\i (00:04:11) setwindow pcb
\i (00:04:11) pick grid 4.691 1.957
\t (00:04:11) last pick: 4.700 2.000
\t (00:04:11) No DRC errors detected.
\t (00:04:11) Changed 1 items out of 1 items found.
\i (00:04:12) pick grid 4.654 -0.876
\t (00:04:12) last pick: 4.700 -0.900
\t (00:04:12) No DRC errors detected.
\t (00:04:12) Changed 1 items out of 1 items found.
\i (00:04:13) pick grid -4.619 2.082
\t (00:04:13) last pick: -4.600 2.100
\t (00:04:13) No DRC errors detected.
\t (00:04:13) Changed 1 items out of 1 items found.
\i (00:04:14) pick grid -4.444 -0.426
\t (00:04:14) last pick: -4.400 -0.400
\t (00:04:14) No DRC errors detected.
\t (00:04:14) Changed 1 items out of 1 items found.
\i (00:04:14) prepopup -2.784 3.530
\i (00:04:15) done
\i (00:04:16) change
\i (00:04:19) setwindow form.mini
\i (00:04:19) FORM mini change_class 'REF DES'
\i (00:04:20) FORM mini change_subclass ASSEMBLY_TOP
\i (00:04:24) FORM mini text_name asm
\i (00:04:25) setwindow pcb
\i (00:04:25) pick grid 0.348 0.535
\t (00:04:25) last pick: 0.300 0.500
\t (00:04:25) No DRC errors detected.
\t (00:04:25) Changed 1 items out of 1 items found.
\i (00:04:26) prepopup 1.072 3.592
\i (00:04:26) done
\i (00:04:30) move
\t (00:04:30) Select element(s) to move.
\i (00:04:31) pick grid 7.499 0.435
\t (00:04:31) last pick: 7.500 0.400
\t (00:04:31) last pick: 6.412 0.000
\t (00:04:31) Pick new location for the element(s).
\i (00:04:33) pick grid 1.571 -1.762
\t (00:04:33) last pick: 1.600 -1.800
\i (00:04:33) prepopup 1.559 6.163
\i (00:04:34) done
\i (00:04:36) step pkg map
\i (00:04:37) fillin yes
\i (00:04:47) setwindow form.pkgmap3d
\i (00:04:47) FORM pkgmap3d namefilter_stp PC817.STEP
\i (00:04:48) FORM pkgmap3d stplist PC817.STEP
\i (00:04:51) FORM pkgmap3d rotation_z 90
\i (00:04:52) FORM pkgmap3d rotation_z 0
\i (00:04:52) FORM pkgmap3d rotation_y 90
\i (00:04:54) FORM pkgmap3d rotation_y 0
\i (00:04:54) FORM pkgmap3d rotation_x 90
\i (00:04:56) FORM pkgmap3d hide_board YES
\i (00:04:57) FORM pkgmap3d overlay YES
\i (00:04:59) FORM pkgmap3d rotation_z 90
\i (00:05:02) FORM pkgmap3d view_orientation Top
\i (00:05:05) FORM pkgmap3d rotation_z -90
\i (00:05:07) FORM pkgmap3d view_orientation Right
\i (00:05:10) FORM pkgmap3d offset_z 10
\i (00:05:11) FORM pkgmap3d offset_z 5
\i (00:05:13) FORM pkgmap3d offset_z 2
\i (00:05:16) FORM pkgmap3d offset_z 2.5
\i (00:05:18) FORM pkgmap3d offset_z 2.1
\i (00:05:21) FORM pkgmap3d view_orientation Top
\i (00:05:25) FORM pkgmap3d save_current
\i (00:05:27) FORM pkgmap3d done
\i (00:05:27) setwindow pcb
\i (00:05:27) save
\i (00:05:28) fillin yes
\t (00:05:28) Symbol 'smd_4.psm' created.
\i (00:05:29) exit
\t (00:05:29) Journal end - Sat May 10 05:03:21 2025

63
smc/allegro.jrl,1
View File

@@ -1,31 +1,32 @@
\t (00:00:01) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:01) Journal start - Fri Apr 25 17:19:11 2025
\t (00:00:01) Host=XEROLYSKINNER User=Xeroly Pid=10760 CPUs=16
\t (00:00:01) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\smc\sot-23-6p.dra
\t (00:00:01)
(00:00:01) Loading axlcore.cxt
\t (00:00:01) Opening existing design...
\i (00:00:01) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sot-23-6p"
\d (00:00:01) Design opened: D:/Workspace/GitHub/pcb_lib/smc/sot-23-6p.dra
\i (00:00:02) trapsize 328
\i (00:00:02) trapsize 337
\i (00:00:02) trapsize 328
\i (00:00:02) trapsize 370
\i (00:00:02) trapsize 255
\i (00:00:03) delete
\i (00:00:05) pick grid 1.2217 3.1662
\t (00:00:05) last pick: 1.2000 3.2000
\t (00:00:05) Text "Last Edit:2024-4-6"
\i (00:00:05) pick grid 2.7610 1.7798
\t (00:00:05) last pick: 2.8000 1.8000
\t (00:00:05) Text "Approved[1]"
\i (00:00:06) pick grid 3.0464 0.1793
\t (00:00:06) last pick: 3.0000 0.2000
\t (00:00:06) Text "*Untested*"
\i (00:00:06) prepopup 3.0464 0.1793
\i (00:00:07) done
\i (00:00:07) save
\i (00:00:08) fillin yes
\t (00:00:08) Symbol 'sot-23-6p.psm' created.
\i (00:00:09) exit
\t (00:00:09) Journal end - Fri Apr 25 17:19:19 2025
\t (00:00:02) allegro 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Sat May 3 00:58:28 2025
\t (00:00:02) Host=XEROLYSKINNER User=Xeroly Pid=14560 CPUs=16
\t (00:00:02) CmdLine= d:\software\cadence\spb_23.1\tools\bin\allegro.exe D:\Workspace\GitHub\pcb_lib\smc\led0603.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged led0603
\d (00:00:02) Design opened: D:/Workspace/GitHub/pcb_lib/smc/led0603.dra
\i (00:00:02) trapsize 639
\i (00:00:02) trapsize 657
\i (00:00:02) trapsize 639
\i (00:00:02) trapsize 679
\i (00:00:02) trapsize 721
\i (00:00:02) trapsize 486
\i (00:00:06) delete
\i (00:00:08) pick grid 3.3549 1.6525
\t (00:00:08) last pick: 3.4000 1.7000
\t (00:00:08) Text "Last Edit:2024-03-17"
\i (00:00:08) pick grid 2.2263 -1.7332
\t (00:00:08) last pick: 2.2000 -1.7000
\t (00:00:08) Text "Approved[1]"
\i (00:00:09) pick grid 1.4480 -3.0953
\t (00:00:09) last pick: 1.4000 -3.1000
\t (00:00:09) Text "*Untested*"
\i (00:00:09) prepopup 1.4480 -3.0953
\i (00:00:10) done
\i (00:00:10) exit
\e (00:00:10) Do you want to save the changes you made to led0603.dra?
\i (00:00:11) fillin yes
\t (00:00:11) Symbol 'led0603.psm' created.
\t (00:00:11) Journal end - Sat May 3 00:58:37 2025

6
smc/batch_drc.log
View File

@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : ll34.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 21:11:16 2024 )
( Drawing : sym_template.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 05:00:03 2025 )
( )
(---------------------------------------------------------------------)

27
smc/batch_drc.log,1 Normal file
View File

@@ -0,0 +1,27 @@
(---------------------------------------------------------------------)
( )
( DRC Update )
( )
( Drawing : ll34.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 21:11:16 2024 )
( )
(---------------------------------------------------------------------)
========= check shapes 0:00:00
========= check standalone pins 0:00:00
========= check symbols (pins,lines,text) 0:00:00
========= check xnets 0:00:00
========= check nets 0:00:00
========= check standalone branches 0:00:00
========= check standalone filled rectangles 0:00:00
========= check standalone lines 0:00:00
========= check standalone text 0:00:00
========= check standalone rectangles 0:00:00
..... Total number of DRC errors 0
..... DRC update completed, total CPU time 0:00:00
*************************************************************************

27
smc/batch_drc.log,2 Normal file
View File

@@ -0,0 +1,27 @@
(---------------------------------------------------------------------)
( )
( DRC Update )
( )
( Drawing : sym_template.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 10 05:00:03 2025 )
( )
(---------------------------------------------------------------------)
========= check shapes 0:00:00
========= check standalone pins 0:00:00
========= check symbols (pins,lines,text) 0:00:00
========= check xnets 0:00:00
========= check nets 0:00:00
========= check standalone branches 0:00:00
========= check standalone filled rectangles 0:00:00
========= check standalone lines 0:00:00
========= check standalone text 0:00:00
========= check standalone rectangles 0:00:00
..... Total number of DRC errors 0
..... DRC update completed, total CPU time 0:00:00
*************************************************************************

4
smc/downrev.log
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : sod-323.dra )
( Drawing : smd_4.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri Apr 25 17:20:00 2025 )
( Date/Time : Sat May 10 05:03:20 2025 )
( )
(---------------------------------------------------------------------)

4
smc/downrev.log,1
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : sot-23-6p.dra )
( Drawing : smd_4.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri Apr 25 17:19:18 2025 )
( Date/Time : Sat May 10 05:00:13 2025 )
( )
(---------------------------------------------------------------------)

4
smc/downrev.log,2
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : sod-323.dra )
( Drawing : smd_4.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri Apr 25 17:20:00 2025 )
( Date/Time : Sat May 10 05:03:19 2025 )
( )
(---------------------------------------------------------------------)

4
smc/downrev.log,3
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : sod-323.dra )
( Drawing : smd_4.dra )
( Software Version : 23.1P001 )
( Date/Time : Fri Apr 25 17:20:00 2025 )
( Date/Time : Sat May 10 05:03:19 2025 )
( )
(---------------------------------------------------------------------)

BIN
smc/led0603.dra
View File

Binary file not shown.

23
smc/led0603.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : led0603.dra )
( Software Version : 23.1P001 )
( Date/Time : Sat May 3 00:58:37 2025 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/Workspace/GitHub/pcb_lib/smc
Name = led0603.psm
User = Xeroly
Machine = XEROLYSKINNER
Create symbol started.
Create symbol completed.

BIN
smc/led0603.psm
View File

Binary file not shown.

2
smc/master.tag
View File

@@ -1 +1 @@
sod-323.dra
smd_4.dra

49
smc/padstack_editor.jrl
View File

@@ -1,7 +1,46 @@
\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:00) Journal start - Fri Apr 25 17:19:26 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=32596 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\smc\sod-323.pad
\t (00:00:00) Journal start - Sat May 10 04:54:55 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=28848 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\smc\smd_4.pad
\t (00:00:00)
\d (00:00:02) QtSignal MainWindow Exit triggered
\t (00:00:02) Journal end - Fri Apr 25 17:19:28 2025
\d (00:00:02) QtSignal GuidedTabsParent NewPads currentRowChanged 2
\d (00:00:02) QtSignal GuidedTabsParent NewPads itemSelectionChanged Oblong
\d (00:00:02) QtSignal GuidedTabsParent NewPads itemClicked Oblong
\d (00:00:02) QtFillin Yes
\d (00:00:05) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:06) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
\d (00:00:06) QtSignal 1
\d (00:00:07) QtSignal GuidedTabsParent GuidedTabs currentChanged Start
\d (00:00:08) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:08) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
\d (00:00:08) QtSignal 1
\d (00:00:09) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
\d (00:00:09) QtSignal 1
\d (00:00:54) QtSignal GuidedDesignLayersTab PadWidth editingFinished "1.0000"
\d (00:00:58) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
\d (00:00:58) QtSignal 1
\d (00:01:04) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
\d (00:01:04) QtSignal 1
\d (00:01:30) QtSignal GuidedDesignLayersTab PadHeight editingFinished "1.2500"
\d (00:01:36) QtSignal GuidedDesignLayersTab PadWidth editingFinished "2.0000"
\d (00:01:39) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:01:44) QtSignal GuidedMaskLayersTab PadWidth editingFinished "2.0000"
\d (00:01:45) QtSignal GuidedMaskLayersTab PadHeight editingFinished "1.2500"
\d (00:01:46) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
\d (00:01:46) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 "Regular Pad" 2 1
\d (00:01:50) QtSignal GuidedMaskLayersTab PadWidth editingFinished "2.0000"
\d (00:01:51) QtSignal GuidedMaskLayersTab PadHeight editingFinished "1.2500"
\d (00:01:54) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 0 "Regular Pad"
\d (00:01:54) QtSignal GuidedMaskLayersTab LayersTable cellClicked 0 "Regular Pad" 0 1
\d (00:02:30) QtSignal GuidedMaskLayersTab PadWidth editingFinished "2.0500"
\d (00:02:32) QtSignal GuidedMaskLayersTab PadHeight editingFinished "1.3000"
\d (00:02:32) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777220 0 false 1 "
"
\d (00:02:39) QtSignal GuidedMaskLayersTab PadWidth editingFinished "2.5500"
\d (00:02:42) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 "Regular Pad"
\d (00:02:42) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 "Regular Pad" 2 1
\d (00:02:44) QtSignal GuidedMaskLayersTab PadWidth editingFinished "2.5000"
\d (00:02:45) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:02:47) QtSignal GuidedDesignLayersTab PadWidth editingFinished "2.5000"
\d (00:02:49) QtSignal MainWindow Save triggered
\d (00:02:51) QtSignal MainWindow Exit triggered

8
smc/padstack_editor.jrl,1
View File

@@ -1,7 +1,7 @@
\t (00:00:00) padstack_editor 23.1 P001 Windows SPB 64-bit Edition
\t (00:00:00) Journal start - Fri Apr 25 14:34:41 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=22968 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\smc\1206.pad
\t (00:00:00) Journal start - Fri Apr 25 17:19:26 2025
\t (00:00:00) Host=XEROLYSKINNER User=Xeroly Pid=32596 CPUs=16
\t (00:00:00) CmdLine= d:\software\cadence\spb_23.1\tools\bin\padstack_editor.exe D:\Workspace\GitHub\pcb_lib\smc\sod-323.pad
\t (00:00:00)
\d (00:00:02) QtSignal MainWindow Exit triggered
\t (00:00:02) Journal end - Fri Apr 25 14:34:42 2025
\t (00:00:02) Journal end - Fri Apr 25 17:19:28 2025

8
smc/param_read.log
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : 3215.dra )
( Drawing : smd_4.dra )
( Software Version : 23.1P001 )
( Date/Time : Wed Apr 23 21:26:35 2025 )
( Date/Time : Sat May 10 05:00:13 2025 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/Workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : 3215.dra
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/workspace/GitHub/pcb_lib/smc/smd_4.dra
Reading...parameter_header:
Reading...db_common_type:

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