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XerolySkinner
2024-03-29 00:52:04 +08:00
parent a3539ac381
commit c8bfe69ca9
37 changed files with 212947 additions and 596 deletions
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13346
3D/CONN-4P-P5.STEP Normal file
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13364
3D/CONN-8P-P5.STEP Normal file
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1361
3D/sod-323.step Normal file
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basic_lib/BASIC_OBJ.OLB
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basic_lib/BASIC_OBJ.OLBlck
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basic_lib/BASIC_OBJ_0.OBK
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other/wh-gm5-1.pad Normal file
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other/wh-gm5-3.pad Normal file
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other/wh-gm5.dra Normal file
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other/wh-gm5.psm Normal file
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smc/sod-323.dra Normal file
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smc/sod-323.pad Normal file
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3454
smc/stepFacetFiles4Map/sod-323.xml Normal file
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1
smc/stepFacetFiles4Map/stepFileInfo.txt
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@@ -6,6 +6,7 @@ SMC.step ! 207133 ! 1710578258
TS-POINT.STEP ! 23849 ! 1710578258
SOD-123FL.step ! 331135 ! 1710578258
ll34.step ! 547277 ! 1711502096
sod-323.step ! 94263 ! 1711640831
LED_0603_G.STEP ! 178570 ! 1710578258
KEY_SOT_P2.step ! 151224 ! 1710578258
RES_CRCW_2512.step ! 33456 ! 1568096060

2
smc/stepFacetFiles4Map/stepFileInfo.txt,1
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@@ -9,5 +9,7 @@ ll34.step ! 547277 ! 1711502096
LED_0603_G.STEP ! 178570 ! 1710578258
KEY_SOT_P2.step ! 151224 ! 1710578258
RES_CRCW_2512.step ! 33456 ! 1568096060
0805.step ! 57849 ! 1568096060
R0603.step ! 652348 ! 1710578258
STL90N10F7.STEP ! 62745 ! 1711513016
C0805.stp ! 348325 ! 1600360029

39
thr/allegro.jrl
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@@ -1,39 +0,0 @@
\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:03) Journal start - Thu Mar 28 17:14:24 2024
\t (00:00:03) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=888 CPUs=12
\t (00:00:03) CmdLine= D:\SOFTWARE\Cadence\SPB_17.4\tools\bin\allegro.exe
\t (00:00:03)
(00:00:03) Loading axlcore.cxt
\t (00:00:06) Opening existing design...
\i (00:00:06) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "thr_conn-th-8p-p5"
\d (00:00:06) Design opened: D:/workspace/GitHub/pcb_lib/thr/thr_conn-th-8p-p5.dra
\t (00:00:06) Grids are drawn 0.4000, 0.4000 apart for enhanced viewing.
\i (00:00:06) trapsize 2548
\i (00:00:06) trapsize 2643
\i (00:00:07) trapsize 2744
\i (00:00:07) trapsize 2643
\t (00:00:07) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:07) trapsize 2318
\i (00:00:07) trapsize 2382
\t (00:00:07) Grids are drawn 0.4000, 0.4000 apart for enhanced viewing.
\i (00:00:07) trapsize 2548
\t (00:00:07) Grids are drawn 0.4000, 0.4000 apart for enhanced viewing.
\i (00:00:07) trapsize 2548
\t (00:00:07) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:07) trapsize 2483
\i (00:00:09) open
\i (00:00:26) fillin "D:/¹¤×÷¿â/Cadence/motor/allegro/motor.brd"
\i (00:00:26) cd "D:/¹¤×÷¿â/Cadence/motor/allegro"
\t (00:00:27) Opening existing design...
\t (00:00:27) Grids are drawn 0.4004, 0.4004 apart for enhanced viewing.
\i (00:00:27) trapsize 4053
\i (00:00:27) trapsize 4153
\t (00:00:28) Grids are drawn 205.0048, 205.0048 apart for enhanced viewing.
\t (00:00:28) Grids are drawn 0.4004, 0.4004 apart for enhanced viewing.
\i (00:00:28) trapsize 4374
\i (00:00:28) setwindow form.mini
\i (00:00:28) FORM mini tree 'Components by refdes'
\i (00:00:28) setwindow pcb
\i (00:00:28) trapsize 4374
\t (00:00:28) > Sending response DoneOpenBoard
\t (00:00:28) Journal end - Thu Mar 28 17:14:49 2024

431
thr/allegro.jrl,1
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@@ -1,431 +0,0 @@
\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:03) Journal start - Thu Mar 28 17:08:09 2024
\t (00:00:03) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=23396 CPUs=12
\t (00:00:03) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\thr\thr_conn-th-8p-p5.dra
\t (00:00:03)
(00:00:03) Loading axlcore.cxt
\t (00:00:06) Opening existing design...
\i (00:00:06) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "thr_conn-th-8p-p5"
\d (00:00:06) Design opened: D:/workspace/GitHub/pcb_lib/thr/thr_conn-th-8p-p5.dra
\t (00:00:06) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:06) trapsize 1340
\i (00:00:06) trapsize 1375
\i (00:00:06) trapsize 1340
\i (00:00:07) trapsize 1175
\i (00:00:07) trapsize 1207
\i (00:00:07) trapsize 1241
\t (00:00:07) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:07) trapsize 1274
\i (00:00:12) delete
\i (00:00:13) drag_start grid -11.3135 5.8502
\i (00:00:17) drag_stop 11.5206 0.8297
\i (00:00:18) pick grid 11.5206 0.8297
\t (00:00:18) last pick: 11.5000 0.8000
\i (00:00:20) add pin
\t (00:00:20) Using 'THR-1R3-2R0.pad'.
\i (00:00:25) setwindow form.mini
\i (00:00:25) FORM mini x_count 4
\i (00:00:29) FORM mini x_spacing 5.0000
\i (00:00:36) setwindow pcb
\i (00:00:36) pick 2.5 0
\t (00:00:36) last pick: 2.5000 0.0000
\t (00:00:37) Using 'THR-1R3-2R0.pad'.
\i (00:00:41) setwindow form.mini
\i (00:00:41) FORM mini x_direction Left
\i (00:00:45) setwindow pcb
\i (00:00:45) pick -2.5 0
\t (00:00:45) last pick: -2.5000 0.0000
\t (00:00:45) Using 'THR-1R3-2R0.pad'.
\i (00:00:47) prepopup 3.5694 4.8308
\i (00:00:48) done
\t (00:00:48) Exiting from Add Pin.
\i (00:00:48) zoom out 1
\i (00:00:48) setwindow pcb
\i (00:00:48) zoom out 2.0149 3.2253
\i (00:00:48) trapsize 2483
\i (00:00:49) zoom in 1
\i (00:00:49) setwindow pcb
\i (00:00:49) zoom in -0.5213 0.7696
\i (00:00:49) trapsize 1241
\i (00:00:49) zoom in 1
\i (00:00:49) setwindow pcb
\i (00:00:49) zoom in -0.5213 0.7696
\i (00:00:49) trapsize 621
\i (00:00:50) zoom out 1
\i (00:00:50) setwindow pcb
\i (00:00:50) zoom out 0.1739 0.1614
\i (00:00:50) trapsize 1241
\i (00:00:50) zoom out 1
\i (00:00:50) setwindow pcb
\i (00:00:50) zoom out 0.1739 0.1613
\i (00:00:51) trapsize 2483
\i (00:00:52) add line
\i (00:00:54) setwindow form.mini
\i (00:00:54) FORM mini subclass SILKSCREEN_TOP
\i (00:00:54) setwindow pcb
\i (00:00:54) updateport CVPane
\i (00:00:56) setwindow form.mini
\i (00:00:56) FORM mini line_width 0.1500
\i (00:01:00) setwindow pcb
\i (00:01:00) pick -5.1 0
\t (00:01:00) last pick: -5.1000 0.0000
\i (00:01:02) prepopup -6.6783 -3.5998
\i (00:01:03) oops
\i (00:01:08) pick 0 -5.1
\t (00:01:08) last pick: 0.0000 -5.1000
\i (00:01:19) ipick -20
\t (00:01:19) last pick: -20.0000 -5.1000
\i (00:01:23) ipick 0 10.65
\t (00:01:23) last pick: -20.0000 5.5500
\i (00:01:27) ipick 40
\t (00:01:27) last pick: 20.0000 5.5500
\i (00:01:30) ipick 0 -10.65
\t (00:01:30) last pick: 20.0000 -5.1000
\i (00:01:32) zoom in 1
\i (00:01:32) setwindow pcb
\i (00:01:32) zoom in -0.8193 -4.3942
\i (00:01:32) trapsize 1241
\i (00:01:32) zoom in 1
\i (00:01:32) setwindow pcb
\i (00:01:32) zoom in -0.8192 -4.3942
\i (00:01:32) trapsize 621
\i (00:01:32) zoom in 1
\i (00:01:32) setwindow pcb
\i (00:01:32) zoom in -0.8192 -4.3942
\i (00:01:32) trapsize 310
\i (00:01:34) pick grid -0.0496 -5.1079
\t (00:01:34) last pick: 0.0000 -5.1000
\i (00:01:35) prepopup -0.0186 -4.2577
\i (00:01:35) done
\i (00:01:36) zoom out 1
\i (00:01:36) setwindow pcb
\i (00:01:36) zoom out -0.1055 -5.0831
\i (00:01:36) trapsize 621
\i (00:01:36) zoom out 1
\i (00:01:36) setwindow pcb
\i (00:01:36) zoom out -0.1054 -5.0831
\i (00:01:36) trapsize 1241
\i (00:01:37) zoom out 1
\i (00:01:37) setwindow pcb
\i (00:01:37) zoom out 1.3345 -2.0792
\i (00:01:37) trapsize 2483
\i (00:01:40) add line
\i (00:01:41) zoom in 1
\i (00:01:41) setwindow pcb
\i (00:01:41) zoom in -19.6872 3.8481
\i (00:01:41) trapsize 1241
\i (00:01:41) zoom in 1
\i (00:01:41) setwindow pcb
\i (00:01:41) zoom in -19.6872 3.8481
\i (00:01:41) trapsize 621
\i (00:01:41) zoom in 1
\i (00:01:41) setwindow pcb
\i (00:01:41) zoom in -19.6872 3.8481
\i (00:01:41) trapsize 310
\i (00:01:43) pick grid -19.9913 3.5440
\t (00:01:43) last pick: -20.0000 3.5000
\i (00:01:43) zoom out 1
\i (00:01:43) setwindow pcb
\i (00:01:43) zoom out -18.4273 3.0040
\i (00:01:43) trapsize 621
\i (00:01:43) zoom out 1
\i (00:01:43) setwindow pcb
\i (00:01:43) zoom out -18.4272 3.0040
\i (00:01:43) trapsize 1241
\i (00:01:44) zoom out 1
\i (00:01:44) setwindow pcb
\i (00:01:44) zoom out -17.3039 3.0041
\i (00:01:44) trapsize 2483
\i (00:01:45) zoom in 1
\i (00:01:45) setwindow pcb
\i (00:01:45) zoom in 19.3893 4.1460
\i (00:01:45) trapsize 1241
\i (00:01:45) zoom in 1
\i (00:01:45) setwindow pcb
\i (00:01:45) zoom in 11.0228 4.1460
\i (00:01:45) trapsize 621
\i (00:01:45) zoom in 1
\i (00:01:45) setwindow pcb
\i (00:01:45) zoom in 11.0228 4.1460
\i (00:01:45) trapsize 310
\i (00:01:45) zoom out 1
\i (00:01:45) setwindow pcb
\i (00:01:45) zoom out 10.7063 3.4447
\i (00:01:45) trapsize 621
\i (00:01:45) zoom out 1
\i (00:01:45) setwindow pcb
\i (00:01:45) zoom out 10.7064 3.4447
\i (00:01:45) trapsize 1241
\i (00:01:46) zoom in 1
\i (00:01:46) setwindow pcb
\i (00:01:46) zoom in 20.6802 3.5440
\i (00:01:46) trapsize 621
\i (00:01:47) zoom in 1
\i (00:01:47) setwindow pcb
\i (00:01:47) zoom in 20.6802 3.5441
\i (00:01:47) trapsize 310
\i (00:01:48) pick grid 20.0471 3.4696
\t (00:01:48) last pick: 20.0000 3.5000
\i (00:01:50) next
\i (00:01:51) pick grid 20.0347 4.5496
\t (00:01:51) last pick: 20.0000 4.5000
\i (00:01:51) zoom out 1
\i (00:01:51) setwindow pcb
\i (00:01:51) zoom out 20.7236 4.4130
\i (00:01:51) trapsize 621
\i (00:01:51) zoom out 1
\i (00:01:51) setwindow pcb
\i (00:01:51) zoom out 20.7237 4.4131
\i (00:01:51) trapsize 1241
\i (00:01:52) zoom out 1
\i (00:01:52) setwindow pcb
\i (00:01:52) zoom out 4.8349 8.3108
\i (00:01:52) trapsize 2483
\i (00:01:52) zoom out 1
\i (00:01:52) setwindow pcb
\i (00:01:52) zoom out 7.2741 13.4806
\i (00:01:52) trapsize 2483
\i (00:01:52) zoom out 1
\i (00:01:52) setwindow pcb
\i (00:01:52) zoom out 7.2741 13.4806
\i (00:01:52) trapsize 2483
\i (00:01:53) zoom in 1
\i (00:01:53) setwindow pcb
\i (00:01:53) zoom in -21.0775 5.2880
\i (00:01:53) trapsize 1241
\i (00:01:53) zoom in 1
\i (00:01:53) setwindow pcb
\i (00:01:53) zoom in -21.0774 5.2880
\i (00:01:53) trapsize 621
\i (00:01:53) zoom in 1
\i (00:01:53) setwindow pcb
\i (00:01:53) zoom in -21.0774 5.2880
\i (00:01:53) trapsize 310
\i (00:01:55) pick grid -20.0099 4.5494
\t (00:01:55) last pick: -20.0000 4.5000
\i (00:01:55) prepopup -19.5506 4.6611
\i (00:01:56) done
\i (00:01:56) zoom out 1
\i (00:01:56) setwindow pcb
\i (00:01:56) zoom out -19.3830 5.2942
\i (00:01:56) trapsize 621
\i (00:01:56) zoom out 1
\i (00:01:56) setwindow pcb
\i (00:01:56) zoom out -19.3830 5.2942
\i (00:01:56) trapsize 1241
\i (00:01:56) zoom out 1
\i (00:01:56) setwindow pcb
\i (00:01:56) zoom out -16.2612 5.2942
\i (00:01:56) trapsize 2483
\i (00:01:56) zoom out 1
\i (00:01:56) setwindow pcb
\i (00:01:56) zoom out -7.5223 5.3376
\i (00:01:56) trapsize 2483
\i (00:02:00) shape add rect
\i (00:02:03) setwindow form.mini
\i (00:02:03) FORM mini subclass PLACE_BOUND_TOP
\i (00:02:03) setwindow pcb
\i (00:02:03) updateport CVPane
\i (00:02:05) zoom in 1
\i (00:02:05) setwindow pcb
\i (00:02:05) zoom in -20.3327 5.8342
\i (00:02:05) trapsize 1241
\i (00:02:05) zoom in 1
\i (00:02:05) setwindow pcb
\i (00:02:05) zoom in -20.3326 5.8342
\i (00:02:05) trapsize 621
\i (00:02:05) zoom in 1
\i (00:02:05) setwindow pcb
\i (00:02:05) zoom in -20.3326 5.8342
\i (00:02:05) trapsize 310
\i (00:02:07) pick grid -20.1216 5.6977
\t (00:02:07) last pick: -20.1000 5.7000
\i (00:02:07) zoom out 1
\i (00:02:07) setwindow pcb
\i (00:02:07) zoom out -19.5195 5.6481
\i (00:02:07) trapsize 621
\i (00:02:07) zoom out 1
\i (00:02:07) setwindow pcb
\i (00:02:07) zoom out -19.5196 5.6480
\i (00:02:07) trapsize 1241
\i (00:02:07) zoom out 1
\i (00:02:07) setwindow pcb
\i (00:02:07) zoom out -19.4141 5.6481
\i (00:02:07) trapsize 2483
\i (00:02:08) zoom in 1
\i (00:02:08) setwindow pcb
\i (00:02:08) zoom in 18.6445 -5.9335
\i (00:02:08) trapsize 1241
\i (00:02:08) zoom in 1
\i (00:02:08) setwindow pcb
\i (00:02:08) zoom in 10.6504 -5.9334
\i (00:02:08) trapsize 621
\i (00:02:08) zoom in 1
\i (00:02:08) setwindow pcb
\i (00:02:08) zoom in 10.6504 -5.9334
\i (00:02:08) trapsize 310
\i (00:02:08) zoom in 1
\i (00:02:08) setwindow pcb
\i (00:02:08) zoom in 10.6504 -5.9334
\i (00:02:08) trapsize 155
\i (00:02:09) zoom out 1
\i (00:02:09) setwindow pcb
\i (00:02:09) zoom out 10.8150 -5.9613
\i (00:02:09) trapsize 310
\i (00:02:09) zoom out 1
\i (00:02:09) setwindow pcb
\i (00:02:09) zoom out 10.8149 -5.9612
\i (00:02:09) trapsize 621
\i (00:02:10) zoom out 1
\i (00:02:10) setwindow pcb
\i (00:02:10) zoom out 10.4674 -6.3337
\i (00:02:10) trapsize 1241
\i (00:02:11) zoom in 1
\i (00:02:11) setwindow pcb
\i (00:02:11) zoom in 21.1925 -5.9364
\i (00:02:11) trapsize 621
\i (00:02:11) zoom in 1
\i (00:02:11) setwindow pcb
\i (00:02:11) zoom in 21.1925 -5.9363
\i (00:02:11) trapsize 310
\i (00:02:12) pick grid 20.0567 -5.1605
\t (00:02:12) last pick: 20.1000 -5.2000
\i (00:02:12) prepopup 20.7705 -5.8618
\i (00:02:13) done
\i (00:02:13) zoom out 1
\i (00:02:13) setwindow pcb
\i (00:02:13) zoom out 20.7891 -6.6190
\i (00:02:13) trapsize 621
\i (00:02:13) zoom out 1
\i (00:02:13) setwindow pcb
\i (00:02:13) zoom out 20.7890 -6.6191
\i (00:02:13) trapsize 1241
\i (00:02:13) zoom out 1
\i (00:02:13) setwindow pcb
\i (00:02:13) zoom out 20.3823 -6.6191
\i (00:02:13) trapsize 2483
\i (00:02:17) add rect
\i (00:02:19) setwindow form.mini
\i (00:02:19) FORM mini subclass ASSEMBLY_TOP
\i (00:02:19) setwindow pcb
\i (00:02:19) updateport CVPane
\i (00:02:20) zoom in 1
\i (00:02:20) setwindow pcb
\i (00:02:20) zoom in -19.7368 5.4369
\i (00:02:20) trapsize 1241
\i (00:02:20) zoom in 1
\i (00:02:20) setwindow pcb
\i (00:02:20) zoom in -19.7368 5.4370
\i (00:02:20) trapsize 621
\i (00:02:22) pick grid -20.1092 5.6977
\t (00:02:22) last pick: -20.1000 5.7000
\i (00:02:22) zoom out 1
\i (00:02:22) setwindow pcb
\i (00:02:22) zoom out -17.5893 5.5860
\i (00:02:22) trapsize 1241
\i (00:02:23) zoom out 1
\i (00:02:23) setwindow pcb
\i (00:02:23) zoom out -6.4672 -0.1985
\i (00:02:23) trapsize 2483
\i (00:02:24) zoom in 1
\i (00:02:24) setwindow pcb
\i (00:02:24) zoom in 21.9712 -5.9831
\i (00:02:24) trapsize 1241
\i (00:02:24) zoom in 1
\i (00:02:24) setwindow pcb
\i (00:02:24) zoom in 12.3138 -5.9831
\i (00:02:24) trapsize 621
\i (00:02:24) zoom in 1
\i (00:02:24) setwindow pcb
\i (00:02:24) zoom in 12.3138 -5.9831
\i (00:02:24) trapsize 310
\i (00:02:25) zoom out 1
\i (00:02:25) setwindow pcb
\i (00:02:25) zoom out 11.0911 -6.3493
\i (00:02:25) trapsize 621
\i (00:02:25) zoom out 1
\i (00:02:25) setwindow pcb
\i (00:02:25) zoom out 11.0911 -6.3493
\i (00:02:25) trapsize 1241
\i (00:02:26) zoom in 1
\i (00:02:26) setwindow pcb
\i (00:02:26) zoom in 20.5065 -5.0086
\i (00:02:26) trapsize 621
\i (00:02:26) zoom in 1
\i (00:02:26) setwindow pcb
\i (00:02:26) zoom in 20.5065 -5.0085
\i (00:02:26) trapsize 310
\i (00:02:27) pick grid 20.1465 -5.1885
\t (00:02:27) last pick: 20.1000 -5.2000
\i (00:02:27) prepopup 20.4507 -5.1327
\i (00:02:28) done
\i (00:02:28) zoom out 1
\i (00:02:28) setwindow pcb
\i (00:02:28) zoom out 20.3762 -5.9519
\i (00:02:28) trapsize 621
\i (00:02:28) zoom out 1
\i (00:02:28) setwindow pcb
\i (00:02:28) zoom out 20.3763 -5.9519
\i (00:02:28) trapsize 1241
\i (00:02:28) zoom out 1
\i (00:02:28) setwindow pcb
\i (00:02:28) zoom out 19.9851 -5.9520
\i (00:02:28) trapsize 2483
\i (00:02:31) text edit
\i (00:02:32) pick grid -17.7011 -1.2165
\t (00:02:32) last pick: -17.7000 -1.2000
\i (00:02:35) setwindow pcb
\i (00:02:35) pick grid -12.7358 -1.2165
\t (00:02:35) last pick: -12.7000 -1.2000
\i (00:02:35) setwindow pcb
\i (00:02:35) pick -17.7011 -1.2165
\t (00:02:35) Pick text to edit.
\i (00:02:39) setwindow pcb
\i (00:02:39) pick grid -7.7210 -1.2165
\t (00:02:39) last pick: -7.7000 -1.2000
\i (00:02:39) setwindow pcb
\i (00:02:39) pick -12.7358 -1.2165
\t (00:02:39) Pick text to edit.
\i (00:02:40) setwindow pcb
\i (00:02:40) pick grid -2.7557 -1.3654
\t (00:02:40) last pick: -2.8000 -1.4000
\i (00:02:40) setwindow pcb
\i (00:02:40) pick -7.7210 -1.2165
\t (00:02:40) Pick text to edit.
\i (00:02:42) setwindow pcb
\i (00:02:42) pick grid 2.3585 -1.2165
\t (00:02:42) last pick: 2.4000 -1.2000
\i (00:02:42) setwindow pcb
\i (00:02:42) pick -2.7557 -1.3654
\t (00:02:42) Pick text to edit.
\i (00:02:43) setwindow pcb
\i (00:02:43) pick grid 7.4727 -1.3654
\t (00:02:43) last pick: 7.5000 -1.4000
\i (00:02:43) setwindow pcb
\i (00:02:43) pick 2.3585 -1.2165
\t (00:02:43) Pick text to edit.
\i (00:02:44) setwindow pcb
\i (00:02:44) pick grid 12.2393 -1.5640
\t (00:02:44) last pick: 12.2000 -1.6000
\i (00:02:44) setwindow pcb
\i (00:02:44) pick 7.4727 -1.3654
\t (00:02:44) Pick text to edit.
\i (00:02:45) setwindow pcb
\i (00:02:45) pick grid 17.4032 -1.5144
\t (00:02:45) last pick: 17.4000 -1.5000
\i (00:02:45) setwindow pcb
\i (00:02:45) pick 12.2393 -1.5640
\t (00:02:45) Pick text to edit.
\i (00:02:46) setwindow pcb
\i (00:02:46) pick grid 19.6872 -9.5084
\t (00:02:46) last pick: 19.7000 -9.5000
\i (00:02:46) setwindow pcb
\i (00:02:46) pick 17.4032 -1.5144
\t (00:02:46) Pick text to edit.
\e (00:02:46) ERROR(SPMHA1-441): Text not found.
\i (00:02:48) setwindow pcb
\i (00:02:48) save
\i (00:02:48) fillin yes
\t (00:02:48) Symbol 'thr_conn-th-8p-p5.psm' created.
\i (00:02:53) exit
\t (00:02:53) Journal end - Thu Mar 28 17:10:59 2024

14
thr/downrev.log
View File

@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : thr_conn-th-8p-p5.dra )
( Software Version : 17.4S035 )
( Date/Time : Thu Mar 28 17:10:54 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
thr/downrev.log,1
View File

@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : thr_conn-th-4p-p5.dra )
( Software Version : 17.4S035 )
( Date/Time : Thu Mar 28 17:07:33 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
thr/downrev.log,2
View File

@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : thr_conn-th-8p-p5.dra )
( Software Version : 17.4S035 )
( Date/Time : Thu Mar 28 17:10:54 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
thr/downrev.log,3
View File

@@ -1,14 +0,0 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : thr_conn-th-8p-p5.dra )
( Software Version : 17.4S035 )
( Date/Time : Thu Mar 28 17:10:54 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

1
thr/master.tag
View File

@@ -1 +0,0 @@
thr_conn-th-8p-p5.dra

60465
thr/stepFacetFiles4Map/CONN-2P-P5.xml Normal file
View File

File diff suppressed because it is too large Load Diff

60473
thr/stepFacetFiles4Map/CONN-4P-P5.xml Normal file
View File

File diff suppressed because it is too large Load Diff

60475
thr/stepFacetFiles4Map/CONN-8P-P5.xml Normal file
View File

File diff suppressed because it is too large Load Diff

3
thr/stepFacetFiles4Map/stepFileInfo.txt
View File

@@ -1,4 +1,7 @@
#STEP_FILE ! FILE_SIZE ! MOD_TIME
CONN-4P-P5.STEP ! 1114691 ! 1711644010
thr-3r090tb.step ! 2404583 ! 1711452688
DIP_2x5.step ! 720870 ! 1710578258
CONN-2P-P5.step ! 1193777 ! 1710578258
CONN-8P-P5.STEP ! 1116390 ! 1711644114

3
thr/stepFacetFiles4Map/stepFileInfo.txt,1
View File

@@ -1,3 +1,6 @@
#STEP_FILE ! FILE_SIZE ! MOD_TIME
CONN-4P-P5.STEP ! 1114691 ! 1711644010
thr-3r090tb.step ! 2404583 ! 1711452688
DIP_2x5.step ! 720870 ! 1710578258
CONN-2P-P5.step ! 1193777 ! 1710578258

BIN
thr/thr_conn-th-4p-p5.dra
View File

Binary file not shown.

23
thr/thr_conn-th-4p-p5.log
View File

@@ -1,23 +0,0 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : thr_conn-th-4p-p5.dra )
( Software Version : 17.4S035 )
( Date/Time : Thu Mar 28 17:07:33 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/thr
Name = thr_conn-th-4p-p5.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
thr/thr_conn-th-4p-p5.log,1
View File

@@ -1,23 +0,0 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : thr_conn-th-4p-p5.dra )
( Software Version : 17.4S035 )
( Date/Time : Thu Mar 28 17:07:24 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/thr
Name = thr_conn-th-4p-p5.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
thr/thr_conn-th-4p-p5.psm
View File

Binary file not shown.

BIN
thr/thr_conn-th-8p-p5.dra
View File

Binary file not shown.

23
thr/thr_conn-th-8p-p5.log
View File

@@ -1,23 +0,0 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : thr_conn-th-8p-p5.dra )
( Software Version : 17.4S035 )
( Date/Time : Thu Mar 28 17:10:54 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/thr
Name = thr_conn-th-8p-p5.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
thr/thr_conn-th-8p-p5.psm
View File

Binary file not shown.