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XerolySkinner
2024-08-03 22:47:13 +08:00
parent 79562d2813
commit dce0e46eed
130 changed files with 353796 additions and 33262 deletions
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chip/STEP_Device_Package_Mapping_Report.html Normal file
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html>
<head><title>3D Model Mapping Report</title></head>
<body>
<b><u>Design Name</u>&nbsp;D:/workspace/GitHub/pcb_lib/chip/ssop-4.dra</b><br>
<b><u>Date</u>&nbsp;Sat Aug 3 22:08:36 2024</b><br>
<br>
<table align=center border=1><caption><b><u>3D Model Mapping Report (UNITS: MM)</u></b></caption>
<tr>
<td><b>PART_NUMBER</b></td>
<td><b>DEVICE</b></td>
<td><b>PACKAGE</b></td>
<td><b>PRI/SEC</b></td>
<td><b>MODEL</b></td>
<td><b>ROTATION_X</b></td>
<td><b>ROTATION_Y</b></td>
<td><b>ROTATION_Z</b></td>
<td><b>OFFSET_X</b></td>
<td><b>OFFSET_Y</b></td>
<td><b>OFFSET_Z</b></td>
</tr>
<tr>
<td>&nbsp;</td>
<td>&nbsp;</td>
<td nowrap=true>ssop-4</td>
<td nowrap=true>Primary</td>
<td nowrap=true>ssop-4.STEP</td>
<td nowrap=true align=right>0.000</td>
<td nowrap=true align=right>0.000</td>
<td nowrap=true align=right>90.000</td>
<td nowrap=true align=right>0.000</td>
<td nowrap=true align=right>0.000</td>
<td nowrap=true align=right>0.000</td>
</tr>
</table>
</body>
</html>

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chip/allegro.jrl
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@@ -1,80 +1,385 @@
\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Mon Jul 29 04:50:28 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=13504 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\chip\lqfp64.dra
\t (00:00:02) Journal start - Sat Aug 3 22:01:08 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=12692 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\chip\ssop-4.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged lqfp64
\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/chip/lqfp64.dra
\t (00:00:02) Grids are drawn 0.200, 0.200 apart for enhanced viewing.
\i (00:00:02) trapsize 135
\i (00:00:02) trapsize 139
\i (00:00:02) trapsize 135
\i (00:00:03) trapsize 118
\i (00:00:03) trapsize 122
\i (00:00:03) trapsize 125
\t (00:00:03) Grids are drawn 0.200, 0.200 apart for enhanced viewing.
\i (00:00:03) trapsize 128
\i (00:00:06) delete
\i (00:00:08) pick grid 0.029 2.342
\t (00:00:08) last pick: 0.000 2.300
\t (00:00:08) Shape "Package Geometry/Silkscreen_Top"
\i (00:00:08) prepopup 7.913 10.740
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "ssop-4"
\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/chip/ssop-4.dra
\i (00:00:02) trapsize 106
\i (00:00:02) trapsize 109
\i (00:00:02) trapsize 106
\i (00:00:02) trapsize 93
\i (00:00:03) trapsize 95
\i (00:00:03) trapsize 98
\i (00:00:03) trapsize 98
\i (00:00:05) delete
\i (00:00:06) drag_start grid -5.518 4.094
\i (00:00:07) drag_stop 4.838 -4.300
\i (00:00:07) pick grid 4.838 -4.300
\t (00:00:07) last pick: 4.800 -4.300
\i (00:00:08) prepopup -0.105 -0.358
\i (00:00:09) done
\i (00:00:14) shape add rect
\i (00:00:16) pick 0 0
\t (00:00:16) last pick: 0.000 0.000
\i (00:00:18) zoom in 1
\i (00:00:18) setwindow pcb
\i (00:00:18) zoom in -5.004 5.424
\i (00:00:18) trapsize 64
\i (00:00:18) zoom in 1
\i (00:00:18) setwindow pcb
\i (00:00:18) zoom in -5.004 5.424
\i (00:00:18) trapsize 32
\i (00:00:18) zoom in 1
\i (00:00:18) setwindow pcb
\i (00:00:18) zoom in -5.004 5.424
\i (00:00:18) trapsize 16
\i (00:00:18) zoom in 1
\i (00:00:18) setwindow pcb
\i (00:00:18) zoom in -5.004 5.425
\i (00:00:18) trapsize 8
\i (00:00:18) zoom in 1
\i (00:00:18) setwindow pcb
\i (00:00:18) zoom in -5.004 5.425
\i (00:00:18) trapsize 4
\i (00:00:19) pick grid -4.991 5.049
\t (00:00:19) last pick: -5.000 5.000
\i (00:00:19) zoom out 1
\i (00:00:19) setwindow pcb
\i (00:00:19) zoom out -4.944 5.410
\i (00:00:19) trapsize 8
\i (00:00:19) zoom out 1
\i (00:00:19) setwindow pcb
\i (00:00:19) zoom out -4.945 5.409
\i (00:00:19) trapsize 16
\i (00:00:19) zoom out 1
\i (00:00:19) setwindow pcb
\i (00:00:19) zoom out -4.945 5.409
\i (00:00:19) trapsize 32
\i (00:00:19) zoom out 1
\i (00:00:19) setwindow pcb
\i (00:00:19) zoom out -4.944 5.410
\i (00:00:19) trapsize 64
\i (00:00:20) prepopup -4.945 5.411
\i (00:00:21) done
\i (00:00:22) delete
\i (00:00:23) pick grid -4.689 4.679
\t (00:00:23) last pick: -4.700 4.700
\t (00:00:23) Line "Package Geometry/Silkscreen_Top"
\i (00:00:24) pick grid -7.886 5.244
\t (00:00:24) last pick: -7.900 5.200
\i (00:00:24) prepopup -7.886 5.244
\i (00:00:25) done
\i (00:00:26) save
\i (00:00:26) fillin yes
\t (00:00:26) Symbol 'lqfp64.psm' created.
\i (00:00:27) exit
\t (00:00:28) Journal end - Mon Jul 29 04:50:54 2024
\i (00:00:12) param in
\i (00:00:13) setwindow form.parm_in
\i (00:00:13) FORM parm_in browse
\i (00:00:15) fillin "D:/workspace/GitHub/pcb_lib/XerolySkinner.prm"
\i (00:00:16) FORM parm_in execute
\t (00:00:16) Starting Importing parameter file...
\w (00:00:17) WARNING(SPMHGE-269): param in had warnings, use Viewlog to review the log file.
\t (00:00:17) Opening existing design...
\i (00:00:17) setwindow pcb
\i (00:00:17) trapsize 98
\i (00:00:17) trapsize 100
\i (00:00:17) trapsize 98
\t (00:00:17) Grids are drawn 51.200, 51.200 apart for enhanced viewing.
\i (00:00:17) trapsize 98
\i (00:00:19) setwindow text
\i (00:00:19) close
\i (00:00:20) setwindow form.parm_in
\i (00:00:20) FORM parm_in cancel
\i (00:00:21) setwindow pcb
\i (00:00:21) zoom out 1
\i (00:00:21) setwindow pcb
\i (00:00:21) zoom out 0.091 -0.142
\i (00:00:21) trapsize 98
\i (00:00:21) zoom out 1
\i (00:00:21) setwindow pcb
\i (00:00:21) zoom out 0.091 -0.142
\i (00:00:21) trapsize 98
\i (00:00:21) zoom out 1
\i (00:00:21) setwindow pcb
\i (00:00:21) zoom out 0.091 -0.142
\i (00:00:21) trapsize 98
\i (00:00:22) add pin
\i (00:00:29) setwindow form.mini
\i (00:00:29) FORM mini pad_name ssop-4
\w (00:00:29) WARNING(SPMHUT-48): Scaled value has been rounded off.
\t (00:00:29) Using 'SSOP-4.pad'.
\i (00:00:31) setwindow pcb
\i (00:00:31) zoom out 1
\i (00:00:31) setwindow pcb
\i (00:00:31) zoom out 0.444 0.054
\i (00:00:31) trapsize 98
\i (00:00:31) zoom out 1
\i (00:00:31) setwindow pcb
\i (00:00:31) zoom out 0.444 0.054
\i (00:00:31) trapsize 98
\i (00:00:31) zoom out 1
\i (00:00:31) setwindow pcb
\i (00:00:31) zoom out 0.444 0.054
\i (00:00:31) trapsize 98
\i (00:00:31) zoom in 1
\i (00:00:31) setwindow pcb
\i (00:00:31) zoom in 0.444 0.054
\i (00:00:31) trapsize 49
\i (00:00:31) zoom in 1
\i (00:00:31) setwindow pcb
\i (00:00:31) zoom in 0.444 0.054
\i (00:00:31) trapsize 25
\i (00:00:32) zoom in 1
\i (00:00:32) setwindow pcb
\i (00:00:32) zoom in 0.444 0.055
\i (00:00:32) trapsize 12
\i (00:00:32) zoom in 1
\i (00:00:32) setwindow pcb
\i (00:00:32) zoom in 0.444 0.055
\i (00:00:32) trapsize 6
\i (00:00:32) zoom out 1
\i (00:00:32) setwindow pcb
\i (00:00:32) zoom out 0.444 0.055
\i (00:00:32) trapsize 12
\i (00:00:32) zoom out 1
\i (00:00:32) setwindow pcb
\i (00:00:32) zoom out 0.444 0.056
\i (00:00:32) trapsize 25
\i (00:00:42) setwindow form.mini
\i (00:00:42) FORM mini x_count 2
\i (00:00:45) FORM mini x_spacing 1.270
\i (00:00:47) FORM mini y_count 2
\i (00:00:48) FORM mini y_spacing 1.270
\i (00:00:53) FORM mini rotate_pin 0.000
\t (00:00:53) Using 'SSOP-4.pad'.
\i (00:01:08) FORM mini x_spacing 6.500
\i (00:01:30) setwindow pcb
\i (00:01:30) pick -3.25 -0.635
\t (00:01:30) last pick: -3.250 -0.635
\t (00:01:30) Using 'SSOP-4.pad'.
\i (00:01:32) prepopup 2.425 0.370
\i (00:01:33) oops
\t (00:01:33) Using 'SSOP-4.pad'.
\i (00:01:35) setwindow form.mini
\i (00:01:35) FORM mini y_direction Up
\i (00:01:38) FORM mini next_pin_number 1
\i (00:01:39) FORM mini text_name pin
\i (00:01:51) setwindow pcb
\i (00:01:51) pick -3.25 -0.635
\t (00:01:51) last pick: -3.250 -0.635
\t (00:01:51) Using 'SSOP-4.pad'.
\i (00:01:52) zoom out 1
\i (00:01:52) setwindow pcb
\i (00:01:52) zoom out 0.547 -1.155
\i (00:01:52) trapsize 49
\i (00:01:52) zoom out 1
\i (00:01:52) setwindow pcb
\i (00:01:52) zoom out 0.547 -1.156
\i (00:01:52) trapsize 98
\i (00:01:52) zoom out 1
\i (00:01:52) setwindow pcb
\i (00:01:52) zoom out 0.856 -4.790
\i (00:01:52) trapsize 98
\i (00:01:53) zoom in 1
\i (00:01:53) setwindow pcb
\i (00:01:53) zoom in -0.026 0.211
\i (00:01:53) trapsize 49
\i (00:01:53) zoom in 1
\i (00:01:53) setwindow pcb
\i (00:01:53) zoom in -0.026 0.212
\i (00:01:53) trapsize 25
\i (00:01:53) zoom in 1
\i (00:01:53) setwindow pcb
\i (00:01:53) zoom in -0.027 0.212
\i (00:01:53) trapsize 12
\i (00:01:54) zoom out 1
\i (00:01:54) setwindow pcb
\i (00:01:54) zoom out 0.024 -0.511
\i (00:01:54) trapsize 25
\i (00:01:54) zoom out 1
\i (00:01:54) setwindow pcb
\i (00:01:54) zoom out 0.025 -0.510
\i (00:01:54) trapsize 49
\i (00:01:54) prepopup 0.026 -0.511
\i (00:01:55) done
\t (00:01:55) Exiting from Add Pin.
\i (00:02:13) text edit
\i (00:02:15) pick grid -3.378 1.000
\t (00:02:15) last pick: -3.400 1.000
\i (00:02:16) setwindow pcb
\i (00:02:16) pick grid -3.358 -0.383
\t (00:02:16) last pick: -3.400 -0.400
\i (00:02:16) setwindow pcb
\i (00:02:16) pick -3.378 1.000
\t (00:02:16) Pick text to edit.
\i (00:02:19) setwindow pcb
\i (00:02:19) pick grid 3.145 -0.472
\t (00:02:19) last pick: 3.100 -0.500
\i (00:02:19) setwindow pcb
\i (00:02:19) pick -3.358 -0.383
\t (00:02:19) Pick text to edit.
\i (00:02:20) setwindow pcb
\i (00:02:20) pick grid 3.164 0.901
\t (00:02:20) last pick: 3.200 0.900
\i (00:02:20) setwindow pcb
\i (00:02:20) pick 3.145 -0.472
\t (00:02:20) Pick text to edit.
\i (00:02:21) setwindow pcb
\i (00:02:21) prepopup 4.106 1.500
\i (00:02:22) done
\i (00:02:22) setwindow pcb
\i (00:02:22) pick 3.164 0.901
\i (00:02:25) setwindow pcb
\i (00:02:25) add rect
\i (00:02:34) add rect
\i (00:02:37) setwindow form.mini
\i (00:02:37) FORM mini class 'PACKAGE GEOMETRY'
\i (00:03:07) setwindow pcb
\i (00:03:07) pick -2. 2 -1.35
\t (00:03:07) last pick: -2.000 2.000
\i (00:03:23) pick 2.2 -1.35
\t (00:03:23) last pick: 2.200 -1.350
\i (00:03:32) prepopup 3.753 2.696
\i (00:03:33) oops
\t (00:03:33) last pick: -2.000 2.000
\i (00:03:33) prepopup 2.605 2.628
\i (00:03:34) oops
\i (00:03:38) pick -2.2 1.25
\t (00:03:38) last pick: -2.200 1.250
\i (00:03:47) prepopup 2.782 1.313
\i (00:03:48) oops
\i (00:03:52) add rect
\i (00:03:56) pick x -2.2 1.35
\t (00:03:56) last pick: -2.200 1.350
\i (00:04:00) pick 2.2 -1.35
\t (00:04:00) last pick: 2.200 -1.350
\i (00:04:01) pick grid 1.399 3.079
\t (00:04:01) last pick: 1.400 3.100
\i (00:04:01) prepopup 1.879 2.883
\i (00:04:03) oops
\t (00:04:03) last pick: 2.200 -1.350
\i (00:04:03) prepopup 0.408 2.873
\i (00:04:04) done
\i (00:04:08) shape add rect
\i (00:04:11) setwindow form.mini
\i (00:04:11) FORM mini subclass PLACE_BOUND_TOP
\i (00:04:11) setwindow pcb
\i (00:04:11) updateport CVPane
\i (00:04:12) zoom in 1
\i (00:04:12) setwindow pcb
\i (00:04:12) zoom in -0.474 0.774
\i (00:04:12) trapsize 25
\i (00:04:12) zoom in 1
\i (00:04:12) setwindow pcb
\i (00:04:12) zoom in -0.474 0.774
\i (00:04:12) trapsize 12
\i (00:04:12) zoom out 1
\i (00:04:12) setwindow pcb
\i (00:04:12) zoom out -0.474 0.774
\i (00:04:12) trapsize 25
\i (00:04:12) zoom out 1
\i (00:04:12) setwindow pcb
\i (00:04:12) zoom out -0.473 0.775
\i (00:04:12) trapsize 49
\i (00:04:15) pick grid -3.601 1.422
\t (00:04:15) last pick: -3.600 1.400
\i (00:04:19) pick grid 3.559 -1.383
\t (00:04:19) last pick: 3.600 -1.400
\i (00:04:19) prepopup 4.265 1.766
\i (00:04:20) done
\i (00:04:24) add rect
\i (00:04:27) add line
\i (00:04:34) setwindow form.mini
\i (00:04:34) FORM mini subclass SILKSCREEN_TOP
\i (00:04:34) setwindow pcb
\i (00:04:34) updateport CVPane
\i (00:04:36) setwindow form.mini
\i (00:04:36) FORM mini line_width 0.150
\i (00:04:40) setwindow pcb
\i (00:04:40) pick 2.2 1.35
\t (00:04:40) last pick: 2.200 1.350
\i (00:04:45) ipick -4.4
\t (00:04:45) last pick: -2.200 1.350
\i (00:04:48) ipick 0 -2.7
\t (00:04:48) last pick: -2.200 -1.350
\i (00:04:50) ipick 4.4
\t (00:04:50) last pick: 2.200 -1.350
\i (00:04:52) ipick 0 2.7
\t (00:04:52) last pick: 2.200 1.350
\i (00:04:53) prepopup 0.783 2.629
\i (00:04:54) done
\i (00:04:57) shape add rect
\i (00:04:59) pick 0 0
\t (00:04:59) last pick: 0.000 0.000
\i (00:05:06) pick -1.1 1.35
\t (00:05:06) last pick: -1.100 1.350
\i (00:05:07) prepopup 2.980 2.844
\i (00:05:08) oops
\t (00:05:08) last pick: 0.000 0.000
\i (00:05:14) pick -2.2 1.35
\t (00:05:14) last pick: -2.200 1.350
\i (00:05:15) prepopup -0.149 2.913
\i (00:05:15) done
\i (00:05:16) save
\i (00:05:16) fillin yes
\e (00:05:17) ERROR(SPMHGE-7): Error(s) occurred, check logfile.
\i (00:05:18) setwindow text
\i (00:05:18) close
\i (00:05:19) setwindow pcb
\i (00:05:19) label refdes
\t (00:05:19) Pick text location.
\i (00:05:23) setwindow form.mini
\i (00:05:23) FORM mini text_name asm
\i (00:05:24) setwindow pcb
\i (00:05:24) pick 0 0
\t (00:05:24) last pick: 0.000 0.000
\t (00:05:24) Enter text string.
\i (00:05:25) setwindow pcb
\i (00:05:25) pick 0.000 0.000
\i (00:05:26) setwindow pcb
\i (00:05:26) prepopup 4.078 3.158
\i (00:05:27) done
\i (00:05:28) label refdes
\t (00:05:28) Pick text location.
\i (00:05:30) setwindow form.mini
\i (00:05:30) FORM mini subclass SILKSCREEN_TOP
\i (00:05:30) setwindow pcb
\i (00:05:30) updateport CVPane
\i (00:05:34) setwindow form.mini
\i (00:05:34) FORM mini text_name ski
\i (00:05:36) setwindow pcb
\i (00:05:36) pick grid 0.459 -1.098
\t (00:05:36) last pick: 0.500 -1.100
\t (00:05:36) Enter text string.
\i (00:05:37) setwindow pcb
\i (00:05:37) pick 0.500 -1.100
\i (00:05:38) prepopup 0.459 -1.098
\i (00:05:38) done
\i (00:05:41) step pkg map
\i (00:05:42) fillin yes
\i (00:05:51) setwindow form.pkgmap3d
\i (00:05:51) FORM pkgmap3d stplist ssop-4.STEP
\i (00:05:55) FORM pkgmap3d offset_y 90
\i (00:05:56) FORM pkgmap3d offset_y 0
\i (00:05:58) FORM pkgmap3d rotation_y 90
\i (00:05:59) FORM pkgmap3d rotation_y 0
\i (00:05:59) FORM pkgmap3d rotation_x 90
\i (00:06:01) FORM pkgmap3d rotation_x 0
\i (00:06:01) FORM pkgmap3d rotation_z 90
\i (00:06:11) FORM pkgmap3d view_orientation Left
\i (00:06:13) FORM pkgmap3d save_current
\i (00:06:14) FORM pkgmap3d done
\i (00:06:40) setwindow pcb
\i (00:06:40) replace padstack
\i (00:06:41) pick grid -3.307 0.608
\t (00:06:41) last pick: -3.300 0.600
\i (00:06:46) setwindow form.mini
\i (00:06:46) FORM mini newname SSOP-4
\w (00:06:46) WARNING(SPMHUT-48): Scaled value has been rounded off.
\i (00:06:49) FORM mini replace
\t (00:06:49) Done, updated padstack.
\t (00:06:49) 4 out of 4 old padstack SSOP-4 were replaced with new padstack SSOP-4.
\i (00:06:50) setwindow pcb
\i (00:06:50) prepopup 1.048 3.521
\i (00:06:50) done
\t (00:06:50) Performing DRC...
\t (00:06:50) No DRC errors detected.
\i (00:06:51) save
\i (00:06:51) fillin yes
\t (00:06:52) Symbol 'ssop-4.psm' created.
\i (00:06:55) define grid
\t (00:06:55) Spacing fields allow simple equations to aid calculations; prefix with =
\i (00:06:58) setwindow form.grid
\i (00:06:58) FORM grid done
\i (00:07:03) setwindow pcb
\i (00:07:03) shape select
\i (00:07:05) pick grid -3.434 1.432
\t (00:07:05) last pick: -3.400 1.400
\i (00:07:07) drag_start grid -3.542 0.294
\i (00:07:07) drag_stop grid -3.797 0.265
\i (00:07:09) drag_start grid -3.542 0.255
\i (00:07:09) drag_stop grid -3.778 0.294
\i (00:07:12) pick grid -3.552 0.236
\t (00:07:12) last pick: -3.600 0.200
\t (00:07:12) last pick: -3.600 0.236
\i (00:07:12) prepopup -3.552 0.236
\i (00:07:13) prepopup -3.582 0.255
\i (00:07:14) oops
\t (00:07:14) last pick: -3.400 1.400
\i (00:07:15) drag_start grid -3.572 0.265
\t (00:07:15) last pick: -3.600 0.265
\i (00:07:17) drag_stop grid -3.817 0.265
\t (00:07:17) No DRC errors detected.
\i (00:07:19) drag_start grid 3.588 0.294
\t (00:07:19) last pick: 3.600 0.294
\i (00:07:19) drag_stop grid 3.833 0.285
\t (00:07:19) No DRC errors detected.
\i (00:07:20) prepopup 4.304 0.392
\i (00:07:21) done
\i (00:07:21) save
\i (00:07:22) fillin yes
\t (00:07:22) Symbol 'ssop-4.psm' created.
\i (00:07:24) step pkg map
\i (00:07:25) fillin yes
\i (00:07:28) setwindow form.pkgmap3d
\i (00:07:28) FORM pkgmap3d view_orientation Top
\i (00:07:30) FORM pkgmap3d report
\i (00:07:33) setwindow text
\i (00:07:33) close
\i (00:07:34) setwindow form.pkgmap3d
\i (00:07:34) FORM pkgmap3d done
\i (00:07:35) setwindow pcb
\i (00:07:35) save
\i (00:07:36) fillin yes
\t (00:07:36) Symbol 'ssop-4.psm' created.
\i (00:07:47) exit
\t (00:07:48) Journal end - Sat Aug 3 22:08:54 2024

137
chip/allegro.jrl,1
View File

@@ -1,111 +1,34 @@
\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Mon Jul 29 04:48:36 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=18232 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\chip\sop-8.dra
\t (00:00:02) Journal start - Fri Aug 2 06:02:52 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=12676 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\chip\sop-16.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sop-8"
\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/chip/sop-8.dra
\i (00:00:02) trapsize 106
\i (00:00:02) trapsize 109
\i (00:00:03) trapsize 106
\i (00:00:03) trapsize 93
\i (00:00:03) trapsize 95
\i (00:00:03) trapsize 98
\i (00:00:03) trapsize 98
\i (00:00:10) shape add rect
\i (00:00:14) setwindow form.mini
\i (00:00:14) FORM mini class 'PACKAGE GEOMETRY'
\i (00:00:16) FORM mini subclass SILKSCREEN_TOP
\i (00:00:16) setwindow pcb
\i (00:00:16) updateport CVPane
\i (00:00:21) pick 0 0
\t (00:00:21) last pick: 0.000 0.000
\i (00:00:23) zoom in 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom in -0.968 2.055
\i (00:00:23) trapsize 49
\i (00:00:23) zoom in 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom in -0.968 2.055
\i (00:00:23) trapsize 25
\i (00:00:23) zoom in 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom in -0.968 2.056
\i (00:00:23) trapsize 12
\i (00:00:23) zoom in 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom in -0.968 2.056
\i (00:00:23) trapsize 6
\i (00:00:23) zoom out 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom out -1.143 1.793
\i (00:00:23) trapsize 12
\i (00:00:23) zoom out 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom out -1.142 1.793
\i (00:00:23) trapsize 25
\i (00:00:23) zoom out 1
\i (00:00:23) setwindow pcb
\i (00:00:23) zoom out -1.142 1.793
\i (00:00:23) trapsize 49
\i (00:00:24) zoom in 1
\i (00:00:24) setwindow pcb
\i (00:00:24) zoom in -1.398 2.469
\i (00:00:24) trapsize 25
\i (00:00:24) zoom in 1
\i (00:00:24) setwindow pcb
\i (00:00:24) zoom in -1.398 2.469
\i (00:00:24) trapsize 12
\i (00:00:24) zoom in 1
\i (00:00:24) setwindow pcb
\i (00:00:24) zoom in -1.398 2.469
\i (00:00:24) trapsize 6
\i (00:00:26) pick grid -1.469 2.450
\t (00:00:26) last pick: -1.500 2.500
\i (00:00:27) prepopup -1.205 2.640
\i (00:00:28) done
\i (00:00:31) delete
\i (00:00:33) pick grid -1.096 2.170
\t (00:00:33) last pick: -1.100 2.200
\t (00:00:33) Line "Package Geometry/Silkscreen_Top"
\i (00:00:33) prepopup -1.049 2.662
\i (00:00:34) done
\i (00:00:34) zoom out 1
\i (00:00:34) setwindow pcb
\i (00:00:34) zoom out -1.049 2.662
\i (00:00:34) trapsize 12
\i (00:00:34) zoom out 1
\i (00:00:34) setwindow pcb
\i (00:00:34) zoom out -1.050 2.662
\i (00:00:34) trapsize 25
\i (00:00:34) zoom out 1
\i (00:00:34) setwindow pcb
\i (00:00:34) zoom out -1.049 2.662
\i (00:00:35) trapsize 49
\i (00:00:35) zoom out 1
\i (00:00:35) setwindow pcb
\i (00:00:35) zoom out -1.049 2.662
\i (00:00:35) trapsize 98
\i (00:00:35) zoom out 1
\i (00:00:35) setwindow pcb
\i (00:00:35) zoom out 1.288 2.270
\i (00:00:35) trapsize 98
\i (00:00:35) save
\i (00:00:36) fillin yes
\t (00:00:36) Symbol 'sop-8.psm' created.
\i (00:00:37) delete
\i (00:00:39) pick grid 0.366 3.447
\t (00:00:39) last pick: 0.400 3.400
\t (00:00:39) Text "Last Edit:2024-3-16"
\i (00:00:40) pick grid 0.582 -3.398
\t (00:00:40) last pick: 0.600 -3.400
\t (00:00:40) Text "Approved[2]"
\i (00:00:40) prepopup 0.582 -3.398
\i (00:00:41) done
\i (00:00:42) save
\i (00:00:42) fillin yes
\t (00:00:42) Symbol 'sop-8.psm' created.
\i (00:00:43) exit
\t (00:00:44) Journal end - Mon Jul 29 04:49:18 2024
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sop-16"
\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/chip/sop-16.dra
\t (00:00:02) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
\i (00:00:02) trapsize 43
\i (00:00:02) trapsize 44
\i (00:00:03) trapsize 43
\i (00:00:03) trapsize 38
\i (00:00:03) trapsize 39
\i (00:00:03) trapsize 40
\t (00:00:03) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
\i (00:00:03) trapsize 41
\i (00:00:06) step pkg map
\i (00:00:06) fillin yes
\i (00:00:12) setwindow form.pkgmap3d
\i (00:00:12) FORM pkgmap3d stplist SOP-16.STEP
\i (00:00:15) FORM pkgmap3d overlay YES
\i (00:00:16) FORM pkgmap3d hide_board YES
\i (00:00:17) FORM pkgmap3d hide_board NO
\i (00:00:20) FORM pkgmap3d view_orientation Top
\i (00:00:23) FORM pkgmap3d save_current
\i (00:00:24) FORM pkgmap3d done
\i (00:00:27) setwindow pcb
\i (00:00:27) save
\i (00:00:27) fillin yes
\t (00:00:27) Symbol 'sop-16.psm' created.
\i (00:00:28) exit
\t (00:00:28) Journal end - Fri Aug 2 06:03:18 2024

27
chip/batch_drc.log Normal file
View File

@@ -0,0 +1,27 @@
(---------------------------------------------------------------------)
( )
( DRC Update )
( )
( Drawing : ssop-4.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 22:07:56 2024 )
( )
(---------------------------------------------------------------------)
========= check shapes 0:00:00
========= check standalone pins 0:00:00
========= check symbols (pins,lines,text) 0:00:00
========= check xnets 0:00:00
========= check nets 0:00:00
========= check standalone branches 0:00:00
========= check standalone filled rectangles 0:00:00
========= check standalone lines 0:00:00
========= check standalone text 0:00:00
========= check standalone rectangles 0:00:00
..... Total number of DRC errors 0
..... DRC update completed, total CPU time 0:00:00
*************************************************************************

27
chip/batch_drc.log,1 Normal file
View File

@@ -0,0 +1,27 @@
(---------------------------------------------------------------------)
( )
( DRC Update )
( )
( Drawing : sym_template.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 04:40:21 2024 )
( )
(---------------------------------------------------------------------)
========= check shapes 0:00:00
========= check standalone pins 0:00:00
========= check symbols (pins,lines,text) 0:00:00
========= check xnets 0:00:00
========= check nets 0:00:00
========= check standalone branches 0:00:00
========= check standalone filled rectangles 0:00:00
========= check standalone lines 0:00:00
========= check standalone text 0:00:00
========= check standalone rectangles 0:00:00
..... Total number of DRC errors 0
..... DRC update completed, total CPU time 0:00:00
*************************************************************************

27
chip/batch_drc.log,2 Normal file
View File

@@ -0,0 +1,27 @@
(---------------------------------------------------------------------)
( )
( DRC Update )
( )
( Drawing : sym_template.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 04:40:22 2024 )
( )
(---------------------------------------------------------------------)
========= check shapes 0:00:00
========= check standalone pins 0:00:00
========= check symbols (pins,lines,text) 0:00:00
========= check xnets 0:00:00
========= check nets 0:00:00
========= check standalone branches 0:00:00
========= check standalone filled rectangles 0:00:00
========= check standalone lines 0:00:00
========= check standalone text 0:00:00
========= check standalone rectangles 0:00:00
..... Total number of DRC errors 0
..... DRC update completed, total CPU time 0:00:00
*************************************************************************

4
chip/downrev.log
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : lqfp64.dra )
( Drawing : ssop-4.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:50:52 2024 )
( Date/Time : Sat Aug 3 22:08:42 2024 )
( )
(---------------------------------------------------------------------)

4
chip/downrev.log,1
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : sop-8.dra )
( Drawing : ssop-4.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:49:17 2024 )
( Date/Time : Sat Aug 3 22:08:28 2024 )
( )
(---------------------------------------------------------------------)

4
chip/downrev.log,2
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : lqfp64.dra )
( Drawing : ssop-4.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:50:52 2024 )
( Date/Time : Sat Aug 3 22:08:42 2024 )
( )
(---------------------------------------------------------------------)

4
chip/downrev.log,3
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : lqfp64.dra )
( Drawing : ssop-4.dra )
( Software Version : 17.4S035 )
( Date/Time : Mon Jul 29 04:50:52 2024 )
( Date/Time : Sat Aug 3 22:08:42 2024 )
( )
(---------------------------------------------------------------------)

2
chip/master.tag
View File

@@ -1 +1 @@
lqfp64.dra
ssop-4.dra

20
chip/padstack_editor.jrl Normal file
View File

@@ -0,0 +1,20 @@
\t (00:00:01) padstack_editor 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:01) Journal start - Sat Aug 3 22:07:28 2024
\t (00:00:01) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=16304 CPUs=12
\t (00:00:01) CmdLine= d:\software\cadence\spb_17.4\tools\bin\padstack_editor.exe D:\workspace\GitHub\pcb_lib\chip\ssop-4.pad
\t (00:00:01)
\d (00:00:03) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:04) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:04) QtSignal 1
\d (00:00:04) QtSignal GuidedDesignLayersTab PadWidth editingFinished "1.0000"
\d (00:00:06) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:07) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:07) QtSignal 1
\d (00:00:10) QtSignal GuidedMaskLayersTab PadWidth editingFinished "1.0500"
\d (00:00:11) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 Pad
\d (00:00:11) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 Pad 2 1
\d (00:00:12) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:12) QtSignal 1
\d (00:00:12) QtSignal GuidedMaskLayersTab PadWidth editingFinished "1.0000"
\d (00:00:14) QtSignal MainWindow Save triggered
\t (00:00:15) Journal end - Sat Aug 3 22:07:42 2024

47
chip/padstack_editor.jrl,1 Normal file
View File

@@ -0,0 +1,47 @@
\t (00:00:01) padstack_editor 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:01) Journal start - Sat Aug 3 21:58:52 2024
\t (00:00:01) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=22372 CPUs=12
\t (00:00:01) CmdLine= d:\software\cadence\spb_17.4\tools\bin\padstack_editor.exe D:\workspace\GitHub\pcb_lib\chip\ssop-4.pad
\t (00:00:01)
\d (00:00:03) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:05) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:05) QtSignal 1
\d (00:00:13) QtSignal GuidedDesignLayersTab PadWidth editingFinished "1.0000"
\d (00:00:15) QtSignal GuidedDesignLayersTab PadHeight editingFinished "0.4000"
\d (00:00:27) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:27) QtSignal 1
\d (00:00:33) QtSignal GuidedDesignLayersTab PadHeight editingFinished "1.0000"
\d (00:00:36) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:36) QtSignal 1
\d (00:00:41) QtSignal GuidedDesignLayersTab PadWidth editingFinished "0.4000"
\d (00:00:43) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:43) QtSignal 1
\d (00:00:45) QtSignal GuidedDesignLayersTab PadWidth editingFinished "1.0000"
\d (00:00:46) QtSignal GuidedDesignLayersTab PadHeight editingFinished "0.2000"
\d (00:00:51) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:51) QtSignal 1
\d (00:00:52) QtSignal GuidedDesignLayersTab PadWidth editingFinished "0.4000"
\d (00:01:03) QtSignal GuidedDesignLayersTab PadHeight editingFinished "0.5000"
\d (00:01:19) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777248 33554432 false +
\d (00:01:19) QtSignal 1
\d (00:01:20) QtSignal GuidedDesignLayersTab PadWidth editingFinished "0.5000"
\d (00:01:21) QtSignal GuidedDesignLayersTab PadHeight editingFinished "0.4000"
\d (00:01:32) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:01:34) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:01:34) QtSignal 1
\d (00:01:35) QtSignal GuidedMaskLayersTab PadWidth editingFinished "0.5000"
\d (00:01:36) QtSignal GuidedMaskLayersTab PadHeight editingFinished "0.4000"
\d (00:01:38) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 Pad
\d (00:01:38) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 Pad 2 1
\d (00:01:39) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 0 Pad
\d (00:01:39) QtSignal GuidedMaskLayersTab LayersTable cellClicked 0 Pad 0 1
\d (00:01:41) QtSignal GuidedMaskLayersTab PadWidth editingFinished "0.5500"
\d (00:01:42) QtSignal GuidedMaskLayersTab PadHeight editingFinished "0.4500"
\d (00:01:43) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 Pad
\d (00:01:44) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 Pad 2 1
\d (00:01:45) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:01:45) QtSignal 1
\d (00:01:45) QtSignal GuidedMaskLayersTab PadWidth editingFinished "0.5000"
\d (00:01:46) QtSignal GuidedMaskLayersTab PadHeight editingFinished "0.4000"
\d (00:01:48) QtSignal MainWindow Save triggered
\t (00:01:49) Journal end - Sat Aug 3 22:00:40 2024

128
chip/param_read.log Normal file
View File

@@ -0,0 +1,128 @@
(---------------------------------------------------------------------)
( )
( Parameter File READ )
( )
( Drawing : ssop-4.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 22:01:23 2024 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/workspace/GitHub/pcb_lib/chip/ssop-4.dra
Reading...parameter_header:
Reading...db_common_type:
Reading...grid_parms_type:
WARNING: The value of element <etchcount> is not equal to the number of
user defined subclass under ETCH class.
Reading...UnusedPadsSuppressionSettings:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
WARNING: Unmatched Data - Field Name: subclass , Value: "SIGNEDTOP"
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
WARNING: Unmatched Data - Field Name: subclass , Value: "SIGNEDBOTTOM"
Reading...art_class_type:
Reading...art_class_type:
Reading...color_table_table:
Reading...ColorParmType:
Reading...profileCustomColors:
Reading...text_size_table:
Reading...drf_parm_type:
Reading...av_parm_type:
Reading...dynfill_parm_type:
Reading...probe_parm_type:
Reading...ifp_parm_type:
Reading...ministat_parm_type:
WARNING: Unmatched Data - Field Name: acon_active_sc , Value: "SIGNEDTOP"
Reading...ats_parm_type:
Reading...placement_parameter_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
..... Total number of errors: 0.
..... Total number of warnings: 4.

128
chip/param_read.log,1 Normal file
View File

@@ -0,0 +1,128 @@
(---------------------------------------------------------------------)
( )
( Parameter File READ )
( )
( Drawing : sop-16.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 04:40:41 2024 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/¹¤×÷¿â/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : D:/¹¤×÷¿â/GitHub/pcb_lib/chip/sop-16.dra
Reading...parameter_header:
Reading...db_common_type:
Reading...grid_parms_type:
WARNING: The value of element <etchcount> is not equal to the number of
user defined subclass under ETCH class.
Reading...UnusedPadsSuppressionSettings:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
WARNING: Unmatched Data - Field Name: subclass , Value: "SIGNEDTOP"
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
WARNING: Unmatched Data - Field Name: subclass , Value: "SIGNEDBOTTOM"
Reading...art_class_type:
Reading...art_class_type:
Reading...color_table_table:
Reading...ColorParmType:
Reading...profileCustomColors:
Reading...text_size_table:
Reading...drf_parm_type:
Reading...av_parm_type:
Reading...dynfill_parm_type:
Reading...probe_parm_type:
Reading...ifp_parm_type:
Reading...ministat_parm_type:
WARNING: Unmatched Data - Field Name: acon_active_sc , Value: "SIGNEDTOP"
Reading...ats_parm_type:
Reading...placement_parameter_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
..... Total number of errors: 0.
..... Total number of warnings: 4.

BIN
chip/sop-16.dra Normal file
View File

Binary file not shown.

23
chip/sop-16.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : sop-16.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 06:03:17 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = sop-16.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
chip/sop-16.log,1 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : sop-16.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 04:47:13 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/š¤×÷żâ/GitHub/pcb_lib/chip
Name = sop-16.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
chip/sop-16.log,2 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : sop-16.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 05:16:38 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/š¤×÷żâ/GitHub/pcb_lib/chip
Name = sop-16.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
chip/sop-16.log,3 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : sop-16.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 06:00:53 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/š¤×÷żâ/GitHub/pcb_lib/chip
Name = sop-16.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
chip/sop-16.pad Normal file
View File

Binary file not shown.

BIN
chip/sop-16.psm Normal file
View File

Binary file not shown.

BIN
chip/ssop-4.dra Normal file
View File

Binary file not shown.

23
chip/ssop-4.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : ssop-4.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 22:08:42 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = ssop-4.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

24
chip/ssop-4.log,1 Normal file
View File

@@ -0,0 +1,24 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : ssop-4.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 22:06:23 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = ssop-4.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
ERROR(SPMHCS-1): Symbol is missing a refdes.
ERROR(SPMHA1-291): Create symbol has been aborted.

23
chip/ssop-4.log,2 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : ssop-4.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 22:07:58 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = ssop-4.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
chip/ssop-4.log,3 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : ssop-4.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 22:08:28 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/chip
Name = ssop-4.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
chip/ssop-4.pad Normal file
View File

Binary file not shown.

BIN
chip/ssop-4.psm Normal file
View File

Binary file not shown.

96008
chip/stepFacetFiles4Map/SOP-16.xml Normal file
View File

File diff suppressed because it is too large Load Diff

8149
chip/stepFacetFiles4Map/ssop-4.xml Normal file
View File

File diff suppressed because it is too large Load Diff

3
chip/stepFacetFiles4Map/stepFileInfo.txt
View File

@@ -1,9 +1,11 @@
#STEP_FILE ! FILE_SIZE ! MOD_TIME
D8-M.step ! 282667 ! 1568096060
SOT-223.step ! 227596 ! 1710578258
tssop8.STEP ! 174674 ! 1711377980
lqfp48.step ! 1919983 ! 1711219780
D8-L.step ! 282667 ! 1568096060
SOP-16.STEP ! 3778717 ! 1722501952
DIP_2x5.step ! 720870 ! 1710578258
SSOP-8.step ! 755497 ! 1712718221
ESP-01.step ! 2352878 ! 1710578258
@@ -14,3 +16,4 @@ LED_0603_G.STEP ! 178570 ! 1710578258
KEY_SOT_P2.step ! 151224 ! 1710578258
sop-14.step ! 521672 ! 1710578258
ufqfpn28_2.step ! 4307335 ! 1711439232
ssop-4.STEP ! 294871 ! 1722693500

4
chip/stepFacetFiles4Map/stepFileInfo.txt,1
View File

@@ -1,10 +1,13 @@
#STEP_FILE ! FILE_SIZE ! MOD_TIME
D8-M.step ! 282667 ! 1568096060
SOT-223.step ! 227596 ! 1710578258
tssop8.STEP ! 174674 ! 1711377980
lqfp48.step ! 1919983 ! 1711219780
D8-L.step ! 282667 ! 1568096060
SOP-16.STEP ! 3778717 ! 1722501952
DIP_2x5.step ! 720870 ! 1710578258
SSOP-8.step ! 755497 ! 1712718221
ESP-01.step ! 2352878 ! 1710578258
LQFP64.step ! 14347354 ! 1710578258
sop-8.STEP ! 273188 ! 1710578258
@@ -12,4 +15,5 @@ tssop8.step ! 306368 ! 1711457082
LED_0603_G.STEP ! 178570 ! 1710578258
KEY_SOT_P2.step ! 151224 ! 1710578258
sop-14.step ! 521672 ! 1710578258
ssop-4.STEP ! 294871 ! 1722693500
ufqfpn28_2.step ! 4307335 ! 1711439232

BIN
chip/tssop-8.dra
View File

Binary file not shown.

23
chip/tssop-8.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : tssop-8.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 05:18:06 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/š¤×÷żâ/GitHub/pcb_lib/chip
Name = tssop-8.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
chip/tssop-8.psm
View File

Binary file not shown.

29
machine/allegro.jrl Normal file
View File

@@ -0,0 +1,29 @@
\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:03) Journal start - Fri Aug 2 06:23:15 2024
\t (00:00:03) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=25644 CPUs=12
\t (00:00:03) CmdLine= D:\SOFTWARE\Cadence\SPB_17.4\tools\bin\allegro.exe
\t (00:00:03)
(00:00:03) Loading axlcore.cxt
\t (00:00:05) Opening existing design...
\i (00:00:05) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "m3x0_5"
\d (00:00:05) Design opened: D:/workspace/GitHub/pcb_lib/machine/m3x0_5.dra
\i (00:00:06) trapsize 671
\i (00:00:06) trapsize 688
\i (00:00:06) trapsize 671
\i (00:00:06) trapsize 588
\i (00:00:06) trapsize 604
\i (00:00:06) trapsize 621
\i (00:00:06) trapsize 638
\i (00:00:15) open
\i (00:00:25) fillin "D:/workspace/Cadence/cardrive/allegro/cardrive.brd"
\i (00:00:25) cd "D:/workspace/Cadence/cardrive/allegro"
\t (00:00:26) Opening existing design...
\t (00:00:26) Grids are drawn 0.8000, 0.8000 apart for enhanced viewing.
\i (00:00:26) trapsize 5428
\i (00:00:26) trapsize 5562
\t (00:00:26) Grids are drawn 409.6000, 409.6000 apart for enhanced viewing.
\t (00:00:26) Grids are drawn 0.8000, 0.8000 apart for enhanced viewing.
\i (00:00:26) trapsize 6033
\i (00:00:26) trapsize 6033
\t (00:00:26) > Sending response DoneOpenBoard
\t (00:00:26) Journal end - Fri Aug 2 06:23:39 2024

44
machine/allegro.jrl,1 Normal file
View File

@@ -0,0 +1,44 @@
\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:03) Journal start - Fri Aug 2 06:19:47 2024
\t (00:00:03) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=24944 CPUs=12
\t (00:00:03) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\machine\m3x0_5.dra
\t (00:00:03)
(00:00:03) Loading axlcore.cxt
\t (00:00:05) Opening existing design...
\i (00:00:06) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "m3x0_5"
\d (00:00:06) Design opened: D:/workspace/GitHub/pcb_lib/machine/m3x0_5.dra
\i (00:00:06) trapsize 653
\i (00:00:06) trapsize 671
\i (00:00:06) trapsize 653
\i (00:00:06) trapsize 573
\i (00:00:06) trapsize 589
\i (00:00:06) trapsize 605
\i (00:00:06) trapsize 621
\i (00:00:07) save
\i (00:00:08) fillin yes
\t (00:00:08) Symbol 'm3x0_5.psm' created.
\i (00:00:10) step pkg map
\i (00:00:11) fillin yes
\i (00:00:16) setwindow form.pkgmap3d
\i (00:00:16) FORM pkgmap3d stplist M3x18.STEP
\i (00:02:49) setwindow pcb
\i (00:02:49) step pkg map
\i (00:02:53) fillin no
\i (00:02:57) setwindow form.pkgmap3d
\i (00:02:57) FORM pkgmap3d rotation_y 90
\i (00:02:59) FORM pkgmap3d rotation_y 0
\i (00:03:00) FORM pkgmap3d rotation_x 90
\i (00:03:02) FORM pkgmap3d hide_board YES
\i (00:03:06) FORM pkgmap3d view_orientation Top
\i (00:03:08) FORM pkgmap3d view_orientation Left
\i (00:03:12) FORM pkgmap3d offset_z 10
\i (00:03:14) FORM pkgmap3d offset_z 20
\i (00:03:17) FORM pkgmap3d offset_z 15
\i (00:03:21) FORM pkgmap3d save_current
\i (00:03:22) FORM pkgmap3d done
\i (00:03:23) setwindow pcb
\i (00:03:23) save
\i (00:03:24) fillin yes
\t (00:03:24) Symbol 'm3x0_5.psm' created.
\i (00:03:25) exit
\t (00:03:25) Journal end - Fri Aug 2 06:23:09 2024

14
machine/downrev.log Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : m3x0_5.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 06:23:08 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
machine/downrev.log,1 Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : m3x0_5.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 06:19:52 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
machine/downrev.log,2 Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : m3x0_5.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 06:23:08 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
machine/downrev.log,3 Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : m3x0_5.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 06:23:08 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

BIN
machine/m3x0_5.dra
View File

Binary file not shown.

23
machine/m3x0_5.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : m3x0_5.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 06:23:08 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/machine
Name = m3x0_5.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
machine/m3x0_5.log,1 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : m3x0_5.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 05:25:21 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/š¤×÷żâ/GitHub/pcb_lib/machine
Name = m3x0_5.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
machine/m3x0_5.log,2 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : m3x0_5.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 06:03:48 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/š¤×÷żâ/GitHub/pcb_lib/machine
Name = m3x0_5.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
machine/m3x0_5.log,3 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : m3x0_5.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 06:19:52 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/machine
Name = m3x0_5.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
machine/m3x0_5.psm
View File

Binary file not shown.

1
machine/master.tag Normal file
View File

@@ -0,0 +1 @@
m3x0_5.dra

25507
machine/stepFacetFiles4Map/M3x18.xml Normal file
View File

File diff suppressed because it is too large Load Diff

46399
machine/stepFacetFiles4Map/M3x8.xml
View File

File diff suppressed because it is too large Load Diff

4
machine/stepFacetFiles4Map/stepFileInfo.txt
View File

@@ -1,4 +1,6 @@
#STEP_FILE ! FILE_SIZE ! MOD_TIME
M3x8.step ! 519917 ! 1710578258
P8.step ! 229628 ! 1568096060
M3x18.STEP ! 717806 ! 1722547502
M3x8.step ! 440671 ! 1722533353
LED_0603_G.STEP ! 178570 ! 1710578258

6
machine/stepFacetFiles4Map/stepFileInfo.txt,1 Normal file
View File

@@ -0,0 +1,6 @@
#STEP_FILE ! FILE_SIZE ! MOD_TIME
P8.step ! 229628 ! 1568096060
M3x18.STEP ! 717806 ! 1722547502
M3x8.step ! 440671 ! 1722533353
LED_0603_G.STEP ! 178570 ! 1710578258

50
smc/allegro.jrl
View File

@@ -1,18 +1,32 @@
\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Sun Jul 28 23:00:44 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=26612 CPUs=12
\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\smc\ll34.dra
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:02) Opening existing design...
\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged ll34
\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/smc/ll34.dra
\i (00:00:02) trapsize 344
\i (00:00:02) trapsize 353
\i (00:00:02) trapsize 344
\i (00:00:03) trapsize 302
\i (00:00:03) trapsize 310
\i (00:00:03) trapsize 319
\i (00:00:03) trapsize 327
\i (00:09:26) exit
\t (00:09:26) Journal end - Sun Jul 28 23:10:09 2024
\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:03) Journal start - Sat Aug 3 21:35:27 2024
\t (00:00:03) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=9888 CPUs=12
\t (00:00:03) CmdLine= D:\SOFTWARE\Cadence\SPB_17.4\tools\bin\allegro.exe
\t (00:00:03)
(00:00:03) Loading axlcore.cxt
\t (00:00:05) Opening existing design...
\i (00:00:05) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged ll41
\d (00:00:05) Design opened: D:/workspace/GitHub/pcb_lib/smc/ll41.dra
\i (00:00:06) trapsize 335
\i (00:00:06) trapsize 344
\i (00:00:06) trapsize 335
\i (00:00:06) trapsize 294
\i (00:00:06) trapsize 302
\i (00:00:06) trapsize 310
\i (00:00:06) trapsize 319
\i (00:00:09) open
\i (00:00:19) fillin "D:/workspace/Cadence/step-motor/allegro/motor.brd"
\i (00:00:19) cd "D:/workspace/Cadence/step-motor/allegro"
\t (00:00:20) Opening existing design...
\t (00:00:20) Grids are drawn 0.6400, 0.6400 apart for enhanced viewing.
\i (00:00:20) trapsize 5519
\i (00:00:20) trapsize 5655
\t (00:00:20) Grids are drawn 327.6800, 327.6800 apart for enhanced viewing.
\t (00:00:20) Grids are drawn 0.6400, 0.6400 apart for enhanced viewing.
\i (00:00:20) trapsize 6134
\i (00:00:20) setwindow form.mini
\i (00:00:20) FORM mini tree 'Components by refdes'
\i (00:00:20) setwindow pcb
\i (00:00:20) trapsize 6134
\t (00:00:20) > Sending response DoneOpenBoard
\t (00:00:20) Journal end - Sat Aug 3 21:35:45 2024

734
smc/allegro.jrl,1
View File

@@ -1,30 +1,708 @@
\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:02) Journal start - Sun Jul 28 22:59:58 2024
\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=21904 CPUs=12
\t (00:00:02) CmdLine= D:\SOFTWARE\Cadence\SPB_17.4\tools\bin\allegro.exe
\t (00:00:02)
(00:00:02) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:03) Journal start - Sat Aug 3 21:13:49 2024
\t (00:00:03) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=15968 CPUs=12
\t (00:00:03) CmdLine= D:\SOFTWARE\Cadence\SPB_17.4\tools\bin\allegro.exe
\t (00:00:03)
(00:00:03) Loading axlcore.cxt
\t (00:00:05) Opening existing design...
\i (00:00:05) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged ll34
\d (00:00:05) Design opened: D:/workspace/GitHub/pcb_lib/smc/ll34.dra
\i (00:00:05) trapsize 344
\i (00:00:05) trapsize 353
\i (00:00:05) trapsize 344
\i (00:00:05) trapsize 302
\i (00:00:05) trapsize 310
\i (00:00:05) trapsize 319
\i (00:00:05) trapsize 327
\i (00:00:08) open
\i (00:00:18) fillin "D:/workspace/Cadence/buck_loop/allegro/buck_loop.brd"
\i (00:00:18) cd "D:/workspace/Cadence/buck_loop/allegro"
\t (00:00:18) Opening existing design...
\i (00:00:18) trapsize 252
\i (00:00:19) trapsize 259
\t (00:00:19) Grids are drawn 12.8000, 12.8000 apart for enhanced viewing.
\i (00:00:19) trapsize 276
\i (00:00:19) setwindow form.mini
\i (00:00:19) FORM mini tree 'Components by refdes'
\i (00:00:19) setwindow pcb
\i (00:00:19) trapsize 276
\t (00:00:19) > Sending response DoneOpenBoard
\t (00:00:19) Journal end - Sun Jul 28 23:00:15 2024
\i (00:00:06) trapsize 353
\i (00:00:06) trapsize 362
\i (00:00:06) trapsize 353
\i (00:00:06) trapsize 310
\i (00:00:06) trapsize 318
\i (00:00:06) trapsize 327
\i (00:00:06) trapsize 336
\i (00:00:10) new
\i (00:00:18) newdrawfillin "ll41.dra" "Package Symbol"
\t (00:00:18) Starting new design...
\i (00:00:19) trapsize 1716
\i (00:00:19) trapsize 1758
\i (00:00:19) trapsize 1716
\t (00:00:19) Grids are drawn 81.2800, 81.2800 apart for enhanced viewing.
\i (00:00:19) trapsize 2572
\i (00:00:19) trapsize 2572
\i (00:00:19) trapsize 2483
\i (00:00:23) param in
\i (00:00:24) setwindow form.parm_in
\i (00:00:24) FORM parm_in browse
\i (00:00:28) fillin "D:/workspace/GitHub/pcb_lib/XerolySkinner.prm"
\i (00:00:29) FORM parm_in execute
\t (00:00:29) Starting Importing parameter file...
\w (00:00:29) WARNING(SPMHGE-269): param in had warnings, use Viewlog to review the log file.
\t (00:00:29) Opening existing design...
\i (00:00:29) setwindow pcb
\i (00:00:29) trapsize 2572
\i (00:00:29) trapsize 2668
\i (00:00:29) trapsize 2572
\i (00:00:30) trapsize 2572
\i (00:00:30) trapsize 2483
\i (00:00:31) setwindow text
\i (00:00:31) close
\i (00:00:32) setwindow form.parm_in
\i (00:00:32) FORM parm_in cancel
\i (00:00:33) setwindow pcb
\i (00:00:33) zoom in 1
\i (00:00:33) setwindow pcb
\i (00:00:33) zoom in -0.2234 -0.1241
\i (00:00:33) trapsize 1241
\i (00:00:36) zoom in 1
\i (00:00:36) setwindow pcb
\i (00:00:36) zoom in -1.3654 0.3725
\i (00:00:36) trapsize 621
\i (00:00:36) zoom in 1
\i (00:00:36) setwindow pcb
\i (00:00:36) zoom in -1.3654 0.3725
\i (00:00:36) trapsize 310
\i (00:00:36) zoom in 1
\i (00:00:36) setwindow pcb
\i (00:00:36) zoom in -1.3653 0.3725
\i (00:00:36) trapsize 155
\i (00:00:36) zoom out 1
\i (00:00:36) setwindow pcb
\i (00:00:36) zoom out 0.0498 -0.0371
\i (00:00:36) trapsize 310
\i (00:00:36) zoom out 1
\i (00:00:36) setwindow pcb
\i (00:00:36) zoom out 0.0498 -0.0371
\i (00:00:37) trapsize 621
\i (00:00:37) zoom out 1
\i (00:00:37) setwindow pcb
\i (00:00:37) zoom out 0.0498 -0.0372
\i (00:00:37) trapsize 1241
\i (00:00:37) zoom out 1
\i (00:00:37) setwindow pcb
\i (00:00:37) zoom out 0.0498 -0.0371
\i (00:00:37) trapsize 2483
\i (00:00:38) zoom in 1
\i (00:00:38) setwindow pcb
\i (00:00:38) zoom in -1.0179 -0.5710
\i (00:00:38) trapsize 1241
\i (00:00:41) add pin
\i (00:00:44) setwindow form.mini
\i (00:00:44) FORM mini pad_name ll41
\t (00:00:44) Using 'LL41.pad'.
\i (00:00:47) FORM mini text_name pin
\i (00:00:49) FORM mini x_count 2
\i (00:01:03) FORM mini x_spacing 3.7500
\i (00:01:10) FORM mini rotate_pin 0.000
\t (00:01:10) Using 'LL41.pad'.
\i (00:01:24) setwindow pcb
\i (00:01:24) pick 0 -1.875
\t (00:01:24) last pick: 0.0000 -1.8750
\t (00:01:24) Using 'LL41.pad'.
\i (00:01:26) prepopup 5.8839 -0.3227
\i (00:01:26) oops
\t (00:01:26) Using 'LL41.pad'.
\i (00:01:30) setwindow form.mini
\i (00:01:30) FORM mini next_pin_number 1
\i (00:01:34) setwindow pcb
\i (00:01:34) pick -1.875 0
\t (00:01:34) last pick: -1.8750 0.0000
\t (00:01:34) Using 'LL41.pad'.
\i (00:01:35) prepopup 7.4727 2.5323
\i (00:01:36) done
\t (00:01:36) Exiting from Add Pin.
\i (00:01:37) zoom in 1
\i (00:01:37) setwindow pcb
\i (00:01:37) zoom in -1.0178 -0.6207
\i (00:01:37) trapsize 621
\i (00:01:37) zoom in 1
\i (00:01:37) setwindow pcb
\i (00:01:37) zoom in -1.0178 -0.6207
\i (00:01:37) trapsize 310
\i (00:01:37) zoom out 1
\i (00:01:37) setwindow pcb
\i (00:01:37) zoom out -0.2916 -0.9621
\i (00:01:37) trapsize 621
\i (00:01:37) zoom out 1
\i (00:01:37) setwindow pcb
\i (00:01:37) zoom out -0.2915 -0.9620
\i (00:01:37) trapsize 1241
\i (00:01:43) define grid
\t (00:01:43) Spacing fields allow simple equations to aid calculations; prefix with =
\i (00:01:44) setwindow form.grid
\i (00:01:44) FORM grid non_etch non_etch_x_grids 0.01
\i (00:01:45) FORM grid non_etch non_etch_y_grids 0.01
\i (00:01:46) FORM grid done
\i (00:01:49) setwindow pcb
\i (00:01:49) prmed
\i (00:01:51) setwindow form.prmedit
\i (00:01:51) FORM prmedit design
\i (00:01:53) FORM prmedit cancel
\i (00:01:55) setwindow pcb
\i (00:01:55) define grid
\t (00:01:55) Spacing fields allow simple equations to aid calculations; prefix with =
\i (00:01:59) setwindow form.grid
\i (00:01:59) FORM grid all_etch all_etch_x_grids 0.1
\i (00:02:00) FORM grid all_etch all_etch_y_grids 0.1
\i (00:02:00) FORM grid done
\i (00:02:02) setwindow pcb
\i (00:02:02) zoom out 1
\i (00:02:02) setwindow pcb
\i (00:02:02) zoom out -0.5647 0.2793
\t (00:02:02) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:02:02) trapsize 2483
\i (00:02:02) zoom out 1
\i (00:02:02) setwindow pcb
\i (00:02:02) zoom out 4.2453 -0.9186
\i (00:02:02) trapsize 2483
\i (00:02:02) zoom out 1
\i (00:02:02) setwindow pcb
\i (00:02:02) zoom out 4.2453 -0.9186
\i (00:02:02) trapsize 2483
\i (00:02:02) zoom out 1
\i (00:02:02) setwindow pcb
\i (00:02:02) zoom out 4.2453 -0.9186
\i (00:02:02) trapsize 2483
\i (00:02:02) zoom out 1
\i (00:02:02) setwindow pcb
\i (00:02:02) zoom out 4.2453 -0.9186
\i (00:02:02) trapsize 2483
\i (00:02:03) zoom in 1
\i (00:02:03) setwindow pcb
\i (00:02:03) zoom in 0.3724 0.1738
\i (00:02:03) trapsize 1241
\i (00:02:03) zoom in 1
\i (00:02:03) setwindow pcb
\i (00:02:03) zoom in 0.3724 0.1738
\i (00:02:03) trapsize 621
\i (00:02:03) zoom in 1
\i (00:02:03) setwindow pcb
\i (00:02:03) zoom in 0.3724 0.1738
\i (00:02:03) trapsize 310
\i (00:02:03) zoom in 1
\i (00:02:03) setwindow pcb
\i (00:02:03) zoom in 0.3724 0.1738
\i (00:02:03) trapsize 155
\i (00:02:03) zoom in 1
\i (00:02:03) setwindow pcb
\i (00:02:03) zoom in 0.3725 0.1739
\i (00:02:03) trapsize 78
\i (00:02:03) zoom in 1
\i (00:02:03) setwindow pcb
\i (00:02:03) zoom in 0.3725 0.1739
\i (00:02:03) trapsize 39
\i (00:02:03) zoom out 1
\i (00:02:03) setwindow pcb
\i (00:02:03) zoom out 0.3725 0.1739
\i (00:02:03) trapsize 78
\i (00:02:03) zoom out 1
\i (00:02:03) setwindow pcb
\i (00:02:03) zoom out 0.3725 0.1739
\i (00:02:03) trapsize 155
\i (00:02:03) zoom out 1
\i (00:02:03) setwindow pcb
\i (00:02:03) zoom out 0.3726 0.1740
\i (00:02:03) trapsize 310
\i (00:02:05) label refdes
\t (00:02:05) Grids are drawn 0.0400, 0.0400 apart for enhanced viewing.
\t (00:02:05) Pick text location.
\i (00:02:09) setwindow form.mini
\i (00:02:09) FORM mini text_name asm
\i (00:02:10) setwindow pcb
\i (00:02:10) pick 0 0
\t (00:02:10) last pick: 0.0000 0.0000
\t (00:02:10) Enter text string.
\i (00:02:12) setwindow pcb
\i (00:02:12) pick 0.0000 0.0000
\i (00:02:13) setwindow pcb
\i (00:02:13) prepopup 3.2460 1.8124
\i (00:02:14) next
\i (00:02:15) setwindow form.mini
\i (00:02:15) FORM mini subclass SILKSCREEN_TOP
\i (00:02:15) setwindow pcb
\i (00:02:15) updateport CVPane
\i (00:02:20) setwindow form.mini
\i (00:02:20) FORM mini text_name ski
\i (00:02:22) setwindow pcb
\i (00:02:22) pick 0 0
\t (00:02:22) last pick: 0.0000 0.0000
\t (00:02:22) Enter text string.
\i (00:02:23) setwindow pcb
\i (00:02:23) pick 0.0000 0.0000
\i (00:02:24) setwindow pcb
\i (00:02:24) prepopup 4.6796 1.5517
\i (00:02:24) done
\i (00:02:25) zoom out 1
\i (00:02:25) setwindow pcb
\i (00:02:25) zoom out 4.6610 0.3601
\t (00:02:25) Grids are drawn 0.0800, 0.0800 apart for enhanced viewing.
\i (00:02:25) trapsize 621
\i (00:02:28) add line
\i (00:02:33) setwindow form.mini
\i (00:02:33) FORM mini class 'PACKAGE GEOMETRY'
\i (00:02:36) FORM mini subclass SILKSCREEN_TOP
\i (00:02:36) setwindow pcb
\i (00:02:36) updateport CVPane
\i (00:02:39) setwindow form.mini
\i (00:02:39) FORM mini line_width 0.1500
\i (00:02:41) setwindow pcb
\i (00:02:41) zoom in 1
\i (00:02:41) setwindow pcb
\i (00:02:41) zoom in 0.4408 0.6580
\t (00:02:41) Grids are drawn 0.0400, 0.0400 apart for enhanced viewing.
\i (00:02:41) trapsize 310
\i (00:02:42) zoom in 1
\i (00:02:42) setwindow pcb
\i (00:02:42) zoom in 2.6813 1.0428
\t (00:02:42) Grids are drawn 0.0200, 0.0200 apart for enhanced viewing.
\i (00:02:42) trapsize 155
\i (00:02:42) zoom in 1
\i (00:02:42) setwindow pcb
\i (00:02:42) zoom in 2.6813 1.0428
\i (00:02:42) trapsize 78
\i (00:02:42) zoom in 1
\i (00:02:42) setwindow pcb
\i (00:02:42) zoom in 2.5479 1.0257
\i (00:02:42) trapsize 39
\i (00:02:44) zoom in 1
\i (00:02:44) setwindow pcb
\i (00:02:44) zoom in 2.5410 1.0436
\i (00:02:44) trapsize 19
\i (00:02:44) zoom in 1
\i (00:02:44) setwindow pcb
\i (00:02:44) zoom in 2.5410 1.0436
\i (00:02:44) trapsize 10
\i (00:02:47) pick grid 2.5304 1.0305
\t (00:02:47) last pick: 2.5300 1.0300
\i (00:02:47) prepopup 2.5211 1.0328
\i (00:02:48) oops
\i (00:02:50) pick grid 2.5399 1.0408
\t (00:02:50) last pick: 2.5400 1.0400
\i (00:02:50) prepopup 2.5399 1.0408
\i (00:02:51) oops
\i (00:02:54) define grid
\t (00:02:54) Spacing fields allow simple equations to aid calculations; prefix with =
\i (00:02:56) setwindow form.grid
\i (00:02:56) FORM grid non_etch non_etch_x_grids 0.1
\i (00:02:56) FORM grid non_etch non_etch_y_grids 0.1
\i (00:02:57) FORM grid done
\i (00:02:58) setwindow pcb
\i (00:02:58) zoom out 1
\i (00:02:58) setwindow pcb
\i (00:02:58) zoom out 2.5145 1.0293
\i (00:02:58) trapsize 19
\i (00:02:58) zoom out 1
\i (00:02:58) setwindow pcb
\i (00:02:58) zoom out 2.5145 1.0293
\i (00:02:58) trapsize 39
\i (00:02:58) zoom out 1
\i (00:02:58) setwindow pcb
\i (00:02:58) zoom out 2.5146 1.0293
\i (00:02:58) trapsize 78
\i (00:02:59) pick grid 2.6061 1.1086
\t (00:02:59) last pick: 2.6000 1.1000
\i (00:03:00) zoom out 1
\i (00:03:00) setwindow pcb
\i (00:03:00) zoom out 2.6853 1.0124
\i (00:03:00) trapsize 155
\i (00:03:00) zoom out 1
\i (00:03:00) setwindow pcb
\i (00:03:00) zoom out 2.6853 1.0123
\i (00:03:00) trapsize 310
\i (00:03:00) zoom out 1
\i (00:03:00) setwindow pcb
\i (00:03:00) zoom out 2.6852 1.0124
\i (00:03:00) trapsize 621
\i (00:03:01) zoom in 1
\i (00:03:01) setwindow pcb
\i (00:03:01) zoom in -2.8390 1.3847
\i (00:03:01) trapsize 310
\i (00:03:01) zoom in 1
\i (00:03:01) setwindow pcb
\i (00:03:01) zoom in -2.8390 1.3848
\i (00:03:01) trapsize 155
\i (00:03:01) zoom in 1
\i (00:03:01) setwindow pcb
\i (00:03:01) zoom in -2.8390 1.3848
\i (00:03:01) trapsize 78
\i (00:03:02) pick grid -2.5503 1.1086
\t (00:03:02) last pick: -2.6000 1.1000
\i (00:03:03) zoom out 1
\i (00:03:03) setwindow pcb
\i (00:03:03) zoom out -2.5938 1.2871
\i (00:03:03) trapsize 155
\i (00:03:03) zoom out 1
\i (00:03:03) setwindow pcb
\i (00:03:03) zoom out -2.5938 1.2870
\i (00:03:03) trapsize 310
\i (00:03:03) zoom out 1
\i (00:03:03) setwindow pcb
\i (00:03:03) zoom out -2.5937 1.2870
\i (00:03:03) trapsize 621
\i (00:03:03) zoom out 1
\i (00:03:03) setwindow pcb
\i (00:03:03) zoom out -2.5937 1.2870
\i (00:03:03) trapsize 1241
\i (00:03:04) zoom in 1
\i (00:03:04) setwindow pcb
\i (00:03:04) zoom in -2.4944 -1.1709
\i (00:03:04) trapsize 621
\i (00:03:04) zoom in 1
\i (00:03:04) setwindow pcb
\i (00:03:04) zoom in -2.4943 -1.1708
\i (00:03:04) trapsize 310
\i (00:03:04) zoom in 1
\i (00:03:04) setwindow pcb
\i (00:03:04) zoom in -2.4943 -1.1708
\i (00:03:04) trapsize 155
\i (00:03:04) zoom in 1
\i (00:03:04) setwindow pcb
\i (00:03:04) zoom in -2.4942 -1.1707
\i (00:03:04) trapsize 78
\i (00:03:04) zoom in 1
\i (00:03:04) setwindow pcb
\i (00:03:04) zoom in -2.4942 -1.1707
\i (00:03:04) trapsize 39
\i (00:03:06) pick grid -2.5702 -1.0512
\t (00:03:06) last pick: -2.6000 -1.1000
\i (00:03:06) zoom out 1
\i (00:03:06) setwindow pcb
\i (00:03:06) zoom out -2.7060 -1.2025
\i (00:03:06) trapsize 78
\i (00:03:06) zoom out 1
\i (00:03:06) setwindow pcb
\i (00:03:06) zoom out -2.7059 -1.2025
\i (00:03:06) trapsize 155
\i (00:03:07) zoom out 1
\i (00:03:07) setwindow pcb
\i (00:03:07) zoom out -2.0728 -1.3142
\i (00:03:07) trapsize 310
\i (00:03:07) zoom out 1
\i (00:03:07) setwindow pcb
\i (00:03:07) zoom out -2.0728 -1.3142
\i (00:03:07) trapsize 621
\i (00:03:08) zoom in 1
\i (00:03:08) setwindow pcb
\i (00:03:08) zoom in 2.9425 -1.1528
\i (00:03:08) trapsize 310
\i (00:03:08) zoom in 1
\i (00:03:08) setwindow pcb
\i (00:03:08) zoom in 2.9426 -1.1528
\i (00:03:08) trapsize 155
\i (00:03:08) zoom in 1
\i (00:03:08) setwindow pcb
\i (00:03:08) zoom in 2.9426 -1.1528
\i (00:03:08) trapsize 78
\i (00:03:09) pick grid 2.6478 -1.0659
\t (00:03:09) last pick: 2.6000 -1.1000
\i (00:03:09) zoom out 1
\i (00:03:09) setwindow pcb
\i (00:03:09) zoom out 2.6928 -1.2661
\i (00:03:09) trapsize 155
\i (00:03:09) zoom out 1
\i (00:03:09) setwindow pcb
\i (00:03:09) zoom out 2.6929 -1.2660
\i (00:03:09) trapsize 310
\i (00:03:09) zoom out 1
\i (00:03:09) setwindow pcb
\i (00:03:09) zoom out 2.6928 -1.2660
\i (00:03:09) trapsize 621
\i (00:03:10) zoom in 1
\i (00:03:10) setwindow pcb
\i (00:03:10) zoom in 2.5936 1.2043
\i (00:03:10) trapsize 310
\i (00:03:10) zoom in 1
\i (00:03:10) setwindow pcb
\i (00:03:10) zoom in 2.5936 1.2044
\i (00:03:10) trapsize 155
\i (00:03:10) zoom in 1
\i (00:03:10) setwindow pcb
\i (00:03:10) zoom in 2.5936 1.2044
\i (00:03:10) trapsize 78
\i (00:03:11) pick grid 2.6107 1.1486
\t (00:03:11) last pick: 2.6000 1.1000
\i (00:03:11) prepopup 2.6091 1.1222
\i (00:03:12) done
\i (00:03:12) zoom out 1
\i (00:03:12) setwindow pcb
\i (00:03:12) zoom out 2.6045 1.1424
\i (00:03:12) trapsize 155
\i (00:03:12) zoom out 1
\i (00:03:12) setwindow pcb
\i (00:03:12) zoom out 2.6045 1.1423
\i (00:03:12) trapsize 310
\i (00:03:12) zoom out 1
\i (00:03:12) setwindow pcb
\i (00:03:12) zoom out 2.6044 1.1424
\i (00:03:12) trapsize 621
\i (00:03:12) zoom out 1
\i (00:03:12) setwindow pcb
\i (00:03:12) zoom out 2.6045 1.1424
\i (00:03:12) trapsize 1241
\i (00:03:13) zoom in 1
\i (00:03:13) setwindow pcb
\i (00:03:13) zoom in 0.1961 0.0251
\i (00:03:13) trapsize 621
\i (00:03:17) shape add rect
\i (00:03:20) zoom in 1
\i (00:03:20) setwindow pcb
\i (00:03:20) zoom in -0.0646 0.1617
\i (00:03:20) trapsize 310
\i (00:03:20) zoom in 1
\i (00:03:20) setwindow pcb
\i (00:03:20) zoom in -0.0646 0.1617
\i (00:03:20) trapsize 155
\i (00:03:20) zoom in 1
\i (00:03:20) setwindow pcb
\i (00:03:20) zoom in -0.0645 0.1617
\i (00:03:20) trapsize 78
\i (00:03:20) zoom in 1
\i (00:03:20) setwindow pcb
\i (00:03:20) zoom in -0.0645 0.1617
\i (00:03:20) trapsize 39
\i (00:03:20) zoom in 1
\i (00:03:20) setwindow pcb
\i (00:03:20) zoom in -0.0645 0.1617
\i (00:03:20) trapsize 19
\i (00:03:21) zoom out 1
\i (00:03:21) setwindow pcb
\i (00:03:21) zoom out -0.0644 0.1617
\i (00:03:21) trapsize 39
\i (00:03:21) zoom out 1
\i (00:03:21) setwindow pcb
\i (00:03:21) zoom out -0.0645 0.1617
\i (00:03:21) trapsize 78
\i (00:03:22) zoom out 1
\i (00:03:22) setwindow pcb
\i (00:03:22) zoom out -0.0039 0.5000
\i (00:03:22) trapsize 155
\i (00:03:22) zoom out 1
\i (00:03:22) setwindow pcb
\i (00:03:22) zoom out -0.0039 0.5000
\i (00:03:22) trapsize 310
\i (00:03:23) pick grid 0.0457 1.1393
\t (00:03:23) last pick: 0.0000 1.1000
\i (00:03:26) pick grid -2.5922 -1.0580
\t (00:03:26) last pick: -2.6000 -1.1000
\i (00:03:26) prepopup -1.4439 -1.8090
\i (00:03:27) done
\i (00:03:28) save
\t (00:03:28) Symbol 'll41.psm' created.
\i (00:03:30) zoom out 1
\i (00:03:30) setwindow pcb
\i (00:03:30) zoom out -0.8977 -0.6111
\i (00:03:30) trapsize 621
\i (00:03:36) add rect
\i (00:03:38) setwindow form.mini
\i (00:03:38) FORM mini subclass ASSEMBLY_TOP
\i (00:03:38) setwindow pcb
\i (00:03:38) updateport CVPane
\i (00:03:40) zoom in 1
\i (00:03:40) setwindow pcb
\i (00:03:40) zoom in 2.5533 1.0648
\i (00:03:40) trapsize 310
\i (00:03:40) zoom in 1
\i (00:03:40) setwindow pcb
\i (00:03:40) zoom in 2.5533 1.0649
\i (00:03:40) trapsize 155
\i (00:03:40) zoom in 1
\i (00:03:40) setwindow pcb
\i (00:03:40) zoom in 2.5534 1.0649
\i (00:03:40) trapsize 78
\i (00:03:40) zoom in 1
\i (00:03:40) setwindow pcb
\i (00:03:40) zoom in 2.5534 1.0649
\i (00:03:40) trapsize 39
\i (00:03:42) pick grid 2.5845 1.0796
\t (00:03:42) last pick: 2.6000 1.1000
\i (00:03:43) zoom out 1
\i (00:03:43) setwindow pcb
\i (00:03:43) zoom out 2.6039 0.9539
\i (00:03:43) trapsize 78
\i (00:03:43) zoom out 1
\i (00:03:43) setwindow pcb
\i (00:03:43) zoom out 2.6039 0.9540
\i (00:03:43) trapsize 155
\i (00:03:43) zoom out 1
\i (00:03:43) setwindow pcb
\i (00:03:43) zoom out 2.6039 0.9540
\i (00:03:43) trapsize 310
\i (00:03:43) zoom out 1
\i (00:03:43) setwindow pcb
\i (00:03:43) zoom out 2.6039 0.9541
\i (00:03:43) trapsize 621
\i (00:03:44) zoom in 1
\i (00:03:44) setwindow pcb
\i (00:03:44) zoom in -2.6597 -1.1067
\i (00:03:44) trapsize 310
\i (00:03:44) zoom in 1
\i (00:03:44) setwindow pcb
\i (00:03:44) zoom in -2.6597 -1.1067
\i (00:03:44) trapsize 155
\i (00:03:44) zoom in 1
\i (00:03:44) setwindow pcb
\i (00:03:44) zoom in -2.6597 -1.1067
\i (00:03:44) trapsize 78
\i (00:03:45) pick grid -2.5541 -1.1036
\t (00:03:45) last pick: -2.6000 -1.1000
\i (00:03:45) prepopup -2.9095 -1.1284
\i (00:03:46) done
\i (00:03:48) shape add rect
\i (00:03:50) setwindow form.mini
\i (00:03:50) FORM mini subclass PLACE_BOUND_TOP
\i (00:03:50) setwindow pcb
\i (00:03:50) updateport CVPane
\i (00:03:52) pick grid -2.5945 -1.1005
\t (00:03:52) last pick: -2.6000 -1.1000
\i (00:03:52) zoom out 1
\i (00:03:52) setwindow pcb
\i (00:03:52) zoom out -3.1143 -1.4527
\i (00:03:52) trapsize 155
\i (00:03:52) zoom out 1
\i (00:03:52) setwindow pcb
\i (00:03:52) zoom out -3.1143 -1.4527
\i (00:03:52) trapsize 310
\i (00:03:52) zoom out 1
\i (00:03:52) setwindow pcb
\i (00:03:52) zoom out -3.1143 -1.4528
\i (00:03:52) trapsize 621
\i (00:03:52) zoom out 1
\i (00:03:52) setwindow pcb
\i (00:03:52) zoom out -3.1144 -1.4527
\i (00:03:52) trapsize 1241
\i (00:03:53) zoom in 1
\i (00:03:53) setwindow pcb
\i (00:03:53) zoom in 2.5712 0.4838
\i (00:03:53) trapsize 621
\i (00:03:53) zoom in 1
\i (00:03:53) setwindow pcb
\i (00:03:53) zoom in 2.5712 0.4839
\i (00:03:53) trapsize 310
\i (00:03:55) pick grid 2.6147 1.0549
\t (00:03:55) last pick: 2.6000 1.1000
\i (00:03:55) zoom out 1
\i (00:03:55) setwindow pcb
\i (00:03:55) zoom out 4.7685 3.3143
\i (00:03:55) trapsize 621
\i (00:03:56) zoom in 1
\i (00:03:56) setwindow pcb
\i (00:03:56) zoom in 0.4857 0.0245
\i (00:03:56) trapsize 310
\i (00:03:56) zoom in 1
\i (00:03:56) setwindow pcb
\i (00:03:56) zoom in 0.4857 0.0245
\i (00:03:56) trapsize 155
\i (00:03:57) prepopup 0.4857 0.0245
\i (00:03:57) done
\i (00:03:58) zoom out 1
\i (00:03:58) setwindow pcb
\i (00:03:58) zoom out 1.0226 0.5459
\i (00:03:58) trapsize 310
\i (00:03:58) save
\i (00:03:59) fillin yes
\t (00:03:59) Symbol 'll41.psm' created.
\i (00:19:11) save
\i (00:19:11) fillin yes
\t (00:19:12) Symbol 'll41.psm' created.
\i (00:19:15) step pkg map
\i (00:19:16) fillin yes
\i (00:19:19) setwindow form.pkgmap3d
\i (00:19:19) FORM pkgmap3d stplist ll41.STEP
\i (00:19:22) FORM pkgmap3d overlay YES
\i (00:19:25) FORM pkgmap3d offset_z 2
\i (00:19:27) FORM pkgmap3d view_orientation Top
\i (00:19:30) FORM pkgmap3d offset_y -10
\i (00:19:31) FORM pkgmap3d offset_y 0
\i (00:19:33) FORM pkgmap3d offset_x -1
\i (00:19:35) FORM pkgmap3d offset_x 2
\i (00:19:38) FORM pkgmap3d offset_x 1
\i (00:19:39) FORM pkgmap3d offset_x 1.5
\i (00:19:42) FORM pkgmap3d offset_x 1.75
\i (00:19:51) FORM pkgmap3d offset_x 1.8
\i (00:19:55) FORM pkgmap3d view_orientation Back
\i (00:19:58) FORM pkgmap3d offset_z 1
\i (00:20:00) FORM pkgmap3d offset_z 0.9
\i (00:20:02) FORM pkgmap3d offset_z 0.8
\i (00:20:04) FORM pkgmap3d save_current
\i (00:20:05) FORM pkgmap3d done
\i (00:20:07) setwindow pcb
\i (00:20:07) save
\i (00:20:08) fillin yes
\t (00:20:08) Symbol 'll41.psm' created.
\i (00:20:12) 3d
\i (00:20:25) QtSignal pcb3d_SymbolTab pcb3dSymbolTree itemChanged "~All" "|" 0
\i (00:20:25) QtSignal pcb3d_SymbolTab pcb3dSymbolTree itemClicked All
\i (00:20:26) QtSignal pcb3d_SymbolTab pcb3dSymbolTree itemChanged "~All" "|" 2
\i (00:20:26) QtSignal pcb3d_SymbolTab pcb3dSymbolTree itemClicked All
\i (00:20:29) QtSignal pcb3dViewer pcb3dViewer closed
\i (00:20:32) zoom out 1
\i (00:20:32) setwindow pcb
\i (00:20:32) zoom out -1.0505 0.3659
\i (00:20:32) trapsize 621
\i (00:20:32) zoom out 1
\i (00:20:32) setwindow pcb
\i (00:20:32) zoom out -1.0505 0.3659
\i (00:20:32) trapsize 1241
\i (00:20:32) zoom in 1
\i (00:20:32) setwindow pcb
\i (00:20:32) zoom in -1.0505 0.3659
\i (00:20:32) trapsize 621
\i (00:20:32) zoom in 1
\i (00:20:32) setwindow pcb
\i (00:20:32) zoom in -1.0505 0.3659
\i (00:20:32) trapsize 310
\i (00:20:33) zoom in 1
\i (00:20:33) setwindow pcb
\i (00:20:33) zoom in -1.0505 0.3659
\i (00:20:33) trapsize 155
\i (00:20:33) zoom in 1
\i (00:20:33) setwindow pcb
\i (00:20:33) zoom in -1.0505 0.3659
\i (00:20:33) trapsize 78
\i (00:20:33) zoom in 1
\i (00:20:33) setwindow pcb
\i (00:20:33) zoom in -1.0504 0.3659
\i (00:20:33) trapsize 39
\i (00:20:33) zoom out 1
\i (00:20:33) setwindow pcb
\i (00:20:33) zoom out -1.0504 0.3659
\i (00:20:33) trapsize 78
\i (00:20:33) zoom out 1
\i (00:20:33) setwindow pcb
\i (00:20:33) zoom out -1.0503 0.3659
\i (00:20:33) trapsize 155
\i (00:20:33) zoom out 1
\i (00:20:33) setwindow pcb
\i (00:20:33) zoom out -1.0504 0.3659
\i (00:20:33) trapsize 310
\i (00:20:39) shape select
\i (00:20:44) setwindow form.find
\i (00:20:44) FORM find all_off
\i (00:20:45) FORM find all_on
\e (00:20:46) Command not found: deelte
\i (00:20:50) setwindow pcb
\i (00:20:50) color192
\i (00:20:54) QtSignal CVDLayerContainer CVDFilterLayerEntry editingFinished silk
\i (00:20:54) QtSignal CVDLayerContainer CVDVisibilityOff clicked
\i (00:20:55) QtSignal CVDLayerTable VertHeader clickedCheckBox "Silkscreen_Top" 1
\i (00:20:55) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 1 0
\i (00:20:56) QtSignal CVDTabs CVDLayerContainer keyPressEvent 16777248 33554432 false 1
\i (00:20:58) QtSignal CVDLayerContainer CVDFilterLayerEntry editingFinished top
\i (00:20:58) QtSignal CVDLayerTable VertHeader clickedCheckBox Top 1
\i (00:20:58) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 0 0
\i (00:21:00) QtSignal ColorVisibilityDialog CVDOkButton clicked
\i (00:21:05) shape select
\i (00:21:06) pick grid -0.0199 -0.0314
\t (00:21:06) last pick: 0.0000 0.0000
\i (00:21:08) drag_start grid -2.5958 0.1983
\t (00:21:08) last pick: -2.6000 0.1983
\i (00:21:09) drag_stop grid -1.1558 0.1983
\t (00:21:09) No DRC errors detected.
\i (00:21:10) prepopup -0.2993 1.8245
\i (00:21:11) done
\i (00:21:12) color192
\i (00:21:13) QtSignal CVDLayerContainer CVDVisibilityOn clicked
\i (00:21:14) QtSignal ColorVisibilityDialog CVDOkButton clicked
\i (00:21:15) save
\i (00:21:15) fillin yes
\t (00:21:16) Symbol 'll41.psm' created.
\i (00:21:17) 3d
\i (00:21:20) QtSignal pcb3dViewer pcb3dViewer closed
\i (00:21:21) save
\i (00:21:21) fillin yes
\t (00:21:22) Symbol 'll41.psm' created.
\i (00:21:23) exit
\t (00:21:23) Journal end - Sat Aug 3 21:35:09 2024

4
smc/batch_drc.log
View File

@@ -2,9 +2,9 @@
( )
( DRC Update )
( )
( Drawing : f1206.dra )
( Drawing : ll34.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Apr 12 17:55:14 2024 )
( Date/Time : Sat Aug 3 21:11:16 2024 )
( )
(---------------------------------------------------------------------)

27
smc/batch_drc.log,1 Normal file
View File

@@ -0,0 +1,27 @@
(---------------------------------------------------------------------)
( )
( DRC Update )
( )
( Drawing : f1206.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Apr 12 17:55:14 2024 )
( )
(---------------------------------------------------------------------)
========= check shapes 0:00:00
========= check standalone pins 0:00:00
========= check symbols (pins,lines,text) 0:00:00
========= check xnets 0:00:00
========= check nets 0:00:00
========= check standalone branches 0:00:00
========= check standalone filled rectangles 0:00:00
========= check standalone lines 0:00:00
========= check standalone text 0:00:00
========= check standalone rectangles 0:00:00
..... Total number of DRC errors 0
..... DRC update completed, total CPU time 0:00:00
*************************************************************************

29
smc/dangling_lines.rpt Normal file
View File

@@ -0,0 +1,29 @@
(---------------------------------------------------------------------)
( )
( Dangling Line, Via and Antenna Report )
( )
( Drawing : ll41.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 21:35:03 2024 )
( )
(---------------------------------------------------------------------)
Report methodology:
- Dangling lines have at least one end not connected.
- Dangling vias have one or no connection
- Plus are not a test, thieving or netshort property via.
- Antenna vias do not have connections on their start and end layers.
- Plus they are not a thieving vias.
- Optionally, VOLTAGE nets, testvias and through vias can be suppressed with
the environment variable report_antennavia.
- Section may be suppressed by variable report_noantennavia.
- Not part of the current partition.
- To suppress items in dangle report add the OK_DANGLE property to the via
or connect line.
<< Summary >>
Total dangling lines: 0
Total dangling vias: 0
Total antenna vias: 0

29
smc/dangling_lines.rpt,1 Normal file
View File

@@ -0,0 +1,29 @@
(---------------------------------------------------------------------)
( )
( Dangling Line, Via and Antenna Report )
( )
( Drawing : ll41.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 21:33:58 2024 )
( )
(---------------------------------------------------------------------)
Report methodology:
- Dangling lines have at least one end not connected.
- Dangling vias have one or no connection
- Plus are not a test, thieving or netshort property via.
- Antenna vias do not have connections on their start and end layers.
- Plus they are not a thieving vias.
- Optionally, VOLTAGE nets, testvias and through vias can be suppressed with
the environment variable report_antennavia.
- Section may be suppressed by variable report_noantennavia.
- Not part of the current partition.
- To suppress items in dangle report add the OK_DANGLE property to the via
or connect line.
<< Summary >>
Total dangling lines: 0
Total dangling vias: 0
Total antenna vias: 0

4
smc/downrev.log
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : ll34.dra )
( Drawing : ll41.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Jul 28 22:59:48 2024 )
( Date/Time : Sat Aug 3 21:35:08 2024 )
( )
(---------------------------------------------------------------------)

4
smc/downrev.log,1
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : f1812.dra )
( Drawing : ll41.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Jul 28 22:43:54 2024 )
( Date/Time : Sat Aug 3 21:35:02 2024 )
( )
(---------------------------------------------------------------------)

4
smc/downrev.log,2
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : ll34.dra )
( Drawing : ll41.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Jul 28 22:59:48 2024 )
( Date/Time : Sat Aug 3 21:35:08 2024 )
( )
(---------------------------------------------------------------------)

4
smc/downrev.log,3
View File

@@ -2,9 +2,9 @@
( )
( Downrev Design )
( )
( Drawing : ll34.dra )
( Drawing : ll41.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Jul 28 22:59:48 2024 )
( Date/Time : Sat Aug 3 21:35:08 2024 )
( )
(---------------------------------------------------------------------)

BIN
smc/ll34.dra
View File

Binary file not shown.

2
smc/ll34.log
View File

@@ -4,7 +4,7 @@
( )
( Drawing : ll34.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Jul 28 22:59:48 2024 )
( Date/Time : Sat Aug 3 21:12:15 2024 )
( )
(---------------------------------------------------------------------)

23
smc/ll34.log,1 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : ll34.dra )
( Software Version : 17.4S035 )
( Date/Time : Sun Jul 28 22:59:48 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = ll34.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
smc/ll34.log,2 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : ll34.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 21:11:56 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = ll34.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
smc/ll34.pad
View File

Binary file not shown.

BIN
smc/ll34.psm
View File

Binary file not shown.

BIN
smc/ll41.dra Normal file
View File

Binary file not shown.

23
smc/ll41.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : ll41.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 21:35:08 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = ll41.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
smc/ll41.log,1 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : ll41.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 21:32:58 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = ll41.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
smc/ll41.log,2 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : ll41.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 21:33:54 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = ll41.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

23
smc/ll41.log,3 Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : ll41.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Aug 3 21:35:02 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = ll41.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
smc/ll41.pad Normal file
View File

Binary file not shown.

BIN
smc/ll41.psm Normal file
View File

Binary file not shown.

2
smc/master.tag
View File

@@ -1 +1 @@
ll34.dra
ll41.dra

72
smc/padstack_editor.jrl
View File

@@ -1,47 +1,29 @@
\t (00:00:01) padstack_editor 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:01) Journal start - Sun Jul 28 22:28:03 2024
\t (00:00:01) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=14944 CPUs=12
\t (00:00:01) CmdLine= d:\software\cadence\spb_17.4\tools\bin\padstack_editor.exe D:\workspace\GitHub\pcb_lib\smc\0201.pad
\t (00:00:01) Journal start - Sat Aug 3 21:12:37 2024
\t (00:00:01) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=21640 CPUs=12
\t (00:00:01) CmdLine= d:\software\cadence\spb_17.4\tools\bin\padstack_editor.exe D:\workspace\GitHub\pcb_lib\smc\ll41.pad
\t (00:00:01)
\d (00:00:03) QtSignal MainWindow New triggered
\d (00:00:06) QtSignal fileNewDialog dirPath editingFinished 1812
\d (00:00:09) QtSignal fileNewDialog dataCombo CurrentIndexChanged "SMD Pin"
\d (00:00:10) QtSignal fileNewDialog OK clicked
\d (00:00:11) QtSignal GuidedTabsParent NewPads currentRowChanged 1
\d (00:00:11) QtSignal GuidedTabsParent NewPads itemSelectionChanged Square
\d (00:00:11) QtSignal GuidedTabsParent NewPads itemClicked Square
\d (00:00:12) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:15) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
\d (00:00:15) QtSignal 1
\d (00:00:20) QtSignal GuidedTabsParent GuidedTabs currentChanged Start
\d (00:00:22) QtSignal GuidedTabsParent NewPads currentRowChanged 3
\d (00:00:22) QtSignal GuidedTabsParent NewPads itemSelectionChanged Rectangle
\d (00:00:22) QtSignal GuidedTabsParent NewPads itemClicked Rectangle
\d (00:00:24) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:25) QtSignal GuidedDesignLayersTab LayersTable cellClicked 0 "Regular Pad" 0 2
\d (00:00:29) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:29) QtSignal 1
\d (00:00:30) QtSignal GuidedDesignLayersTab PadWidth editingFinished "1.7800"
\d (00:00:39) QtSignal GuidedDesignLayersTab PadHeight editingFinished "3.2000"
\d (00:00:48) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:51) QtSignal GuidedMaskLayersTab LayersTable cellClicked 0 Pad 0 1
\d (00:00:52) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:52) QtSignal 1
\d (00:00:54) QtSignal GuidedMaskLayersTab PadWidth editingFinished "1.7800"
\d (00:01:04) QtSignal GuidedMaskLayersTab PadWidth editingFinished "1.8800"
\d (00:01:07) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:01:07) QtSignal 1
\d (00:01:10) QtSignal GuidedMaskLayersTab PadHeight editingFinished "3.3000"
\d (00:01:14) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 Pad
\d (00:01:14) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 Pad 2 1
\d (00:01:16) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:01:16) QtSignal 1
\d (00:01:17) QtSignal GuidedMaskLayersTab PadWidth editingFinished "1.7800"
\d (00:01:19) QtSignal GuidedMaskLayersTab PadHeight editingFinished "3.2000"
\d (00:01:26) QtSignal GuidedTabsParent GuidedTabs currentChanged Options
\d (00:01:27) QtSignal GuidedTabsParent GuidedTabs currentChanged Summary
\d (00:01:28) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:01:28) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:01:35) QtSignal MainWindow Save triggered
\w (00:01:35) WARNING(SPMHUT-48): Scaled value has been rounded off.
\t (00:01:37) Journal end - Sun Jul 28 22:29:39 2024
\d (00:00:35) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:36) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:36) QtSignal 1
\d (00:00:38) QtSignal GuidedDesignLayersTab PadWidth editingFinished "1.2500"
\d (00:00:38) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
\d (00:00:38) QtSignal 1
\d (00:00:40) QtSignal GuidedDesignLayersTab PadHeight editingFinished "2.0000"
\d (00:00:41) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
\d (00:00:41) QtSignal 1
\d (00:00:43) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:00:44) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:44) QtSignal 1
\d (00:00:48) QtSignal GuidedMaskLayersTab PadWidth editingFinished "1.3000"
\d (00:00:50) QtSignal GuidedMaskLayersTab PadHeight editingFinished "2.0500"
\d (00:00:51) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 1 Pad
\d (00:00:51) QtSignal GuidedMaskLayersTab LayersTable cellClicked 1 Pad 1 1
\d (00:00:52) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 Pad
\d (00:00:52) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 Pad 2 1
\d (00:00:53) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:00:53) QtSignal 1
\d (00:00:54) QtSignal GuidedMaskLayersTab PadWidth editingFinished "1.2500"
\d (00:00:54) QtSignal GuidedMaskLayersTab PadHeight editingFinished "2.0000"
\d (00:00:56) QtSignal MainWindow Save triggered
\t (00:00:57) Journal end - Sat Aug 3 21:13:33 2024

39
smc/padstack_editor.jrl,1
View File

@@ -1,14 +1,29 @@
\t (00:00:01) padstack_editor 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:01) Journal start - Sun Jul 28 22:27:40 2024
\t (00:00:01) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=21076 CPUs=12
\t (00:00:01) CmdLine= d:\software\cadence\spb_17.4\tools\bin\padstack_editor.exe D:\workspace\GitHub\pcb_lib\smc\0201.pad
\t (00:00:01) Journal start - Sat Aug 3 21:05:27 2024
\t (00:00:01) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=7456 CPUs=12
\t (00:00:01) CmdLine= d:\software\cadence\spb_17.4\tools\bin\padstack_editor.exe D:\workspace\GitHub\pcb_lib\smc\ll34.pad
\t (00:00:01)
\d (00:00:03) QtSignal MainWindow New triggered
\d (00:00:07) QtSignal fileNewDialog dirPath editingFinished 1812
\d (00:00:08) QtSignal fileNewDialog dataCombo CurrentIndexChanged "SMD Pin"
\d (00:00:10) QtSignal fileNewDialog OK clicked
\d (00:00:12) QtSignal GuidedTabsParent NewPads currentRowChanged 1
\d (00:00:12) QtSignal GuidedTabsParent NewPads itemSelectionChanged Square
\d (00:00:12) QtSignal GuidedTabsParent NewPads itemClicked Square
\d (00:00:21) QtFillin No
\t (00:00:21) Journal end - Sun Jul 28 22:28:01 2024
\d (00:00:06) QtSignal GuidedTabsParent GuidedTabs currentChanged Drill
\d (00:00:07) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:00:13) QtSignal GuidedDesignLayersTab LayersTable cellClicked 0 "Regular Pad" 0 2
\d (00:00:29) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
\d (00:00:29) QtSignal 1
\d (00:00:31) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777251 134217728 false +
\d (00:00:31) QtSignal 1
\d (00:03:04) QtSignal GuidedTabsParent GuidedDesignLayersTab keyPressEvent 16777248 33554432 false +
\d (00:03:04) QtSignal 1
\d (00:03:05) QtSignal GuidedDesignLayersTab PadHeight editingFinished "1.0000"
\d (00:03:08) QtSignal GuidedTabsParent GuidedTabs currentChanged "Mask Layers"
\d (00:03:09) QtSignal GuidedMaskLayersTab LayersTable cellClicked 0 Pad 0 1
\d (00:03:11) QtSignal GuidedMaskLayersTab PadHeight editingFinished "1.5500"
\d (00:03:13) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 2 Pad
\d (00:03:13) QtSignal GuidedMaskLayersTab LayersTable cellClicked 2 Pad 2 1
\d (00:03:17) QtSignal GuidedTabsParent GuidedMaskLayersTab keyPressEvent 16777248 33554432 false +
\d (00:03:17) QtSignal 1
\d (00:03:17) QtSignal GuidedMaskLayersTab PadHeight editingFinished "1.0000"
\d (00:03:19) QtSignal GuidedMaskLayersTab LayersTable itemSelectionChanged 0 Pad
\d (00:03:19) QtSignal GuidedMaskLayersTab LayersTable cellClicked 0 Pad 0 1
\d (00:03:21) QtSignal GuidedMaskLayersTab PadHeight editingFinished "1.0500"
\d (00:03:24) QtSignal GuidedTabsParent GuidedTabs currentChanged "Design Layers"
\d (00:03:27) QtSignal MainWindow Save triggered
\t (00:03:28) Journal end - Sat Aug 3 21:08:54 2024

8
smc/param_read.log
View File

@@ -2,15 +2,15 @@
( )
( Parameter File READ )
( )
( Drawing : smb.dra )
( Drawing : ll41.dra )
( Software Version : 17.4S035 )
( Date/Time : Thu Jul 11 02:24:02 2024 )
( Date/Time : Sat Aug 3 21:14:15 2024 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/¹¤×÷¿â/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : smb.dra
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : ll41.dra
Reading...parameter_header:
Reading...db_common_type:

128
smc/param_read.log,1 Normal file
View File

@@ -0,0 +1,128 @@
(---------------------------------------------------------------------)
( )
( Parameter File READ )
( )
( Drawing : smb.dra )
( Software Version : 17.4S035 )
( Date/Time : Thu Jul 11 02:24:02 2024 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/¹¤×÷¿â/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : smb.dra
Reading...parameter_header:
Reading...db_common_type:
Reading...grid_parms_type:
WARNING: The value of element <etchcount> is not equal to the number of
user defined subclass under ETCH class.
Reading...UnusedPadsSuppressionSettings:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
WARNING: Unmatched Data - Field Name: subclass , Value: "SIGNEDTOP"
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
WARNING: Unmatched Data - Field Name: subclass , Value: "SIGNEDBOTTOM"
Reading...art_class_type:
Reading...art_class_type:
Reading...color_table_table:
Reading...ColorParmType:
Reading...profileCustomColors:
Reading...text_size_table:
Reading...drf_parm_type:
Reading...av_parm_type:
Reading...dynfill_parm_type:
Reading...probe_parm_type:
Reading...ifp_parm_type:
Reading...ministat_parm_type:
WARNING: Unmatched Data - Field Name: acon_active_sc , Value: "SIGNEDTOP"
Reading...ats_parm_type:
Reading...placement_parameter_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
..... Total number of errors: 0.
..... Total number of warnings: 4.

128
smc/param_read.log,2 Normal file
View File

@@ -0,0 +1,128 @@
(---------------------------------------------------------------------)
( )
( Parameter File READ )
( )
( Drawing : sma.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Aug 2 04:07:33 2024 )
( )
(---------------------------------------------------------------------)
Paramfile Name : D:/workspace/GitHub/pcb_lib/XerolySkinner.prm
Layout Name : sma.dra
Reading...parameter_header:
Reading...db_common_type:
Reading...grid_parms_type:
WARNING: The value of element <etchcount> is not equal to the number of
user defined subclass under ETCH class.
Reading...UnusedPadsSuppressionSettings:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
WARNING: Unmatched Data - Field Name: subclass , Value: "SIGNEDTOP"
Reading...art_class_type:
Reading...art_class_type:
Reading...artwork_film:
Reading...art_film_type:
Reading...art_film_block_type:
Reading...art_class_type:
WARNING: Unmatched Data - Field Name: subclass , Value: "SIGNEDBOTTOM"
Reading...art_class_type:
Reading...art_class_type:
Reading...color_table_table:
Reading...ColorParmType:
Reading...profileCustomColors:
Reading...text_size_table:
Reading...drf_parm_type:
Reading...av_parm_type:
Reading...dynfill_parm_type:
Reading...probe_parm_type:
Reading...ifp_parm_type:
Reading...ministat_parm_type:
WARNING: Unmatched Data - Field Name: acon_active_sc , Value: "SIGNEDTOP"
Reading...ats_parm_type:
Reading...placement_parameter_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
Reading...backdrill_parm_type:
..... Total number of errors: 0.
..... Total number of warnings: 4.

BIN
smc/r0805.dra
View File

Binary file not shown.

Some files were not shown because too many files have changed in this diff Show More