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XerolySkinner
2024-03-31 21:26:49 +08:00
parent 619ad9e57a
commit e5eacc6a0c
58 changed files with 210853 additions and 38319 deletions
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49
ind_smd/allegro.jrl Normal file
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\t (00:00:04) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:04) Journal start - Sat Mar 30 19:30:59 2024
\t (00:00:04) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=29116 CPUs=12
\t (00:00:04) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\ind_smd\i0630.dra
\t (00:00:04)
(00:00:04) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged i0630
\d (00:00:04) Design opened: D:/workspace/GitHub/pcb_lib/ind_smd/i0630.dra
\i (00:00:05) trapsize 1071
\i (00:00:05) trapsize 1100
\i (00:00:05) trapsize 1071
\i (00:00:06) trapsize 940
\i (00:00:06) trapsize 965
\i (00:00:06) trapsize 993
\t (00:00:06) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:06) trapsize 1274
\i (00:00:07) zoom in 1
\i (00:00:07) setwindow pcb
\i (00:00:07) zoom in -0.8265 1.7713
\i (00:00:07) trapsize 637
\i (00:00:07) zoom in 1
\i (00:00:07) setwindow pcb
\i (00:00:07) zoom in -0.8265 1.7713
\i (00:00:07) trapsize 319
\i (00:00:07) zoom in 1
\i (00:00:07) setwindow pcb
\i (00:00:07) zoom in -0.8265 1.7713
\i (00:00:07) trapsize 159
\i (00:00:08) zoom out 1
\i (00:00:08) setwindow pcb
\i (00:00:08) zoom out -0.6194 1.6598
\i (00:00:08) trapsize 319
\i (00:00:08) zoom out 1
\i (00:00:08) setwindow pcb
\i (00:00:08) zoom out -0.6195 1.6598
\i (00:00:08) trapsize 637
\i (00:00:09) color192
\i (00:00:14) QtSignal CVDLayerContainer CVDFilterLayerEntry editingFinished place
\i (00:00:14) QtSignal CVDLayerContainer CVDVisibilityOff clicked
\i (00:00:15) QtSignal CVDLayerTable VertHeader clickedCheckBox "Place_Bound_Top" 1
\i (00:00:15) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 2 0
\i (00:00:18) QtSignal CVDLayerContainer CVDVisibilityOn clicked
\i (00:00:19) QtSignal ColorVisibilityDialog CVDOkButton clicked
\i (00:00:20) exit
\e (00:00:20) Do you want to save the changes you made to i0630.dra?
\i (00:00:20) fillin yes
\t (00:00:21) Symbol 'i0630.psm' created.
\t (00:00:21) Journal end - Sat Mar 30 19:31:16 2024

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ind_smd/allegro.jrl,1 Normal file
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\t (00:00:03) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:03) Journal start - Sat Mar 30 19:29:45 2024
\t (00:00:03) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=33704 CPUs=12
\t (00:00:03) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\ind_smd\i0630.dra
\t (00:00:03)
(00:00:03) Loading axlcore.cxt
\t (00:00:03) Opening existing design...
\i (00:00:03) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged i0630
\d (00:00:03) Design opened: D:/workspace/GitHub/pcb_lib/ind_smd/i0630.dra
\i (00:00:04) trapsize 1071
\i (00:00:04) trapsize 1100
\i (00:00:04) trapsize 1071
\i (00:00:04) trapsize 940
\i (00:00:04) trapsize 965
\i (00:00:04) trapsize 993
\t (00:00:04) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:05) trapsize 1274
\i (00:00:07) zoom in 1
\i (00:00:07) setwindow pcb
\i (00:00:07) zoom in -0.3423 0.9303
\i (00:00:07) trapsize 637
\i (00:00:07) zoom in 1
\i (00:00:07) setwindow pcb
\i (00:00:07) zoom in -0.3423 0.9303
\i (00:00:07) trapsize 319
\i (00:00:07) zoom in 1
\i (00:00:07) setwindow pcb
\i (00:00:07) zoom in -0.3422 0.9303
\i (00:00:07) trapsize 159
\i (00:00:09) exit
\t (00:00:09) Journal end - Sat Mar 30 19:29:51 2024

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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : i0630.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 30 19:31:16 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

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ind_smd/downrev.log,1 Normal file
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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : i0630.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 30 19:31:15 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
ind_smd/downrev.log,2 Normal file
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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : i0630.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 30 19:31:15 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

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ind_smd/i0630.log Normal file
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(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : i0630.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 30 19:31:16 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/ind_smd
Name = i0630.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

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ind_smd/i0630.psm
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