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XerolySkinner
2024-03-29 01:32:55 +08:00
parent c8bfe69ca9
commit 619ad9e57a
11 changed files with 18839 additions and 0 deletions
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3D/ID8.STEP Normal file
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smc/allegro.jrl Normal file
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\t (00:00:05) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:05) Journal start - Fri Mar 29 01:30:57 2024
\t (00:00:05) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=20912 CPUs=12
\t (00:00:05) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\smc\id8.dra
\t (00:00:05)
(00:00:05) Loading axlcore.cxt
\t (00:00:05) Opening existing design...
\i (00:00:05) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged id8
\d (00:00:05) Design opened: D:/workspace/GitHub/pcb_lib/smc/id8.dra
\t (00:00:06) Grids are drawn 0.2002, 0.2002 apart for enhanced viewing.
\i (00:00:06) trapsize 1340
\i (00:00:06) trapsize 1375
\i (00:00:07) trapsize 1340
\i (00:00:07) trapsize 1175
\i (00:00:08) trapsize 1207
\i (00:00:08) trapsize 1241
\t (00:00:08) Grids are drawn 0.2002, 0.2002 apart for enhanced viewing.
\i (00:00:08) trapsize 1274
\i (00:00:13) step pkg map
\i (00:00:14) fillin yes
\i (00:00:21) setwindow form.pkgmap3d
\i (00:00:21) FORM pkgmap3d stplist ID8.STEP
\i (00:00:23) FORM pkgmap3d overlay YES
\i (00:00:25) FORM pkgmap3d view_orientation 'Front Right'
\i (00:00:28) FORM pkgmap3d view_orientation Top
\i (00:00:32) FORM pkgmap3d view_orientation 'Front Right'
\i (00:00:34) FORM pkgmap3d save_current
\i (00:00:38) FORM pkgmap3d done
\i (00:00:39) setwindow pcb
\i (00:00:39) exit
\e (00:00:39) Do you want to save the changes you made to id8.dra?
\i (00:00:39) fillin yes
\t (00:00:40) Symbol 'id8.psm' created.
\t (00:00:41) Journal end - Fri Mar 29 01:31:32 2024

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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : id8.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Mar 29 01:31:32 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : id8.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Mar 29 01:31:31 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

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(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : id8.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Mar 29 01:31:31 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

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(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : id8.dra )
( Software Version : 17.4S035 )
( Date/Time : Fri Mar 29 01:31:32 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/smc
Name = id8.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

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smc/stepFacetFiles4Map/ID8.xml Normal file
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smc/stepFacetFiles4Map/stepFileInfo.txt
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#STEP_FILE ! FILE_SIZE ! MOD_TIME
ID8.STEP ! 320759 ! 1711647018
C0603.stp ! 74996 ! 1710578258
SMA-DO-214AC.step ! 213070 ! 1710578258
SMC.step ! 207133 ! 1710578258

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smc/stepFacetFiles4Map/stepFileInfo.txt,1
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@@ -6,6 +6,7 @@ SMC.step ! 207133 ! 1710578258
TS-POINT.STEP ! 23849 ! 1710578258
SOD-123FL.step ! 331135 ! 1710578258
ll34.step ! 547277 ! 1711502096
sod-323.step ! 94263 ! 1711640831
LED_0603_G.STEP ! 178570 ! 1710578258
KEY_SOT_P2.step ! 151224 ! 1710578258
RES_CRCW_2512.step ! 33456 ! 1568096060