xerolyskinner/pcb_lib
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

更新一些封装

Browse Source
This commit is contained in:
XerolySkinner
2024-03-23 02:02:12 +08:00
parent cdf1d1189c
commit fc470544d4
26 changed files with 138 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

BIN
basic_lib/BASIC_OBJ.OLB
View File

Binary file not shown.

BIN
basic_lib/BASIC_OBJ.OLBlck Normal file
View File

Binary file not shown.

BIN
basic_lib/BASIC_OBJ_0.OBK
View File

Binary file not shown.

25
basic_lib/basic_obj.opj
View File

@@ -27,7 +27,10 @@
(GlobalState
(FileView
(Path "Design Resources")
(Select "Design Resources" ".\basic_obj.olb"))
(Path "Design Resources"
"d:\workspace\github\pcb_lib\basic_lib\basic_obj.olb")
(Select "Design Resources"
"d:\workspace\github\pcb_lib\basic_lib\basic_obj.olb"))
(HierarchyView)
(Doc
(Type "COrCapturePMDoc")
@@ -37,7 +40,7 @@
(Doc
(Type "COrPrmBrowserDoc")
(Frame
(Placement "44 0 1 -1 -1 -8 -31 5 1099 28 555"))
(Placement "44 0 1 -1 -1 -1 -1 5 1099 28 555"))
(Path "D:\WORKSPACE\GITHUB\PCB_LIB\BASIC_LIB\BASIC_OBJ.OLB")
(Package "8MHZ")
(PartType "1"))
@@ -51,14 +54,14 @@
(Doc
(Type "COrPrmBrowserDoc")
(Frame
(Placement "44 0 1 -1 -1 -1 -1 5 1099 28 555"))
(Placement "44 0 1 -1 -1 -8 -31 5 1099 28 555"))
(Path "D:\WORKSPACE\GITHUB\PCB_LIB\BASIC_LIB\BASIC_OBJ.OLB")
(Package "SS310")
(PartType "1"))
(Doc
(Type "COrPrmBrowserDoc")
(Frame
(Placement "44 0 1 -1 -1 -1 -1 5 1099 28 555"))
(Placement "44 0 1 -1 -1 -8 -31 5 1099 28 555"))
(Path "D:\WORKSPACE\GITHUB\PCB_LIB\BASIC_LIB\BASIC_OBJ.OLB")
(Package "SWITCH")
(PartType "1"))
@@ -75,18 +78,4 @@
(Placement "44 0 1 -1 -1 -8 -31 5 1099 28 555"))
(Path "D:\WORKSPACE\GITHUB\PCB_LIB\BASIC_LIB\BASIC_OBJ.OLB")
(Package "UCC27517")
(PartType "1"))
(Doc
(Type "COrPrmBrowserDoc")
(Frame
(Placement "44 0 1 -1 -1 -8 -31 5 1099 28 555"))
(Path "D:\WORKSPACE\GITHUB\PCB_LIB\BASIC_LIB\BASIC_OBJ.OLB")
(Package "UCC27710")
(PartType "1"))
(Doc
(Type "COrPrmBrowserDoc")
(Frame
(Placement "44 0 1 -1 -1 -8 -31 5 1099 28 555"))
(Path "D:\WORKSPACE\GITHUB\PCB_LIB\BASIC_LIB\BASIC_OBJ.OLB")
(Package "XML-DEBUG")
(PartType "1"))))

BIN
cap_smd/unnamed.brd Normal file
View File

Binary file not shown.

BIN
chip/lqfp48.dra Normal file
View File

Binary file not shown.

BIN
chip/lqfp48.pad Normal file
View File

Binary file not shown.

BIN
chip/lqfp48.psm Normal file
View File

Binary file not shown.

BIN
chip/ufqfpn28.dra Normal file
View File

Binary file not shown.

BIN
chip/ufqfpn28.psm Normal file
View File

Binary file not shown.

BIN
chip/ufqfpn28_1_1.dra Normal file
View File

Binary file not shown.

BIN
chip/ufqfpn28_1_1.pad Normal file
View File

Binary file not shown.

BIN
chip/ufqfpn28_1_1.ssm Normal file
View File

Binary file not shown.

BIN
chip/ufqfpn28_1_2.dra Normal file
View File

Binary file not shown.

BIN
chip/ufqfpn28_1_2.pad Normal file
View File

Binary file not shown.

BIN
chip/ufqfpn28_1_2.ssm Normal file
View File

Binary file not shown.

BIN
chip/ufqfpn28_2.pad Normal file
View File

Binary file not shown.

38
thr/allegro.jrl Normal file
View File

@@ -0,0 +1,38 @@
\t (00:00:04) allegro 17.4 S035 Windows SPB 64-bit Edition
\t (00:00:04) Journal start - Sat Mar 23 01:49:19 2024
\t (00:00:04) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=26640 CPUs=12
\t (00:00:04) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\thr\thr_dip_2x5.dra
\t (00:00:04)
(00:00:04) Loading axlcore.cxt
\t (00:00:04) Opening existing design...
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "thr_dip_2x5"
\d (00:00:04) Design opened: D:/workspace/GitHub/pcb_lib/thr/thr_dip_2x5.dra
\i (00:00:04) trapsize 1071
\i (00:00:05) trapsize 1100
\i (00:00:05) trapsize 1071
\i (00:00:05) trapsize 1241
\t (00:00:05) Grids are drawn 0.2000, 0.2000 apart for enhanced viewing.
\i (00:00:06) trapsize 1274
\i (00:00:06) updateport CVPane
\i (00:00:06) shapeedit
\i (00:00:15) replace padstack
\i (00:00:16) setwindow form.mini
\i (00:00:16) FORM mini oldname_browse
\i (00:00:19) fillin "Thr-1r6_0R9"
\i (00:00:20) FORM mini newname_browse
\t (00:00:33) No valid name selected.
\i (00:00:35) fillin "Thr-1r02_1R8"
\i (00:00:37) FORM mini replace
\t (00:00:37) Done, updated padstack.
\t (00:00:37) 10 out of 10 old padstack THR-1R6_0R9 were replaced with new padstack THR-1R02_1R8.
\i (00:00:39) setwindow pcb
\i (00:00:39) pick grid 0.1418 -7.9086
\t (00:00:39) last pick: 0.1000 -7.9000
\i (00:00:40) save
\t (00:00:40) Performing DRC...
\t (00:00:40) No DRC errors detected.
\i (00:00:41) fillin yes
\t (00:00:42) Symbol 'thr_dip_2x5.psm' created.
\i (00:00:42) shapeedit
\i (00:00:43) exit
\t (00:00:43) Journal end - Sat Mar 23 01:49:59 2024

27
thr/batch_drc.log Normal file
View File

@@ -0,0 +1,27 @@
(---------------------------------------------------------------------)
( )
( DRC Update )
( )
( Drawing : thr_dip_2x5.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 23 01:49:55 2024 )
( )
(---------------------------------------------------------------------)
========= check shapes 0:00:00
========= check standalone pins 0:00:00
========= check symbols (pins,lines,text) 0:00:00
========= check xnets 0:00:00
========= check nets 0:00:00
========= check standalone branches 0:00:00
========= check standalone filled rectangles 0:00:00
========= check standalone lines 0:00:00
========= check standalone text 0:00:00
========= check standalone rectangles 0:00:00
..... Total number of DRC errors 0
..... DRC update completed, total CPU time 0:00:00
*************************************************************************

14
thr/downrev.log Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : thr_dip_2x5.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 23 01:49:57 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
thr/downrev.log,1 Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : thr_dip_2x5.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 23 01:49:57 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

14
thr/downrev.log,2 Normal file
View File

@@ -0,0 +1,14 @@
(---------------------------------------------------------------------)
( )
( Downrev Design )
( )
( Drawing : thr_dip_2x5.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 23 01:49:57 2024 )
( )
(---------------------------------------------------------------------)
Changes made to design for 17.2 compatibility.

1
thr/master.tag Normal file
View File

@@ -0,0 +1 @@
thr_dip_2x5.dra

BIN
thr/thr_dip_2x5.dra
View File

Binary file not shown.

23
thr/thr_dip_2x5.log Normal file
View File

@@ -0,0 +1,23 @@
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : thr_dip_2x5.dra )
( Software Version : 17.4S035 )
( Date/Time : Sat Mar 23 01:49:57 2024 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = D:/workspace/GitHub/pcb_lib/thr
Name = thr_dip_2x5.psm
User = XerolySkinner
Machine = LAPTOP-XEROLYSK
Create symbol started.
Create symbol completed.

BIN
thr/thr_dip_2x5.psm
View File

Binary file not shown.