35 lines
1.4 KiB
Plaintext
35 lines
1.4 KiB
Plaintext
\t (00:00:02) allegro 17.4 S035 Windows SPB 64-bit Edition
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\t (00:00:02) Journal start - Fri Aug 2 06:02:52 2024
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\t (00:00:02) Host=LAPTOP-XEROLYSK User=XerolySkinner Pid=12676 CPUs=12
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\t (00:00:02) CmdLine= d:\software\cadence\spb_17.4\tools\bin\allegro.exe D:\workspace\GitHub\pcb_lib\chip\sop-16.dra
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\t (00:00:02)
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(00:00:02) Loading axlcore.cxt
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\t (00:00:02) Opening existing design...
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\i (00:00:02) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "sop-16"
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\d (00:00:02) Design opened: D:/workspace/GitHub/pcb_lib/chip/sop-16.dra
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\t (00:00:02) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
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\i (00:00:02) trapsize 43
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\i (00:00:02) trapsize 44
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\i (00:00:03) trapsize 43
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\i (00:00:03) trapsize 38
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\i (00:00:03) trapsize 39
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\i (00:00:03) trapsize 40
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\t (00:00:03) Grids are drawn 0.040, 0.040 apart for enhanced viewing.
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\i (00:00:03) trapsize 41
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\i (00:00:06) step pkg map
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\i (00:00:06) fillin yes
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\i (00:00:12) setwindow form.pkgmap3d
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\i (00:00:12) FORM pkgmap3d stplist SOP-16.STEP
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\i (00:00:15) FORM pkgmap3d overlay YES
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\i (00:00:16) FORM pkgmap3d hide_board YES
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\i (00:00:17) FORM pkgmap3d hide_board NO
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\i (00:00:20) FORM pkgmap3d view_orientation Top
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\i (00:00:23) FORM pkgmap3d save_current
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\i (00:00:24) FORM pkgmap3d done
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\i (00:00:27) setwindow pcb
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\i (00:00:27) save
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\i (00:00:27) fillin yes
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\t (00:00:27) Symbol 'sop-16.psm' created.
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\i (00:00:28) exit
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\t (00:00:28) Journal end - Fri Aug 2 06:03:18 2024
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